4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#------------------------------------------------------------------------------
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#*
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#* Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#* This program and the accompanying materials
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#* are licensed and made available under the terms and conditions of the BSD License
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#* which accompanies this distribution. The full text of the license may be found at
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#* http://opensource.org/licenses/bsd-license.php
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#*
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#*
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#*
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#------------------------------------------------------------------------------
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync# Float control word initial value:
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync# all exceptions masked, double-precision, round-to-nearest
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncASM_PFX(mFpuControlWord): .word 0x027F
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync# Multimedia-extensions control word:
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync# all exceptions masked, round-to-nearest, flush to zero for masked underflow
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncASM_PFX(mMmxControlWord): .long 0x01F80
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync# Initializes floating point units for requirement of UEFI specification.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync# This function initializes floating-point control word to 0x027F (all exceptions
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync# masked,double-precision, round-to-nearest) and multimedia-extensions control word
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync# (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync# for masked underflow).
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncASM_PFX(InitializeFloatingPointUnits):
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync pushl %ebx
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync #
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync # Initialize floating point units
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync #
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync finit
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync fldcw ASM_PFX(mFpuControlWord)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync #
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync # whether the processor supports SSE instruction.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync #
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync movl $1, %eax
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync cpuid
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync btl $25, %edx
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync jnc Done
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync #
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync # Set OSFXSR bit 9 in CR4
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync #
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync movl %cr4, %eax
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync or $0x200, %eax
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync movl %eax, %cr4
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync #
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync # The processor should support SSE instruction and we can use
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync # ldmxcsr instruction
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync #
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ldmxcsr ASM_PFX(mMmxControlWord)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncDone:
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync popl %ebx
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ret
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#END
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync