LocalApic.h revision 4fd606d1f5abe38e1f42c38de1d2e895166bd0f4
/** @file
IA32 Local APIC Definitions.
Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __LOCAL_APIC_H__
#define __LOCAL_APIC_H__
//
// Definitions for IA32 architectural MSRs
//
#define MSR_IA32_APIC_BASE_ADDRESS 0x1B
//
// Definitions for CPUID instruction
//
#define CPUID_VERSION_INFO 0x1
#define CPUID_EXTENDED_FUNCTION 0x80000000
#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
//
// Definition for Local APIC registers and related values
//
#define XAPIC_ID_OFFSET 0x20
#define XAPIC_VERSION_OFFSET 0x30
#define XAPIC_EOI_OFFSET 0x0b0
#define XAPIC_ICR_DFR_OFFSET 0x0e0
#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0
#define XAPIC_ICR_LOW_OFFSET 0x300
#define XAPIC_ICR_HIGH_OFFSET 0x310
#define XAPIC_LVT_TIMER_OFFSET 0x320
#define XAPIC_LVT_LINT0_OFFSET 0x350
#define XAPIC_LVT_LINT1_OFFSET 0x360
#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380
#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390
#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0
#define X2APIC_MSR_BASE_ADDRESS 0x800
#define X2APIC_MSR_ICR_ADDRESS 0x830
#define LOCAL_APIC_DELIVERY_MODE_FIXED 0
#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
#define LOCAL_APIC_DELIVERY_MODE_SMI 2
#define LOCAL_APIC_DELIVERY_MODE_NMI 4
#define LOCAL_APIC_DELIVERY_MODE_INIT 5
#define LOCAL_APIC_DELIVERY_MODE_STARTUP 6
#define LOCAL_APIC_DELIVERY_MODE_EXTINT 7
#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1
typedef union {
struct {
UINT32 ApicBaseLow:20; ///< APIC Base physical address. The actual field width depends on physical address width.
} Bits;
//
// Local APIC Version Register.
//
typedef union {
struct {
} Bits;
//
// Low half of Interrupt Command Register (ICR).
//
typedef union {
struct {
UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.
UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt.
} Bits;
//
// High half of Interrupt Command Register (ICR)
//
typedef union {
struct {
} Bits;
//
// Spurious-Interrupt Vector Register (SVR)
//
typedef union {
struct {
} Bits;
//
// Divide Configuration Register (DCR)
//
typedef union {
struct {
} Bits;
//
// LVT Timer Register
//
typedef union {
struct {
} Bits;
//
//
typedef union {
struct {
UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.
} Bits;
//
// MSI Address Register
//
typedef union {
struct {
} Bits;
//
// MSI Address Register
//
typedef union {
struct {
} Bits;
#endif