4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Public include file for Local APIC library.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Local APIC library assumes local APIC is enabled. It does not
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync handles cases where local APIC is disabled.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This program and the accompanying materials
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync are licensed and made available under the terms and conditions of the BSD License
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync which accompanies this distribution. The full text of the license may be found at
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Get the current local APIC mode.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If local APIC is disabled, then ASSERT.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Set the current local APIC mode.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If the specified local APIC mode is not valid, then ASSERT.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If the specified local APIC mode can't be set as current, then ASSERT.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param ApicMode APIC mode to be set.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync In xAPIC mode, the initial local APIC ID is 8-bit, and may be different from current APIC ID.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync the 32-bit local APIC ID is returned as initial APIC ID.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return 32-bit initial local APIC ID of the executing processor.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Get the local APIC ID of the executing processor.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return 32-bit local APIC ID of the executing processor.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Get the value of the local APIC version register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return the value of the local APIC version register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Send a Fixed IPI to a specified target processor.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function returns after the IPI has been accepted by the target processor.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param ApicId The local APIC ID of the target processor.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Vector The vector number of the interrupt being sent.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Send a Fixed IPI to all processors excluding self.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function returns after the IPI has been accepted by the target processors.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Vector The vector number of the interrupt being sent.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Send a SMI IPI to a specified target processor.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function returns after the IPI has been accepted by the target processor.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param ApicId Specify the local APIC ID of the target processor.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Send a SMI IPI to all processors excluding self.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function returns after the IPI has been accepted by the target processors.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Send an INIT IPI to a specified target processor.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function returns after the IPI has been accepted by the target processor.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param ApicId Specify the local APIC ID of the target processor.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Send an INIT IPI to all processors excluding self.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function returns after the IPI has been accepted by the target processors.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function returns after the IPI has been accepted by the target processor.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if StartupRoutine >= 1M, then ASSERT.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if StartupRoutine is not multiple of 4K, then ASSERT.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param ApicId Specify the local APIC ID of the target processor.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartupRoutine Points to a start-up routine which is below 1M physical
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync address and 4K aligned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function returns after the IPI has been accepted by the target processors.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if StartupRoutine >= 1M, then ASSERT.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if StartupRoutine is not multiple of 4K, then ASSERT.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartupRoutine Points to a start-up routine which is below 1M physical
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync address and 4K aligned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Programming Virtual Wire Mode.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function programs the local APIC for virtual wire mode following
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync the example described in chapter A.3 of the MP 1.4 spec.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync IOxAPIC is not involved in this type of virtual wire mode.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Disable LINT0 & LINT1 interrupts.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function sets the mask flag in the LVT LINT0 & LINT1 registers.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Read the initial count value from the init-count register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The initial count value read from the init-count register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Read the current count value from the current-count register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The current count value read from the current-count register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Initialize the local APIC timer.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync The local APIC timer is initialized and enabled.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If it is 0, then use the current divide value in the DCR.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param InitCount The initial count value.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Vector The timer interrupt vector number.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Get the state of the local APIC timer.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Vector Return the timer interrupt vector number.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Enable the local APIC timer interrupt.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Disable the local APIC timer interrupt.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Get the local APIC timer interrupt state.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval TRUE The local APIC timer interrupt is enabled.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval FALSE The local APIC timer interrupt is disabled.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Send EOI to the local APIC.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Get the 32-bit address that a device should use to send a Message Signaled
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Interrupt (MSI) to the Local APIC of the currently executing processor.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return 32-bit address used to send an MSI to the Local APIC.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Get the 64-bit data value that a device should use to send a Message Signaled
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Interrupt (MSI) to the Local APIC of the currently executing processor.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Vector is not in range 0x10..0xFE, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If DeliveryMode is not supported, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Vector The 8-bit interrupt vector associated with the MSI.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Must be in the range 0x10..0xFE
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync is handled. The only supported values are:
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 0: LOCAL_APIC_DELIVERY_MODE_FIXED
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 2: LOCAL_APIC_DELIVERY_MODE_SMI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 4: LOCAL_APIC_DELIVERY_MODE_NMI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 5: LOCAL_APIC_DELIVERY_MODE_INIT
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param LevelTriggered TRUE specifies a level triggered interrupt.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync FALSE specifies an edge triggered interrupt.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param AssertionLevel Ignored if LevelTriggered is FALSE.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync TRUE specifies a level triggered interrupt that active
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync when the interrupt line is asserted.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync FALSE specifies a level triggered interrupt that active
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync when the interrupt line is deasserted.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return 64-bit data value used to send an MSI to the Local APIC.