E100b.h revision 4fd606d1f5abe38e1f42c38de1d2e895166bd0f4
/** @file
Definitions for network adapter card.
Copyright (c) 2006 - 2007, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _E100B_H_
#define _E100B_H_
// pci config offsets:
#define RX_BUFFER_COUNT 32
#define TX_BUFFER_COUNT 32
#define PCI_VENDOR_ID_INTEL 0x8086
#define PCI_DEVICE_ID_INTEL_82557 0x1229
#define D100_VENDOR_ID 0x8086
#define D100_DEVICE_ID 0x1229
#define D102_DEVICE_ID 0x2449
#define ICH3_DEVICE_ID_1 0x1031
#define ICH3_DEVICE_ID_2 0x1032
#define ICH3_DEVICE_ID_3 0x1033
#define ICH3_DEVICE_ID_4 0x1034
#define ICH3_DEVICE_ID_5 0x1035
#define ICH3_DEVICE_ID_6 0x1036
#define ICH3_DEVICE_ID_7 0x1037
#define ICH3_DEVICE_ID_8 0x1038
#define SPEEDO_DEVICE_ID 0x1227
#define SPLASH1_DEVICE_ID 0x1226
// bit fields for the command
#define PCI_COMMAND 0x04
#define PCI_LATENCY_TIMER 0x0D
#define ETHER_MAC_ADDR_LEN 6
#ifdef AVL_XXX
#define ETHER_HEADER_LEN 14
// media interface type
// #define INTERFACE_TYPE "
// Hardware type values
#define HW_ETHER_TYPE 1
#define HW_EXPERIMENTAL_ETHER_TYPE 2
#define HW_IEEE_TYPE 6
#define HW_ARCNET_TYPE 7
#endif // AVL_XXX
#define TX_BUFFER_SIZE 64
#define SPEEDO3_TOTAL_SIZE 0x20
#pragma pack(1)
typedef struct eth {
} EtherHeader;
#pragma pack(1)
typedef struct CONFIG_HEADER {
#pragma pack()
//-------------------------------------------------------------------------
// Offsets to the various registers.
// All accesses need not be longword aligned.
//-------------------------------------------------------------------------
enum speedo_offsets {
// offsets for general control registers (GCRs)
};
//-------------------------------------------------------------------------
// Action commands - Commands that can be put in a command list entry.
//-------------------------------------------------------------------------
enum commands {
};
//-------------------------------------------------------------------------
// port commands
//-------------------------------------------------------------------------
#define PORT_RESET 0
#define PORT_SELF_TEST 1
#define POR_SELECTIVE_RESET 2
#define PORT_DUMP_POINTER 2
//-------------------------------------------------------------------------
// SCB Command Word bit definitions
//-------------------------------------------------------------------------
//- CUC fields
#define CU_START 0x0010
#define CU_RESUME 0x0020
#define CU_STATSADDR 0x0040
//- RUC fields
#define RX_START 0x0001
#define RX_RESUME 0x0002
#define RX_ABORT 0x0004
#define RX_RESUMENR 0x0007
// Interrupt fields (assuming byte addressing)
#define INT_MASK 0x0100
//- CB Status Word
#define CMD_STATUS_COMPLETE 0x8000
#define RX_STATUS_COMPLETE 0x8000
#define CMD_STATUS_MASK 0xF000
//-------------------------------------------------------------------------
//- SCB Status bits:
// Interrupts are ACKed by writing to the upper 6 interrupt bits
//-------------------------------------------------------------------------
// CU STATUS: bits 6 & 7
// RU STATUS: bits 2-5
#define SCB_RUS_IDLE 0x0000
//-------------------------------------------------------------------------
// Bit Mask definitions
//-------------------------------------------------------------------------
#define BIT_0 0x0001
#define BIT_1 0x0002
#define BIT_2 0x0004
#define BIT_3 0x0008
#define BIT_4 0x0010
#define BIT_5 0x0020
#define BIT_6 0x0040
#define BIT_7 0x0080
#define BIT_8 0x0100
#define BIT_9 0x0200
#define BIT_10 0x0400
#define BIT_11 0x0800
#define BIT_12 0x1000
#define BIT_13 0x2000
#define BIT_14 0x4000
#define BIT_15 0x8000
#define BIT_24 0x01000000
#define BIT_28 0x10000000
//-------------------------------------------------------------------------
// MDI Control register bit definitions
//-------------------------------------------------------------------------
#define BIT_0_2 0x0007
#define BIT_0_3 0x000F
#define BIT_0_4 0x001F
#define BIT_0_5 0x003F
#define BIT_0_6 0x007F
#define BIT_0_7 0x00FF
#define BIT_0_8 0x01FF
#define BIT_0_13 0x3FFF
#define BIT_0_15 0xFFFF
#define BIT_1_2 0x0006
#define BIT_1_3 0x000E
#define BIT_2_5 0x003C
#define BIT_3_4 0x0018
#define BIT_4_5 0x0030
#define BIT_4_6 0x0070
#define BIT_4_7 0x00F0
#define BIT_5_7 0x00E0
#define BIT_5_9 0x03E0
#define BIT_5_12 0x1FE0
#define BIT_5_15 0xFFE0
#define BIT_6_7 0x00c0
#define BIT_7_11 0x0F80
#define BIT_8_10 0x0700
#define BIT_9_13 0x3E00
#define BIT_12_15 0xF000
#define BIT_16_20 0x001F0000
#define BIT_21_25 0x03E00000
#define BIT_26_27 0x0C000000
//-------------------------------------------------------------------------
// MDI Control register opcode definitions
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// MDI register set
// MDI Control register bit definitions
// MDI Status register bit definitions
// Auto-Negotiation advertisement register bit definitions
// Auto-Negotiation link partner ability register bit definitions
// Auto-Negotiation expansion register bit definitions
// PHY 100 Extended Register 0 bit definitions
// PHY 100 Extended Register 1 bit definitions
// National Semiconductor TX phy congestion control register bit definitions
// National Semiconductor TX phy speed indication register bit definitions
//-------------------------------------------------------------------------
// Phy related constants
//-------------------------------------------------------------------------
#define PHY_503 0
#define PHY_100_A 0x000003E0
#define PHY_100_C 0x035002A8
#define PHY_TX_ID 0x015002A8
#define PHY_NSC_TX 0x5c002000
#define PHY_OTHER 0xFFFF
#define PHY_MODEL_REV_ID_MASK 0xFFF0FFFF
#define PARALLEL_DETECT 0
#define N_WAY 1
#define CONNECTOR_AUTO 0
#define CONNECTOR_TPE 1
#define CONNECTOR_MII 2
//-------------------------------------------------------------------------
#pragma pack(1)
struct CB_Header { /* A generic descriptor. */
};
/* transmit command block structure */
#pragma pack(1)
typedef struct s_TxCB {
physical TBD pointers */
/* following fields are not seen by the 82557 */
struct TBD {
struct s_TxCB *NextTCBVirtualLinkPtr;
struct s_TxCB *PrevTCBVirtualLinkPtr;
}TxCB;
/* The Speedo3 Rx and Tx buffer descriptors. */
#pragma pack(1)
typedef struct s_RxFD { /* Receive frame descriptor. */
}RxFD;
/* Elements of the RxFD.status word. */
#define RX_COMPLETE 0x8000
#define RX_FRAME_OK 0x2000
/* Elements of the dump_statistics block. This block must be lword aligned. */
#pragma pack(1)
struct speedo_stats {
};
#pragma pack()
struct Krn_Mem{
struct speedo_stats statistics;
};
#define MEMORY_NEEDED sizeof(struct Krn_Mem)
/* The parameters for a CmdConfigure operation.
There are so many options that it would be difficult to document each bit.
We mostly use the default or recommended settings.
*/
/*
*--------------------------------------------------------------------------
* Configuration CB Parameter Bit Definitions
*--------------------------------------------------------------------------
*/
// - Byte 0 (Default Value = 16h)
//- Byte 1 (Default Value = 88h)
#define CFIG_TXRX_FIFO_LIMIT 0x88
//- Byte 2 (Default Value = 0)
#define CFIG_ADAPTIVE_IFS 0
//- Byte 3 (Default Value = 0, ALWAYS. This byte is RESERVED)
#define CFIG_RESERVED 0
//- Byte 4 (Default Value = 0. Default implies that Rx DMA cannot be
//- preempted).
#define CFIG_RXDMA_BYTE_COUNT 0
//- Byte 5 (Default Value = 80h. Default implies that Tx DMA cannot be
//- preempted. However, setting these counters is enabled.)
#define CFIG_DMBC_ENABLE 0x80
//- Byte 6 (Default Value = 33h. Late SCB enabled, No TNO interrupts,
//- CNA interrupts and do not save bad frames.)
//- Byte 7 (Default Value = 7h. Discard short frames automatically and
//- attempt upto 3 retries on transmit.)
#define CFIG_DISCARD_SHORTRX 0x00001
//- Byte 8 (Default Value = 1. Enable MII mode.)
#define CFIG_503_MII BIT_0
//- Byte 9 (Default Value = 0, ALWAYS)
//- Byte 10 (Default Value = 2Eh)
#define CFIG_NO_LOOPBACK 0
#define CFIG_INTERNAL_LOOPBACK BIT_6
#define CFIG_EXT_LOOPBACK BIT_7
//- Byte 11 (Default Value = 0)
#define CFIG_LINEAR_PRIORITY 0
//- Byte 12 (Default Value = 60h)
#define CFIG_LPRIORITY_MODE 0
//- Byte 13 (Default Value = 0, ALWAYS)
//- Byte 14 (Default Value = 0F2h, ALWAYS)
//- Byte 15 (Default Value = E8h)
#define CFIG_PROMISCUOUS_MODE BIT_0
#define CFIG_BROADCAST_DISABLE BIT_1
#define CFIG_CRS_CDT BIT_7
//- Byte 16 (Default Value = 0, ALWAYS)
//- Byte 17 (Default Value = 40h, ALWAYS)
//- Byte 18 (Default Value = F2h)
#define CFIG_STRIPPING BIT_0
#define CFIG_PADDING BIT_1
#define CFIG_RX_CRC_TRANSFER BIT_2
//- Byte 19 (Default Value = 80h)
#define CFIG_FORCE_FDX BIT_6
#define CFIG_FDX_PIN_ENABLE BIT_7
//- Byte 20 (Default Value = 3Fh)
#define CFIG_MULTI_IA BIT_6
//- Byte 21 (Default Value = 05)
#define CFIG_MC_ALL BIT_3
/*-----------------------------------------------------------------------*/
#define D102_REVID 0x0b
#define HALF_DUPLEX 1
#define FULL_DUPLEX 2
typedef struct s_data_instance {
struct speedo_stats *statistics;
struct mc{
} mcast_list;
//
// Original PCI attributes
//
#pragma pack(1)
struct MC_CB_STRUCT{
};
#pragma pack()
#endif