4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PCI Segment Library implementation using PCI CFG2 PPI.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.<BR>
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This program and the accompanying materials are
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync licensed and made available under the terms and conditions of
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync the BSD License which accompanies this distribution. The full
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync text of the license may be found at
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Assert the validity of a PCI Segment address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param A The address to validate.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param M Additional bits to assert to be zero.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Translate PCI Lib address into format of PCI CFG2 PPI.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param A The address that encodes the PCI Bus, Device, Function and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ((((UINT32)(A) << 4) & 0xff000000) | (((UINT32)(A) >> 4) & 0x00000700) | (((UINT32)(A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Gets PCI CFG2 PPI.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This internal function retrieves PCI CFG2 PPI from PPI database.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Segment, Bus, Device,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Function and Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The pointer to PCI CFG2 PPI.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Loop through all instances of the PPI and match segment number
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Internal worker function to read a PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync It reads and returns the PCI configuration register specified by Address,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync the width of data is specified by Width.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Bus, Device, Function and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Width The width of data to read
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value read from the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Internal worker function to writes a PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync It writes the PCI configuration register specified by Address with the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync value specified by Data. The width of data is specifed by Width.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Data is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Bus, Device, Function and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Width The width of data to write
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Data The value to write.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Register a PCI device so PCI configuration registers may be accessed after
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync SetVirtualAddressMap().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Bus, Device, Function and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval RETURN_SUCCESS The PCI device was registered for runtime access.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval RETURN_UNSUPPORTED An attempt was made to call this function
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync after ExitBootServices().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval RETURN_UNSUPPORTED The resources required to access the PCI device
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync at runtime could not be mapped.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync complete the registration.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads an 8-bit PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads and returns the 8-bit PCI configuration register specified by Address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function must guarantee that all PCI read and write operations are serialized.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Segment, Bus, Device, Function,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync and Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The 8-bit PCI configuration register specified by Address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return (UINT8) PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint8);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes an 8-bit PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Value is returned. This function must guarantee that all PCI read and write operations are serialized.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Value The value to write.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return (UINT8) PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint8, Value);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the 8-bit PCI configuration register specified by Address,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync performs a bitwise OR between the read result and the value specified by OrData,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync and writes the result to the 8-bit PCI configuration register specified by Address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync The value written to the PCI configuration register is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function must guarantee that all PCI read and write operations are serialized.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param OrData The value to OR with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the 8-bit PCI configuration register specified by Address,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync performs a bitwise AND between the read result and the value specified by AndData,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync and writes the result to the 8-bit PCI configuration register specified by Address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync The value written to the PCI configuration register is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function must guarantee that all PCI read and write operations are serialized.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param AndData The value to AND with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync followed a bitwise OR with another 8-bit value.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the 8-bit PCI configuration register specified by Address,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync performs a bitwise AND between the read result and the value specified by AndData,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync performs a bitwise OR between the result of the AND operation and the value specified by OrData,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync and writes the result to the 8-bit PCI configuration register specified by Address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync The value written to the PCI configuration register is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function must guarantee that all PCI read and write operations are serialized.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param AndData The value to AND with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param OrData The value to OR with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads a bit field of a PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the bit field in an 8-bit PCI configuration register. The bit field is
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync specified by the StartBit and the EndBit. The value of the bit field is
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If StartBit is greater than 7, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is greater than 7, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is less than StartBit, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The PCI configuration register to read.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartBit The ordinal of the least significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..7.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param EndBit The ordinal of the most significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..7.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value of the bit field read from the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes a bit field to a PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes Value to the bit field of the PCI configuration register. The bit
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync field is specified by the StartBit and the EndBit. All other bits in the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync destination PCI configuration register are preserved. The new value of the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 8-bit register is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If StartBit is greater than 7, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is greater than 7, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is less than StartBit, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The PCI configuration register to write.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartBit The ordinal of the least significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..7.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param EndBit The ordinal of the most significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..7.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Value The new value of the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written back to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync writes the result back to the bit field in the 8-bit port.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the 8-bit PCI configuration register specified by Address, performs a
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync bitwise OR between the read result and the value specified by
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync OrData, and writes the result to the 8-bit PCI configuration register
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync specified by Address. The value written to the PCI configuration register is
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync returned. This function must guarantee that all PCI read and write operations
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync are serialized. Extra left bits in OrData are stripped.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If StartBit is greater than 7, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is greater than 7, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is less than StartBit, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The PCI configuration register to write.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartBit The ordinal of the least significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..7.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param EndBit The ordinal of the most significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..7.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param OrData The value to OR with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written back to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync AND, and writes the result back to the bit field in the 8-bit register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the 8-bit PCI configuration register specified by Address, performs a
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync bitwise AND between the read result and the value specified by AndData, and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync writes the result to the 8-bit PCI configuration register specified by
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Address. The value written to the PCI configuration register is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function must guarantee that all PCI read and write operations are
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync serialized. Extra left bits in AndData are stripped.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If StartBit is greater than 7, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is greater than 7, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is less than StartBit, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The PCI configuration register to write.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartBit The ordinal of the least significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..7.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param EndBit The ordinal of the most significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..7.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param AndData The value to AND with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written back to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync bitwise OR, and writes the result back to the bit field in the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 8-bit port.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the 8-bit PCI configuration register specified by Address, performs a
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync bitwise AND followed by a bitwise OR between the read result and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync the value specified by AndData, and writes the result to the 8-bit PCI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync configuration register specified by Address. The value written to the PCI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync configuration register is returned. This function must guarantee that all PCI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync read and write operations are serialized. Extra left bits in both AndData and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync OrData are stripped.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If StartBit is greater than 7, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is greater than 7, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is less than StartBit, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The PCI configuration register to write.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartBit The ordinal of the least significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..7.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param EndBit The ordinal of the most significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..7.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param AndData The value to AND with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param OrData The value to OR with the result of the AND operation.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written back to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads a 16-bit PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads and returns the 16-bit PCI configuration register specified by Address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function must guarantee that all PCI read and write operations are serialized.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Address is not aligned on a 16-bit boundary, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The 16-bit PCI configuration register specified by Address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return (UINT16) PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint16);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes a 16-bit PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Value is returned. This function must guarantee that all PCI read and write operations are serialized.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Address is not aligned on a 16-bit boundary, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Value The value to write.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The parameter of Value.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return (UINT16) PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint16, Value);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Performs a bitwise OR of a 16-bit PCI configuration register with
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync a 16-bit value.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the 16-bit PCI configuration register specified by Address, performs a
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync bitwise OR between the read result and the value specified by
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync OrData, and writes the result to the 16-bit PCI configuration register
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync specified by Address. The value written to the PCI configuration register is
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync returned. This function must guarantee that all PCI read and write operations
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync are serialized.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Address is not aligned on a 16-bit boundary, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Segment, Bus, Device, Function and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param OrData The value to OR with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written back to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the 16-bit PCI configuration register specified by Address,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync performs a bitwise AND between the read result and the value specified by AndData,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync and writes the result to the 16-bit PCI configuration register specified by Address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync The value written to the PCI configuration register is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function must guarantee that all PCI read and write operations are serialized.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Address is not aligned on a 16-bit boundary, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param AndData The value to AND with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync followed a bitwise OR with another 16-bit value.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the 16-bit PCI configuration register specified by Address,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync performs a bitwise AND between the read result and the value specified by AndData,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync performs a bitwise OR between the result of the AND operation and the value specified by OrData,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync and writes the result to the 16-bit PCI configuration register specified by Address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync The value written to the PCI configuration register is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function must guarantee that all PCI read and write operations are serialized.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Address is not aligned on a 16-bit boundary, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param AndData The value to AND with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param OrData The value to OR with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads a bit field of a PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the bit field in a 16-bit PCI configuration register. The bit field is
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync specified by the StartBit and the EndBit. The value of the bit field is
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Address is not aligned on a 16-bit boundary, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If StartBit is greater than 15, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is greater than 15, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is less than StartBit, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The PCI configuration register to read.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartBit The ordinal of the least significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..15.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param EndBit The ordinal of the most significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..15.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value of the bit field read from the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes a bit field to a PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes Value to the bit field of the PCI configuration register. The bit
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync field is specified by the StartBit and the EndBit. All other bits in the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync destination PCI configuration register are preserved. The new value of the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 16-bit register is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Address is not aligned on a 16-bit boundary, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If StartBit is greater than 15, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is greater than 15, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is less than StartBit, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The PCI configuration register to write.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartBit The ordinal of the least significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..15.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param EndBit The ordinal of the most significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..15.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Value The new value of the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written back to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the 16-bit PCI configuration register specified by Address,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync performs a bitwise OR between the read result and the value specified by OrData,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync and writes the result to the 16-bit PCI configuration register specified by Address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Address is not aligned on a 16-bit boundary, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If StartBit is greater than 15, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is greater than 15, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is less than StartBit, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The PCI configuration register to write.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartBit The ordinal of the least significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..15.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param EndBit The ordinal of the most significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..15.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param OrData The value to OR with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written back to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync and writes the result back to the bit field in the 16-bit port.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the 16-bit PCI configuration register specified by Address,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync performs a bitwise OR between the read result and the value specified by OrData,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync and writes the result to the 16-bit PCI configuration register specified by Address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync The value written to the PCI configuration register is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function must guarantee that all PCI read and write operations are serialized.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Extra left bits in OrData are stripped.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Address is not aligned on a 16-bit boundary, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If StartBit is greater than 7, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is greater than 7, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is less than StartBit, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartBit The ordinal of the least significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync The ordinal of the least significant bit in a byte is bit 0.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param EndBit The ordinal of the most significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync The ordinal of the most significant bit in a byte is bit 7.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param AndData The value to AND with the read value from the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync bitwise OR, and writes the result back to the bit field in the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 16-bit port.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the 16-bit PCI configuration register specified by Address, performs a
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync bitwise AND followed by a bitwise OR between the read result and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync the value specified by AndData, and writes the result to the 16-bit PCI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync configuration register specified by Address. The value written to the PCI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync configuration register is returned. This function must guarantee that all PCI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync read and write operations are serialized. Extra left bits in both AndData and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync OrData are stripped.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If StartBit is greater than 15, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is greater than 15, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is less than StartBit, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The PCI configuration register to write.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartBit The ordinal of the least significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..15.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param EndBit The ordinal of the most significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..15.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param AndData The value to AND with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param OrData The value to OR with the result of the AND operation.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written back to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads a 32-bit PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads and returns the 32-bit PCI configuration register specified by Address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function must guarantee that all PCI read and write operations are serialized.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Address is not aligned on a 32-bit boundary, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Segment, Bus, Device, Function,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync and Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The 32-bit PCI configuration register specified by Address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint32);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes a 32-bit PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Value is returned. This function must guarantee that all PCI read and write operations are serialized.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Address is not aligned on a 32-bit boundary, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Segment, Bus, Device,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Function, and Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Value The value to write.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The parameter of Value.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint32, Value);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the 32-bit PCI configuration register specified by Address,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync performs a bitwise OR between the read result and the value specified by OrData,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync and writes the result to the 32-bit PCI configuration register specified by Address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync The value written to the PCI configuration register is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function must guarantee that all PCI read and write operations are serialized.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Address is not aligned on a 32-bit boundary, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param OrData The value to OR with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the 32-bit PCI configuration register specified by Address,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync performs a bitwise AND between the read result and the value specified by AndData,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync and writes the result to the 32-bit PCI configuration register specified by Address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync The value written to the PCI configuration register is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function must guarantee that all PCI read and write operations are serialized.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Address is not aligned on a 32-bit boundary, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Segment, Bus, Device, Function,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync and Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param AndData The value to AND with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync followed a bitwise OR with another 32-bit value.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the 32-bit PCI configuration register specified by Address,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync performs a bitwise AND between the read result and the value specified by AndData,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync performs a bitwise OR between the result of the AND operation and the value specified by OrData,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync and writes the result to the 32-bit PCI configuration register specified by Address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync The value written to the PCI configuration register is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function must guarantee that all PCI read and write operations are serialized.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Address is not aligned on a 32-bit boundary, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The address that encodes the PCI Segment, Bus, Device, Function,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync and Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param AndData The value to AND with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param OrData The value to OR with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads a bit field of a PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the bit field in a 32-bit PCI configuration register. The bit field is
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync specified by the StartBit and the EndBit. The value of the bit field is
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Address is not aligned on a 32-bit boundary, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If StartBit is greater than 31, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is greater than 31, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is less than StartBit, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The PCI configuration register to read.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartBit The ordinal of the least significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..31.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param EndBit The ordinal of the most significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..31.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value of the bit field read from the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes a bit field to a PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes Value to the bit field of the PCI configuration register. The bit
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync field is specified by the StartBit and the EndBit. All other bits in the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync destination PCI configuration register are preserved. The new value of the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 32-bit register is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Address is not aligned on a 32-bit boundary, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If StartBit is greater than 31, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is greater than 31, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is less than StartBit, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The PCI configuration register to write.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartBit The ordinal of the least significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..31.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param EndBit The ordinal of the most significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..31.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Value The new value of the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written back to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync writes the result back to the bit field in the 32-bit port.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the 32-bit PCI configuration register specified by Address, performs a
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync bitwise OR between the read result and the value specified by
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync OrData, and writes the result to the 32-bit PCI configuration register
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync specified by Address. The value written to the PCI configuration register is
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync returned. This function must guarantee that all PCI read and write operations
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync are serialized. Extra left bits in OrData are stripped.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If StartBit is greater than 31, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is greater than 31, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is less than StartBit, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The PCI configuration register to write.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartBit The ordinal of the least significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..31.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param EndBit The ordinal of the most significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..31.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param OrData The value to OR with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written back to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync AND, and writes the result back to the bit field in the 32-bit register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync AND between the read result and the value specified by AndData, and writes the result
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync to the 32-bit PCI configuration register specified by Address. The value written to
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync the PCI configuration register is returned. This function must guarantee that all PCI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync read and write operations are serialized. Extra left bits in AndData are stripped.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Address is not aligned on a 32-bit boundary, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If StartBit is greater than 31, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is greater than 31, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is less than StartBit, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The PCI configuration register to write.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartBit The ordinal of the least significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..31.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param EndBit The ordinal of the most significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..31.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param AndData The value to AND with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written back to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync bitwise OR, and writes the result back to the bit field in the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 32-bit port.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the 32-bit PCI configuration register specified by Address, performs a
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync bitwise AND followed by a bitwise OR between the read result and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync the value specified by AndData, and writes the result to the 32-bit PCI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync configuration register specified by Address. The value written to the PCI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync configuration register is returned. This function must guarantee that all PCI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync read and write operations are serialized. Extra left bits in both AndData and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync OrData are stripped.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in Address are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If StartBit is greater than 31, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is greater than 31, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If EndBit is less than StartBit, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The PCI configuration register to write.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartBit The ordinal of the least significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..31.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param EndBit The ordinal of the most significant bit in the bit field.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Range 0..31.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param AndData The value to AND with the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param OrData The value to OR with the result of the AND operation.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The value written back to the PCI configuration register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads a range of PCI configuration registers into a caller supplied buffer.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reads the range of PCI configuration registers specified by StartAddress and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Size into the buffer specified by Buffer. This function only allows the PCI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync configuration registers from a single PCI function to be read. Size is
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync returned. When possible 32-bit PCI configuration read cycles are used to read
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync and 16-bit PCI configuration read cycles may be used at the beginning and the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync end of the range.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in StartAddress are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Size > 0 and Buffer is NULL, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartAddress The starting address that encodes the PCI Segment, Bus,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Device, Function and Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Size The size in bytes of the transfer.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Buffer The pointer to a buffer receiving the data read.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return Size
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if (Size == 0) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Save Size for return
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Read a byte if StartAddress is byte aligned
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Read a word if StartAddress is word aligned
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Read as many double words as possible
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Read the last remaining word if exist
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Read the last remaining byte if exist
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Copies the data in a caller supplied buffer to a specified range of PCI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync configuration space.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes the range of PCI configuration registers specified by StartAddress and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Size from the buffer specified by Buffer. This function only allows the PCI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync configuration registers from a single PCI function to be written. Size is
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync returned. When possible 32-bit PCI configuration write cycles are used to
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync write from StartAdress to StartAddress + Size. Due to alignment restrictions,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync and the end of the range.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If any reserved bits in StartAddress are set, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Size > 0 and Buffer is NULL, then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param StartAddress The starting address that encodes the PCI Segment, Bus,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Device, Function and Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Size The size in bytes of the transfer.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Buffer The pointer to a buffer containing the data to write.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The parameter of Size.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if (Size == 0) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Save Size for return
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Write a byte if StartAddress is byte aligned
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Write a word if StartAddress is word aligned
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Write as many double words as possible
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Write the last remaining word if exist
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Write the last remaining byte if exist