PciLib.c revision 4fd606d1f5abe38e1f42c38de1d2e895166bd0f4
1N/A PCI Library functions that use I/O ports 0xCF8 and 0xCFC to perform 1N/A PCI Configuration cycles. Layers on top of one PCI CF8 Library instance. 1N/A Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR> 1N/A This program and the accompanying materials 1N/A are licensed and made available under the terms and conditions of the BSD License 1N/A which accompanies this distribution. The full text of the license may be found at 1N/A THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 1N/A WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 1N/A Registers a PCI device so PCI configuration registers may be accessed after 1N/A SetVirtualAddressMap(). 1N/A Registers the PCI device specified by Address so all the PCI configuration registers 1N/A associated with that PCI device may be accessed after SetVirtualAddressMap() is called. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A @param Address The address that encodes the PCI Bus, Device, Function and 1N/A @retval RETURN_SUCCESS The PCI device was registered for runtime access. 1N/A @retval RETURN_UNSUPPORTED An attempt was made to call this function 1N/A after ExitBootServices(). 1N/A @retval RETURN_UNSUPPORTED The resources required to access the PCI device 1N/A at runtime could not be mapped. 1N/A @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to 1N/A complete the registration. 1N/A Reads an 8-bit PCI configuration register. 1N/A Reads and returns the 8-bit PCI configuration register specified by Address. 1N/A This function must guarantee that all PCI read and write operations are 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A @param Address The address that encodes the PCI Bus, Device, Function and 1N/A @return The read value from the PCI configuration register. 1N/A Writes an 8-bit PCI configuration register. 1N/A Writes the 8-bit PCI configuration register specified by Address with the 1N/A value specified by Value. Value is returned. This function must guarantee 1N/A that all PCI read and write operations are serialized. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A @param Address The address that encodes the PCI Bus, Device, Function and 1N/A @param Value The value to write. 1N/A @return The value written to the PCI configuration register. 1N/A Performs a bitwise OR of an 8-bit PCI configuration register with 1N/A Reads the 8-bit PCI configuration register specified by Address, performs a 1N/A bitwise OR between the read result and the value specified by 1N/A OrData, and writes the result to the 8-bit PCI configuration register 1N/A specified by Address. The value written to the PCI configuration register is 1N/A returned. This function must guarantee that all PCI read and write operations 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A @param Address The address that encodes the PCI Bus, Device, Function and 1N/A @param OrData The value to OR with the PCI configuration register. 1N/A @return The value written back to the PCI configuration register. 1N/A Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit 1N/A Reads the 8-bit PCI configuration register specified by Address, performs a 1N/A bitwise AND between the read result and the value specified by AndData, and 1N/A writes the result to the 8-bit PCI configuration register specified by 1N/A Address. The value written to the PCI configuration register is returned. 1N/A This function must guarantee that all PCI read and write operations are 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A @param Address The address that encodes the PCI Bus, Device, Function and 1N/A @param AndData The value to AND with the PCI configuration register. 1N/A @return The value written back to the PCI configuration register. 1N/A Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit 1N/A value, followed a bitwise OR with another 8-bit value. 1N/A Reads the 8-bit PCI configuration register specified by Address, performs a 1N/A bitwise AND between the read result and the value specified by AndData, 1N/A performs a bitwise OR between the result of the AND operation and 1N/A the value specified by OrData, and writes the result to the 8-bit PCI 1N/A configuration register specified by Address. The value written to the PCI 1N/A configuration register is returned. This function must guarantee that all PCI 1N/A read and write operations are serialized. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A @param Address The address that encodes the PCI Bus, Device, Function and 1N/A @param AndData The value to AND with the PCI configuration register. 1N/A @param OrData The value to OR with the result of the AND operation. 1N/A @return The value written back to the PCI configuration register. 1N/A Reads a bit field of a PCI configuration register. 1N/A Reads the bit field in an 8-bit PCI configuration register. The bit field is 1N/A specified by the StartBit and the EndBit. The value of the bit field is 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If StartBit is greater than 7, then ASSERT(). 1N/A If EndBit is greater than 7, then ASSERT(). 1N/A If EndBit is less than StartBit, then ASSERT(). 1N/A @param Address The PCI configuration register to read. 1N/A @param StartBit The ordinal of the least significant bit in the bit field. 1N/A @param EndBit The ordinal of the most significant bit in the bit field. 1N/A @return The value of the bit field read from the PCI configuration register. 1N/A Writes a bit field to a PCI configuration register. 1N/A Writes Value to the bit field of the PCI configuration register. The bit 1N/A field is specified by the StartBit and the EndBit. All other bits in the 1N/A destination PCI configuration register are preserved. The new value of the 1N/A 8-bit register is returned. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If StartBit is greater than 7, then ASSERT(). 1N/A If EndBit is greater than 7, then ASSERT(). 1N/A If EndBit is less than StartBit, then ASSERT(). 1N/A @param Address The PCI configuration register to write. 1N/A @param StartBit The ordinal of the least significant bit in the bit field. 1N/A @param EndBit The ordinal of the most significant bit in the bit field. 1N/A @param Value The new value of the bit field. 1N/A @return The value written back to the PCI configuration register. 1N/A Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and 1N/A writes the result back to the bit field in the 8-bit port. 1N/A Reads the 8-bit PCI configuration register specified by Address, performs a 1N/A bitwise OR between the read result and the value specified by 1N/A OrData, and writes the result to the 8-bit PCI configuration register 1N/A specified by Address. The value written to the PCI configuration register is 1N/A returned. This function must guarantee that all PCI read and write operations 1N/A are serialized. Extra left bits in OrData are stripped. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If StartBit is greater than 7, then ASSERT(). 1N/A If EndBit is greater than 7, then ASSERT(). 1N/A If EndBit is less than StartBit, then ASSERT(). 1N/A @param Address The PCI configuration register to write. 1N/A @param StartBit The ordinal of the least significant bit in the bit field. 1N/A @param EndBit The ordinal of the most significant bit in the bit field. 1N/A @param OrData The value to OR with the PCI configuration register. 1N/A @return The value written back to the PCI configuration register. 1N/A Reads a bit field in an 8-bit PCI configuration register, performs a bitwise 1N/A AND, and writes the result back to the bit field in the 8-bit register. 1N/A Reads the 8-bit PCI configuration register specified by Address, performs a 1N/A bitwise AND between the read result and the value specified by AndData, and 1N/A writes the result to the 8-bit PCI configuration register specified by 1N/A Address. The value written to the PCI configuration register is returned. 1N/A This function must guarantee that all PCI read and write operations are 1N/A serialized. Extra left bits in AndData are stripped. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If StartBit is greater than 7, then ASSERT(). 1N/A If EndBit is greater than 7, then ASSERT(). 1N/A If EndBit is less than StartBit, then ASSERT(). 1N/A @param Address The PCI configuration register to write. 1N/A @param StartBit The ordinal of the least significant bit in the bit field. 1N/A @param EndBit The ordinal of the most significant bit in the bit field. 1N/A @param AndData The value to AND with the PCI configuration register. 1N/A @return The value written back to the PCI configuration register. 1N/A Reads a bit field in an 8-bit port, performs a bitwise AND followed by a 1N/A bitwise OR, and writes the result back to the bit field in the 1N/A Reads the 8-bit PCI configuration register specified by Address, performs a 1N/A bitwise AND followed by a bitwise OR between the read result and 1N/A the value specified by AndData, and writes the result to the 8-bit PCI 1N/A configuration register specified by Address. The value written to the PCI 1N/A configuration register is returned. This function must guarantee that all PCI 1N/A read and write operations are serialized. Extra left bits in both AndData and 1N/A OrData are stripped. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If StartBit is greater than 7, then ASSERT(). 1N/A If EndBit is greater than 7, then ASSERT(). 1N/A If EndBit is less than StartBit, then ASSERT(). 1N/A @param Address The PCI configuration register to write. 1N/A @param StartBit The ordinal of the least significant bit in the bit field. 1N/A @param EndBit The ordinal of the most significant bit in the bit field. 1N/A @param AndData The value to AND with the PCI configuration register. 1N/A @param OrData The value to OR with the result of the AND operation. 1N/A @return The value written back to the PCI configuration register. 1N/A Reads a 16-bit PCI configuration register. 1N/A Reads and returns the 16-bit PCI configuration register specified by Address. 1N/A This function must guarantee that all PCI read and write operations are 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 16-bit boundary, then ASSERT(). 1N/A @param Address The address that encodes the PCI Bus, Device, Function and 1N/A @return The read value from the PCI configuration register. 1N/A Writes a 16-bit PCI configuration register. 1N/A Writes the 16-bit PCI configuration register specified by Address with the 1N/A value specified by Value. Value is returned. This function must guarantee 1N/A that all PCI read and write operations are serialized. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 16-bit boundary, then ASSERT(). 1N/A @param Address The address that encodes the PCI Bus, Device, Function and 1N/A @param Value The value to write. 1N/A @return The value written to the PCI configuration register. 1N/A Performs a bitwise OR of a 16-bit PCI configuration register with 1N/A Reads the 16-bit PCI configuration register specified by Address, performs a 1N/A bitwise OR between the read result and the value specified by 1N/A OrData, and writes the result to the 16-bit PCI configuration register 1N/A specified by Address. The value written to the PCI configuration register is 1N/A returned. This function must guarantee that all PCI read and write operations 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 16-bit boundary, then ASSERT(). 1N/A @param Address The address that encodes the PCI Bus, Device, Function and 1N/A @param OrData The value to OR with the PCI configuration register. 1N/A @return The value written back to the PCI configuration register. 1N/A Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit 1N/A Reads the 16-bit PCI configuration register specified by Address, performs a 1N/A bitwise AND between the read result and the value specified by AndData, and 1N/A writes the result to the 16-bit PCI configuration register specified by 1N/A Address. The value written to the PCI configuration register is returned. 1N/A This function must guarantee that all PCI read and write operations are 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 16-bit boundary, then ASSERT(). 1N/A @param Address The address that encodes the PCI Bus, Device, Function and 1N/A @param AndData The value to AND with the PCI configuration register. 1N/A @return The value written back to the PCI configuration register. 1N/A Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit 1N/A value, followed a bitwise OR with another 16-bit value. 1N/A Reads the 16-bit PCI configuration register specified by Address, performs a 1N/A bitwise AND between the read result and the value specified by AndData, 1N/A performs a bitwise OR between the result of the AND operation and 1N/A the value specified by OrData, and writes the result to the 16-bit PCI 1N/A configuration register specified by Address. The value written to the PCI 1N/A configuration register is returned. This function must guarantee that all PCI 1N/A read and write operations are serialized. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 16-bit boundary, then ASSERT(). 1N/A @param Address The address that encodes the PCI Bus, Device, Function and 1N/A @param AndData The value to AND with the PCI configuration register. 1N/A @param OrData The value to OR with the result of the AND operation. 1N/A @return The value written back to the PCI configuration register. 1N/A Reads a bit field of a PCI configuration register. 1N/A Reads the bit field in a 16-bit PCI configuration register. The bit field is 1N/A specified by the StartBit and the EndBit. The value of the bit field is 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 16-bit boundary, then ASSERT(). 1N/A If StartBit is greater than 15, then ASSERT(). 1N/A If EndBit is greater than 15, then ASSERT(). 1N/A If EndBit is less than StartBit, then ASSERT(). 1N/A @param Address The PCI configuration register to read. 1N/A @param StartBit The ordinal of the least significant bit in the bit field. 1N/A @param EndBit The ordinal of the most significant bit in the bit field. 1N/A @return The value of the bit field read from the PCI configuration register. 1N/A Writes a bit field to a PCI configuration register. 1N/A Writes Value to the bit field of the PCI configuration register. The bit 1N/A field is specified by the StartBit and the EndBit. All other bits in the 1N/A destination PCI configuration register are preserved. The new value of the 1N/A 16-bit register is returned. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 16-bit boundary, then ASSERT(). 1N/A If StartBit is greater than 15, then ASSERT(). 1N/A If EndBit is greater than 15, then ASSERT(). 1N/A If EndBit is less than StartBit, then ASSERT(). 1N/A @param Address The PCI configuration register to write. 1N/A @param StartBit The ordinal of the least significant bit in the bit field. 1N/A @param EndBit The ordinal of the most significant bit in the bit field. 1N/A @param Value The new value of the bit field. 1N/A @return The value written back to the PCI configuration register. 1N/A Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and 1N/A writes the result back to the bit field in the 16-bit port. 1N/A Reads the 16-bit PCI configuration register specified by Address, performs a 1N/A bitwise OR between the read result and the value specified by 1N/A OrData, and writes the result to the 16-bit PCI configuration register 1N/A specified by Address. The value written to the PCI configuration register is 1N/A returned. This function must guarantee that all PCI read and write operations 1N/A are serialized. Extra left bits in OrData are stripped. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 16-bit boundary, then ASSERT(). 1N/A If StartBit is greater than 15, then ASSERT(). 1N/A If EndBit is greater than 15, then ASSERT(). 1N/A If EndBit is less than StartBit, then ASSERT(). 1N/A @param Address The PCI configuration register to write. 1N/A @param StartBit The ordinal of the least significant bit in the bit field. 1N/A @param EndBit The ordinal of the most significant bit in the bit field. 1N/A @param OrData The value to OR with the PCI configuration register. 1N/A @return The value written back to the PCI configuration register. 1N/A Reads a bit field in a 16-bit PCI configuration register, performs a bitwise 1N/A AND, and writes the result back to the bit field in the 16-bit register. 1N/A Reads the 16-bit PCI configuration register specified by Address, performs a 1N/A bitwise AND between the read result and the value specified by AndData, and 1N/A writes the result to the 16-bit PCI configuration register specified by 1N/A Address. The value written to the PCI configuration register is returned. 1N/A This function must guarantee that all PCI read and write operations are 1N/A serialized. Extra left bits in AndData are stripped. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 16-bit boundary, then ASSERT(). 1N/A If StartBit is greater than 15, then ASSERT(). 1N/A If EndBit is greater than 15, then ASSERT(). 1N/A If EndBit is less than StartBit, then ASSERT(). 1N/A @param Address The PCI configuration register to write. 1N/A @param StartBit The ordinal of the least significant bit in the bit field. 1N/A @param EndBit The ordinal of the most significant bit in the bit field. 1N/A @param AndData The value to AND with the PCI configuration register. 1N/A @return The value written back to the PCI configuration register. 1N/A Reads a bit field in a 16-bit port, performs a bitwise AND followed by a 1N/A bitwise OR, and writes the result back to the bit field in the 1N/A Reads the 16-bit PCI configuration register specified by Address, performs a 1N/A bitwise AND followed by a bitwise OR between the read result and 1N/A the value specified by AndData, and writes the result to the 16-bit PCI 1N/A configuration register specified by Address. The value written to the PCI 1N/A configuration register is returned. This function must guarantee that all PCI 1N/A read and write operations are serialized. Extra left bits in both AndData and 1N/A OrData are stripped. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 16-bit boundary, then ASSERT(). 1N/A If StartBit is greater than 15, then ASSERT(). 1N/A If EndBit is greater than 15, then ASSERT(). 1N/A If EndBit is less than StartBit, then ASSERT(). 1N/A @param Address The PCI configuration register to write. 1N/A @param StartBit The ordinal of the least significant bit in the bit field. 1N/A @param EndBit The ordinal of the most significant bit in the bit field. 1N/A @param AndData The value to AND with the PCI configuration register. 1N/A @param OrData The value to OR with the result of the AND operation. 1N/A @return The value written back to the PCI configuration register. 1N/A Reads a 32-bit PCI configuration register. 1N/A Reads and returns the 32-bit PCI configuration register specified by Address. 1N/A This function must guarantee that all PCI read and write operations are 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 32-bit boundary, then ASSERT(). 1N/A @param Address The address that encodes the PCI Bus, Device, Function and 1N/A @return The read value from the PCI configuration register. 1N/A Writes a 32-bit PCI configuration register. 1N/A Writes the 32-bit PCI configuration register specified by Address with the 1N/A value specified by Value. Value is returned. This function must guarantee 1N/A that all PCI read and write operations are serialized. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 32-bit boundary, then ASSERT(). 1N/A @param Address The address that encodes the PCI Bus, Device, Function and 1N/A @param Value The value to write. 1N/A @return The value written to the PCI configuration register. 1N/A Performs a bitwise OR of a 32-bit PCI configuration register with 1N/A Reads the 32-bit PCI configuration register specified by Address, performs a 1N/A bitwise OR between the read result and the value specified by 1N/A OrData, and writes the result to the 32-bit PCI configuration register 1N/A specified by Address. The value written to the PCI configuration register is 1N/A returned. This function must guarantee that all PCI read and write operations 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 32-bit boundary, then ASSERT(). 1N/A @param Address The address that encodes the PCI Bus, Device, Function and 1N/A @param OrData The value to OR with the PCI configuration register. 1N/A @return The value written back to the PCI configuration register. 1N/A Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit 1N/A Reads the 32-bit PCI configuration register specified by Address, performs a 1N/A bitwise AND between the read result and the value specified by AndData, and 1N/A writes the result to the 32-bit PCI configuration register specified by 1N/A Address. The value written to the PCI configuration register is returned. 1N/A This function must guarantee that all PCI read and write operations are 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 32-bit boundary, then ASSERT(). 1N/A @param Address The address that encodes the PCI Bus, Device, Function and 1N/A @param AndData The value to AND with the PCI configuration register. 1N/A @return The value written back to the PCI configuration register. 1N/A Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit 1N/A value, followed a bitwise OR with another 32-bit value. 1N/A Reads the 32-bit PCI configuration register specified by Address, performs a 1N/A bitwise AND between the read result and the value specified by AndData, 1N/A performs a bitwise OR between the result of the AND operation and 1N/A the value specified by OrData, and writes the result to the 32-bit PCI 1N/A configuration register specified by Address. The value written to the PCI 1N/A configuration register is returned. This function must guarantee that all PCI 1N/A read and write operations are serialized. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 32-bit boundary, then ASSERT(). 1N/A @param Address The address that encodes the PCI Bus, Device, Function and 1N/A @param AndData The value to AND with the PCI configuration register. 1N/A @param OrData The value to OR with the result of the AND operation. 1N/A @return The value written back to the PCI configuration register. 1N/A Reads a bit field of a PCI configuration register. 1N/A Reads the bit field in a 32-bit PCI configuration register. The bit field is 1N/A specified by the StartBit and the EndBit. The value of the bit field is 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 32-bit boundary, then ASSERT(). 1N/A If StartBit is greater than 31, then ASSERT(). 1N/A If EndBit is greater than 31, then ASSERT(). 1N/A If EndBit is less than StartBit, then ASSERT(). 1N/A @param Address The PCI configuration register to read. 1N/A @param StartBit The ordinal of the least significant bit in the bit field. 1N/A @param EndBit The ordinal of the most significant bit in the bit field. 1N/A @return The value of the bit field read from the PCI configuration register. 1N/A Writes a bit field to a PCI configuration register. 1N/A Writes Value to the bit field of the PCI configuration register. The bit 1N/A field is specified by the StartBit and the EndBit. All other bits in the 1N/A destination PCI configuration register are preserved. The new value of the 1N/A 32-bit register is returned. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 32-bit boundary, then ASSERT(). 1N/A If StartBit is greater than 31, then ASSERT(). 1N/A If EndBit is greater than 31, then ASSERT(). 1N/A If EndBit is less than StartBit, then ASSERT(). 1N/A @param Address The PCI configuration register to write. 1N/A @param StartBit The ordinal of the least significant bit in the bit field. 1N/A @param EndBit The ordinal of the most significant bit in the bit field. 1N/A @param Value The new value of the bit field. 1N/A @return The value written back to the PCI configuration register. 1N/A Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and 1N/A writes the result back to the bit field in the 32-bit port. 1N/A Reads the 32-bit PCI configuration register specified by Address, performs a 1N/A bitwise OR between the read result and the value specified by 1N/A OrData, and writes the result to the 32-bit PCI configuration register 1N/A specified by Address. The value written to the PCI configuration register is 1N/A returned. This function must guarantee that all PCI read and write operations 1N/A are serialized. Extra left bits in OrData are stripped. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 32-bit boundary, then ASSERT(). 1N/A If StartBit is greater than 31, then ASSERT(). 1N/A If EndBit is greater than 31, then ASSERT(). 1N/A If EndBit is less than StartBit, then ASSERT(). 1N/A @param Address The PCI configuration register to write. 1N/A @param StartBit The ordinal of the least significant bit in the bit field. 1N/A @param EndBit The ordinal of the most significant bit in the bit field. 1N/A @param OrData The value to OR with the PCI configuration register. 1N/A @return The value written back to the PCI configuration register. 1N/A Reads a bit field in a 32-bit PCI configuration register, performs a bitwise 1N/A AND, and writes the result back to the bit field in the 32-bit register. 1N/A Reads the 32-bit PCI configuration register specified by Address, performs a 1N/A bitwise AND between the read result and the value specified by AndData, and 1N/A writes the result to the 32-bit PCI configuration register specified by 1N/A Address. The value written to the PCI configuration register is returned. 1N/A This function must guarantee that all PCI read and write operations are 1N/A serialized. Extra left bits in AndData are stripped. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 32-bit boundary, then ASSERT(). 1N/A If StartBit is greater than 31, then ASSERT(). 1N/A If EndBit is greater than 31, then ASSERT(). 1N/A If EndBit is less than StartBit, then ASSERT(). 1N/A @param Address The PCI configuration register to write. 1N/A @param StartBit The ordinal of the least significant bit in the bit field. 1N/A @param EndBit The ordinal of the most significant bit in the bit field. 1N/A @param AndData The value to AND with the PCI configuration register. 1N/A @return The value written back to the PCI configuration register. 1N/A Reads a bit field in a 32-bit port, performs a bitwise AND followed by a 1N/A bitwise OR, and writes the result back to the bit field in the 1N/A Reads the 32-bit PCI configuration register specified by Address, performs a 1N/A bitwise AND followed by a bitwise OR between the read result and 1N/A the value specified by AndData, and writes the result to the 32-bit PCI 1N/A configuration register specified by Address. The value written to the PCI 1N/A configuration register is returned. This function must guarantee that all PCI 1N/A read and write operations are serialized. Extra left bits in both AndData and 1N/A OrData are stripped. 1N/A If Address > 0x0FFFFFFF, then ASSERT(). 1N/A If Address is not aligned on a 32-bit boundary, then ASSERT(). 1N/A If StartBit is greater than 31, then ASSERT(). 1N/A If EndBit is greater than 31, then ASSERT(). 1N/A If EndBit is less than StartBit, then ASSERT(). 1N/A @param Address The PCI configuration register to write. 1N/A @param StartBit The ordinal of the least significant bit in the bit field. 1N/A @param EndBit The ordinal of the most significant bit in the bit field. 1N/A @param AndData The value to AND with the PCI configuration register. 1N/A @param OrData The value to OR with the result of the AND operation. 1N/A @return The value written back to the PCI configuration register. 1N/A Reads a range of PCI configuration registers into a caller supplied buffer. 1N/A Reads the range of PCI configuration registers specified by StartAddress and 1N/A Size into the buffer specified by Buffer. This function only allows the PCI 1N/A configuration registers from a single PCI function to be read. Size is 1N/A returned. When possible 32-bit PCI configuration read cycles are used to read 1N/A from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit 1N/A and 16-bit PCI configuration read cycles may be used at the beginning and the 1N/A If StartAddress > 0x0FFFFFFF, then ASSERT(). 1N/A If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). 1N/A If Size > 0 and Buffer is NULL, then ASSERT(). 1N/A @param StartAddress The starting address that encodes the PCI Bus, Device, 1N/A Function and Register. 1N/A @param Size The size in bytes of the transfer. 1N/A @param Buffer The pointer to a buffer receiving the data read. 1N/A Copies the data in a caller supplied buffer to a specified range of PCI 1N/A configuration space. 1N/A Writes the range of PCI configuration registers specified by StartAddress and 1N/A Size from the buffer specified by Buffer. This function only allows the PCI 1N/A configuration registers from a single PCI function to be written. Size is 1N/A returned. When possible 32-bit PCI configuration write cycles are used to 1N/A write from StartAdress to StartAddress + Size. Due to alignment restrictions, 1N/A 8-bit and 16-bit PCI configuration write cycles may be used at the beginning 1N/A and the end of the range. 1N/A If StartAddress > 0x0FFFFFFF, then ASSERT(). 1N/A If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). 1N/A If Size > 0 and Buffer is NULL, then ASSERT(). 1N/A @param StartAddress The starting address that encodes the PCI Bus, Device, 1N/A Function and Register. 1N/A @param Size The size in bytes of the transfer. 1N/A @param Buffer The pointer to a buffer containing the data to write. 1N/A @return Size written to StartAddress.