ee6da855ccebdd8b5dc295447420b0607757b431vboxsync Cache Maintenance Functions.
ee6da855ccebdd8b5dc295447420b0607757b431vboxsync Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
ee6da855ccebdd8b5dc295447420b0607757b431vboxsync This program and the accompanying materials
ee6da855ccebdd8b5dc295447420b0607757b431vboxsync are licensed and made available under the terms and conditions of the BSD License
d4c0b01d95e56701ccb5a430fea1a36dc671153bvboxsync which accompanies this distribution. The full text of the license may be found at
ee6da855ccebdd8b5dc295447420b0607757b431vboxsync THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
ee6da855ccebdd8b5dc295447420b0607757b431vboxsync WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
88c355789359ed9e72ed456a617ccd59d7b0f69avboxsync Invalidates the entire instruction cache in cache coherency domain of the
ee6da855ccebdd8b5dc295447420b0607757b431vboxsync calling CPU.
30ddfc88ff06def267c2ffd1b750cc5fe6c310f2vboxsync PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
fccc59981ee96f9e392fbfa0ab3a378d9732ea4evboxsync Invalidates a range of instruction cache lines in the cache coherency domain
a728d62d1cdd12794b98aa645532cdb35b995b6evboxsync of the calling CPU.
1f17f33cc8338f56a4ca17ac85bca4e373663bf5vboxsync Invalidates the instruction cache lines specified by Address and Length. If
04982697b03f25ee4738b26d1c6a2b26bf06c9e7vboxsync Address is not aligned on a cache line boundary, then entire instruction
04982697b03f25ee4738b26d1c6a2b26bf06c9e7vboxsync cache line containing Address is invalidated. If Address + Length is not
321713c8724d53a5563eda3a70ab0f3830fd9e16vboxsync aligned on a cache line boundary, then the entire instruction cache line
1aaa4b75cfc9f222c4308fcb10f44d3aeb3b017dvboxsync containing Address + Length -1 is invalidated. This function may choose to
9ca017ceee656f9d33f2cb6652e401b5f17fcfb7vboxsync invalidate the entire instruction cache if that is more efficient than
9ca017ceee656f9d33f2cb6652e401b5f17fcfb7vboxsync invalidating the specified range. If Length is 0, then no instruction cache
9ca017ceee656f9d33f2cb6652e401b5f17fcfb7vboxsync lines are invalidated. Address is returned.
9ca017ceee656f9d33f2cb6652e401b5f17fcfb7vboxsync If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
9ca017ceee656f9d33f2cb6652e401b5f17fcfb7vboxsync @param Address The base address of the instruction cache lines to
ee6da855ccebdd8b5dc295447420b0607757b431vboxsync invalidate. If the CPU is in a physical addressing mode, then
ee6da855ccebdd8b5dc295447420b0607757b431vboxsync Address is a physical address. If the CPU is in a virtual
ee6da855ccebdd8b5dc295447420b0607757b431vboxsync addressing mode, then Address is a virtual address.
ee6da855ccebdd8b5dc295447420b0607757b431vboxsync @param Length The number of bytes to invalidate from the instruction cache.
ee6da855ccebdd8b5dc295447420b0607757b431vboxsync @return Address.
c4838583fda41f70290ca79ce09e743db0d33488vboxsync Writes back and invalidates the entire data cache in cache coherency domain
c4838583fda41f70290ca79ce09e743db0d33488vboxsync of the calling CPU.
ff525c9827feb8097b272c36e3f0ab91e745f0ffvboxsync Writes back and invalidates the entire data cache in cache coherency domain
ff525c9827feb8097b272c36e3f0ab91e745f0ffvboxsync of the calling CPU. This function guarantees that all dirty cache lines are
ff525c9827feb8097b272c36e3f0ab91e745f0ffvboxsync written back to system memory, and also invalidates all the data cache lines
d70f332ce412cf75187ceda26709e58e4edc69ecvboxsync in the cache coherency domain of the calling CPU.
d4c0b01d95e56701ccb5a430fea1a36dc671153bvboxsync PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
d4c0b01d95e56701ccb5a430fea1a36dc671153bvboxsync Writes back and invalidates a range of data cache lines in the cache
d4c0b01d95e56701ccb5a430fea1a36dc671153bvboxsync coherency domain of the calling CPU.
f9bbb477594efad6aaf8accca9a83a2071158f98vboxsync Writes back and invalidates the data cache lines specified by Address and
f9bbb477594efad6aaf8accca9a83a2071158f98vboxsync Length. If Address is not aligned on a cache line boundary, then entire data
f9bbb477594efad6aaf8accca9a83a2071158f98vboxsync cache line containing Address is written back and invalidated. If Address +
f9bbb477594efad6aaf8accca9a83a2071158f98vboxsync Length is not aligned on a cache line boundary, then the entire data cache
f9bbb477594efad6aaf8accca9a83a2071158f98vboxsync line containing Address + Length -1 is written back and invalidated. This
f9bbb477594efad6aaf8accca9a83a2071158f98vboxsync function may choose to write back and invalidate the entire data cache if
f9bbb477594efad6aaf8accca9a83a2071158f98vboxsync that is more efficient than writing back and invalidating the specified
8f574d4912727ef7f831a29e3f836a04b0261392vboxsync range. If Length is 0, then no data cache lines are written back and
f9bbb477594efad6aaf8accca9a83a2071158f98vboxsync invalidated. Address is returned.
f9bbb477594efad6aaf8accca9a83a2071158f98vboxsync If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
f9bbb477594efad6aaf8accca9a83a2071158f98vboxsync @param Address The base address of the data cache lines to write back and
f9bbb477594efad6aaf8accca9a83a2071158f98vboxsync invalidate. If the CPU is in a physical addressing mode, then
f9bbb477594efad6aaf8accca9a83a2071158f98vboxsync Address is a physical address. If the CPU is in a virtual
f9bbb477594efad6aaf8accca9a83a2071158f98vboxsync addressing mode, then Address is a virtual address.
97b672c60368db8e7ba24563e516fc308e73b192vboxsync @param Length The number of bytes to write back and invalidate from the
f9bbb477594efad6aaf8accca9a83a2071158f98vboxsync data cache.
f9bbb477594efad6aaf8accca9a83a2071158f98vboxsync @return Address of cache invalidation.
8f574d4912727ef7f831a29e3f836a04b0261392vboxsync Writes Back the entire data cache in cache coherency domain of the calling
8f574d4912727ef7f831a29e3f836a04b0261392vboxsync Writes Back the entire data cache in cache coherency domain of the calling
8f574d4912727ef7f831a29e3f836a04b0261392vboxsync CPU. This function guarantees that all dirty cache lines are written back to
8f574d4912727ef7f831a29e3f836a04b0261392vboxsync system memory. This function may also invalidate all the data cache lines in
8f574d4912727ef7f831a29e3f836a04b0261392vboxsync the cache coherency domain of the calling CPU.
df6a45e2f3db089eb8e0491a9a8abb4548327c85vboxsync PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_NO_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
2c55518088b033c1bddc9e854b9537518b2abbc6vboxsync Writes Back a range of data cache lines in the cache coherency domain of the
2c55518088b033c1bddc9e854b9537518b2abbc6vboxsync calling CPU.
2c55518088b033c1bddc9e854b9537518b2abbc6vboxsync Writes Back the data cache lines specified by Address and Length. If Address
2c55518088b033c1bddc9e854b9537518b2abbc6vboxsync is not aligned on a cache line boundary, then entire data cache line
2c55518088b033c1bddc9e854b9537518b2abbc6vboxsync containing Address is written back. If Address + Length is not aligned on a
2c55518088b033c1bddc9e854b9537518b2abbc6vboxsync cache line boundary, then the entire data cache line containing Address +
2c55518088b033c1bddc9e854b9537518b2abbc6vboxsync Length -1 is written back. This function may choose to write back the entire
0158d474771d8cf8fb0bfbbe297d3f9b74de04ccvboxsync data cache if that is more efficient than writing back the specified range.
0158d474771d8cf8fb0bfbbe297d3f9b74de04ccvboxsync If Length is 0, then no data cache lines are written back. This function may
0158d474771d8cf8fb0bfbbe297d3f9b74de04ccvboxsync also invalidate all the data cache lines in the specified range of the cache
0158d474771d8cf8fb0bfbbe297d3f9b74de04ccvboxsync coherency domain of the calling CPU. Address is returned.
0158d474771d8cf8fb0bfbbe297d3f9b74de04ccvboxsync If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
0158d474771d8cf8fb0bfbbe297d3f9b74de04ccvboxsync @param Address The base address of the data cache lines to write back. If
d35d319b9a415c443751e23006d9a8e7b1a9660fvboxsync the CPU is in a physical addressing mode, then Address is a
d35d319b9a415c443751e23006d9a8e7b1a9660fvboxsync physical address. If the CPU is in a virtual addressing
d35d319b9a415c443751e23006d9a8e7b1a9660fvboxsync mode, then Address is a virtual address.
d35d319b9a415c443751e23006d9a8e7b1a9660fvboxsync @param Length The number of bytes to write back from the data cache.
d35d319b9a415c443751e23006d9a8e7b1a9660fvboxsync @return Address of cache written in main memory.
ee6da855ccebdd8b5dc295447420b0607757b431vboxsync Invalidates the entire data cache in cache coherency domain of the calling
f6adf1a86574758258baa232172c965aed0d848dvboxsync Invalidates the entire data cache in cache coherency domain of the calling
VOID *