4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Cache Maintenance Functions.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This program and the accompanying materials
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync are licensed and made available under the terms and conditions of the BSD License
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync which accompanies this distribution. The full text of the license may be found at
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Invalidates the entire instruction cache in cache coherency domain of the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync calling CPU.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Invalidates a range of instruction cache lines in the cache coherency domain
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync of the calling CPU.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Invalidates the instruction cache lines specified by Address and Length. If
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Address is not aligned on a cache line boundary, then entire instruction
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync cache line containing Address is invalidated. If Address + Length is not
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync aligned on a cache line boundary, then the entire instruction cache line
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync containing Address + Length -1 is invalidated. This function may choose to
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync invalidate the entire instruction cache if that is more efficient than
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync invalidating the specified range. If Length is 0, then no instruction cache
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync lines are invalidated. Address is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The base address of the instruction cache lines to
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync invalidate. If the CPU is in a physical addressing mode, then
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Address is a physical address. If the CPU is in a virtual
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync addressing mode, then Address is a virtual address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Length The number of bytes to invalidate from the instruction cache.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return Address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes back and invalidates the entire data cache in cache coherency domain
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync of the calling CPU.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes back and invalidates the entire data cache in cache coherency domain
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync of the calling CPU. This function guarantees that all dirty cache lines are
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync written back to system memory, and also invalidates all the data cache lines
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync in the cache coherency domain of the calling CPU.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes back and invalidates a range of data cache lines in the cache
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync coherency domain of the calling CPU.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes Back and Invalidate the data cache lines specified by Address and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Length. If Address is not aligned on a cache line boundary, then entire data
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync cache line containing Address is written back and invalidated. If Address +
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Length is not aligned on a cache line boundary, then the entire data cache
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync line containing Address + Length -1 is written back and invalidated. This
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync function may choose to write back and invalidate the entire data cache if
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync that is more efficient than writing back and invalidating the specified
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync range. If Length is 0, then no data cache lines are written back and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync invalidated. Address is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The base address of the data cache lines to write back and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync invalidate. If the CPU is in a physical addressing mode, then
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Address is a physical address. If the CPU is in a virtual
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync addressing mode, then Address is a virtual address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Length The number of bytes to write back and invalidate from the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync data cache.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return Address of cache invalidation.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes back the entire data cache in cache coherency domain of the calling
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes back the entire data cache in cache coherency domain of the calling
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync CPU. This function guarantees that all dirty cache lines are written back to
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync system memory. This function may also invalidate all the data cache lines in
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync the cache coherency domain of the calling CPU.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes back a range of data cache lines in the cache coherency domain of the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync calling CPU.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Writes back the data cache lines specified by Address and Length. If Address
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync is not aligned on a cache line boundary, then entire data cache line
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync containing Address is written back. If Address + Length is not aligned on a
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync cache line boundary, then the entire data cache line containing Address +
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Length -1 is written back. This function may choose to write back the entire
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync data cache if that is more efficient than writing back the specified range.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Length is 0, then no data cache lines are written back. This function may
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync also invalidate all the data cache lines in the specified range of the cache
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync coherency domain of the calling CPU. Address is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The base address of the data cache lines to write back. If
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync the CPU is in a physical addressing mode, then Address is a
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync physical address. If the CPU is in a virtual addressing
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mode, then Address is a virtual address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Length The number of bytes to write back from the data cache.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return Address of cache written in main memory.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Invalidates the entire data cache in cache coherency domain of the calling
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Invalidates the entire data cache in cache coherency domain of the calling
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync CPU. This function must be used with care because dirty cache lines are not
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync written back to system memory. It is typically used for cache diagnostics. If
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync the CPU does not support invalidation of the entire data cache, then a write
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync back and invalidate operation should be performed on the entire data cache.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Invalidates a range of data cache lines in the cache coherency domain of the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync calling CPU.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Invalidates the data cache lines specified by Address and Length. If Address
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync is not aligned on a cache line boundary, then entire data cache line
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync containing Address is invalidated. If Address + Length is not aligned on a
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync cache line boundary, then the entire data cache line containing Address +
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Length -1 is invalidated. This function must never invalidate any cache lines
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync outside the specified range. If Length is 0, then no data cache lines are
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync invalidated. Address is returned. This function must be used with care
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync because dirty cache lines are not written back to system memory. It is
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync typically used for cache diagnostics. If the CPU does not support
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync invalidation of a data cache range, then a write back and invalidate
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync operation should be performed on the data cache range.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address The base address of the data cache lines to invalidate. If
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync the CPU is in a physical addressing mode, then Address is a
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync physical address. If the CPU is in a virtual addressing mode,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync then Address is a virtual address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Length The number of bytes to invalidate from the data cache.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return Address.