Pci22.h revision 4fd606d1f5abe38e1f42c38de1d2e895166bd0f4
/** @file
Support for PCI 2.2 standard.
This file includes the definitions in the following specifications,
PCI Local Bus Specification, 2.2
PCI-to-PCI Bridge Architecture Specification, Revision 1.2
PC Card Standard, 8.0
Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _PCI22_H_
#define _PCI22_H_
#define PCI_MAX_BUS 255
#define PCI_MAX_DEVICE 31
#define PCI_MAX_FUNC 7
#pragma pack(1)
///
/// Common header region in PCI Configuration Space
/// Section 6.1, PCI Local Bus Specification, 2.2
///
typedef struct {
///
/// PCI Device header region in PCI Configuration Space
/// Section 6.1, PCI Local Bus Specification, 2.2
///
typedef struct {
///
/// PCI Device Configuration Space
/// Section 6.1, PCI Local Bus Specification, 2.2
///
typedef struct {
} PCI_TYPE00;
///
/// PCI-PCI Bridge header region in PCI Configuration Space
/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
///
typedef struct {
///
/// PCI-to-PCI Bridge Configuration Space
/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
///
typedef struct {
} PCI_TYPE01;
typedef union {
///
/// CardBus Conroller Configuration Space,
/// Section 4.5.1, PC Card Standard. 8.0
///
typedef struct {
//
// Definitions of PCI class bytes and manipulation macros.
//
#define PCI_CLASS_OLD 0x00
#define PCI_CLASS_OLD_OTHER 0x00
#define PCI_CLASS_OLD_VGA 0x01
#define PCI_CLASS_MASS_STORAGE 0x01
#define PCI_CLASS_MASS_STORAGE_SCSI 0x00
#define PCI_CLASS_MASS_STORAGE_IDE 0x01
#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
#define PCI_CLASS_MASS_STORAGE_IPI 0x03
#define PCI_CLASS_MASS_STORAGE_RAID 0x04
#define PCI_CLASS_MASS_STORAGE_OTHER 0x80
#define PCI_CLASS_NETWORK 0x02
#define PCI_CLASS_NETWORK_ETHERNET 0x00
#define PCI_CLASS_NETWORK_TOKENRING 0x01
#define PCI_CLASS_NETWORK_FDDI 0x02
#define PCI_CLASS_NETWORK_ATM 0x03
#define PCI_CLASS_NETWORK_ISDN 0x04
#define PCI_CLASS_NETWORK_OTHER 0x80
#define PCI_CLASS_DISPLAY 0x03
#define PCI_CLASS_DISPLAY_VGA 0x00
#define PCI_IF_VGA_VGA 0x00
#define PCI_IF_VGA_8514 0x01
#define PCI_CLASS_DISPLAY_XGA 0x01
#define PCI_CLASS_DISPLAY_3D 0x02
#define PCI_CLASS_DISPLAY_OTHER 0x80
#define PCI_CLASS_MEDIA 0x04
#define PCI_CLASS_MEDIA_VIDEO 0x00
#define PCI_CLASS_MEDIA_AUDIO 0x01
#define PCI_CLASS_MEDIA_TELEPHONE 0x02
#define PCI_CLASS_MEDIA_OTHER 0x80
#define PCI_CLASS_MEMORY_CONTROLLER 0x05
#define PCI_CLASS_MEMORY_RAM 0x00
#define PCI_CLASS_MEMORY_FLASH 0x01
#define PCI_CLASS_MEMORY_OTHER 0x80
#define PCI_CLASS_BRIDGE 0x06
#define PCI_CLASS_BRIDGE_HOST 0x00
#define PCI_CLASS_BRIDGE_ISA 0x01
#define PCI_CLASS_BRIDGE_EISA 0x02
#define PCI_CLASS_BRIDGE_MCA 0x03
#define PCI_CLASS_BRIDGE_P2P 0x04
#define PCI_IF_BRIDGE_P2P 0x00
#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
#define PCI_CLASS_BRIDGE_PCMCIA 0x05
#define PCI_CLASS_BRIDGE_NUBUS 0x06
#define PCI_CLASS_BRIDGE_CARDBUS 0x07
#define PCI_CLASS_BRIDGE_RACEWAY 0x08
#define PCI_CLASS_BRIDGE_OTHER 0x80
#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
#define PCI_SUBCLASS_SERIAL 0x00
#define PCI_IF_GENERIC_XT 0x00
#define PCI_IF_16450 0x01
#define PCI_IF_16550 0x02
#define PCI_IF_16650 0x03
#define PCI_IF_16750 0x04
#define PCI_IF_16850 0x05
#define PCI_IF_16950 0x06
#define PCI_SUBCLASS_PARALLEL 0x01
#define PCI_IF_PARALLEL_PORT 0x00
#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
#define PCI_IF_ECP_PARALLEL_PORT 0x02
#define PCI_IF_1284_CONTROLLER 0x03
#define PCI_IF_1284_DEVICE 0xFE
#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
#define PCI_SUBCLASS_MODEM 0x03
#define PCI_IF_GENERIC_MODEM 0x00
#define PCI_IF_16450_MODEM 0x01
#define PCI_IF_16550_MODEM 0x02
#define PCI_IF_16650_MODEM 0x03
#define PCI_IF_16750_MODEM 0x04
#define PCI_SUBCLASS_SCC_OTHER 0x80
#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
#define PCI_SUBCLASS_PIC 0x00
#define PCI_IF_8259_PIC 0x00
#define PCI_IF_ISA_PIC 0x01
#define PCI_IF_EISA_PIC 0x02
#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.
#define PCI_IF_APIC_CONTROLLER2 0x20
#define PCI_SUBCLASS_DMA 0x01
#define PCI_IF_8237_DMA 0x00
#define PCI_IF_ISA_DMA 0x01
#define PCI_IF_EISA_DMA 0x02
#define PCI_SUBCLASS_TIMER 0x02
#define PCI_IF_8254_TIMER 0x00
#define PCI_IF_ISA_TIMER 0x01
#define PCI_IF_EISA_TIMER 0x02
#define PCI_SUBCLASS_RTC 0x03
#define PCI_IF_GENERIC_RTC 0x00
#define PCI_IF_ISA_RTC 0x00
#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
#define PCI_CLASS_INPUT_DEVICE 0x09
#define PCI_SUBCLASS_KEYBOARD 0x00
#define PCI_SUBCLASS_PEN 0x01
#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
#define PCI_SUBCLASS_GAMEPORT 0x04
#define PCI_IF_GAMEPORT 0x00
#define PCI_IF_GAMEPORT1 0x01
#define PCI_SUBCLASS_INPUT_OTHER 0x80
#define PCI_CLASS_DOCKING_STATION 0x0A
#define PCI_CLASS_PROCESSOR 0x0B
#define PCI_SUBCLASS_PROC_386 0x00
#define PCI_SUBCLASS_PROC_486 0x01
#define PCI_SUBCLASS_PROC_PENTIUM 0x02
#define PCI_SUBCLASS_PROC_ALPHA 0x10
#define PCI_SUBCLASS_PROC_POWERPC 0x20
#define PCI_SUBCLASS_PROC_MIPS 0x30
#define PCI_CLASS_SERIAL 0x0C
#define PCI_CLASS_SERIAL_FIREWIRE 0x00
#define PCI_IF_1394 0x00
#define PCI_IF_1394_OPEN_HCI 0x10
#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
#define PCI_CLASS_SERIAL_SSA 0x02
#define PCI_CLASS_SERIAL_USB 0x03
#define PCI_IF_UHCI 0x00
#define PCI_IF_OHCI 0x10
#define PCI_IF_USB_OTHER 0x80
#define PCI_IF_USB_DEVICE 0xFE
#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
#define PCI_CLASS_SERIAL_SMB 0x05
#define PCI_CLASS_WIRELESS 0x0D
#define PCI_SUBCLASS_IRDA 0x00
#define PCI_SUBCLASS_IR 0x01
#define PCI_SUBCLASS_RF 0x02
#define PCI_SUBCLASS_WIRELESS_OTHER 0x80
#define PCI_CLASS_INTELLIGENT_IO 0x0E
#define PCI_CLASS_SATELLITE 0x0F
#define PCI_SUBCLASS_TV 0x01
#define PCI_SUBCLASS_AUDIO 0x02
#define PCI_SUBCLASS_VOICE 0x03
#define PCI_SUBCLASS_DATA 0x04
#define PCI_SUBCLASS_NET_COMPUT 0x00
#define PCI_SUBCLASS_ENTERTAINMENT 0x10
#define PCI_SUBCLASS_SECURITY_OTHER 0x80
#define PCI_CLASS_DPIO 0x11
#define PCI_SUBCLASS_DPIO 0x00
#define PCI_SUBCLASS_DPIO_OTHER 0x80
/**
Macro that checks whether the Base Class code of device matched.
@param _p Specified device.
@param c Base Class code needs matching.
@retval TRUE Base Class code matches the specified device.
@retval FALSE Base Class code doesn't match the specified device.
**/
/**
Macro that checks whether the Base Class code and Sub-Class code of device matched.
@param _p Specified device.
@param c Base Class code needs matching.
@param s Sub-Class code needs matching.
@retval TRUE Base Class code and Sub-Class code match the specified device.
@retval FALSE Base Class code and Sub-Class code don't match the specified device.
**/
/**
Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.
@param _p Specified device.
@param c Base Class code needs matching.
@param s Sub-Class code needs matching.
@param p Interface code needs matching.
@retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.
@retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device.
**/
/**
Macro that checks whether device is a display controller.
@param _p Specified device.
@retval TRUE Device is a display controller.
@retval FALSE Device is not a display controller.
**/
/**
Macro that checks whether device is a VGA-compatible controller.
@param _p Specified device.
@retval TRUE Device is a VGA-compatible controller.
@retval FALSE Device is not a VGA-compatible controller.
**/
/**
Macro that checks whether device is an 8514-compatible controller.
@param _p Specified device.
@retval TRUE Device is an 8514-compatible controller.
@retval FALSE Device is not an 8514-compatible controller.
**/
/**
Macro that checks whether device is built before the Class Code field was defined.
@param _p Specified device.
@retval TRUE Device is an old device.
@retval FALSE Device is not an old device.
**/
/**
Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.
@param _p Specified device.
@retval TRUE Device is an old VGA-compatible device.
@retval FALSE Device is not an old VGA-compatible device.
**/
/**
Macro that checks whether device is an IDE controller.
@param _p Specified device.
@retval TRUE Device is an IDE controller.
@retval FALSE Device is not an IDE controller.
**/
/**
Macro that checks whether device is a SCSI bus controller.
@param _p Specified device.
@retval TRUE Device is a SCSI bus controller.
@retval FALSE Device is not a SCSI bus controller.
**/
/**
Macro that checks whether device is a RAID controller.
@param _p Specified device.
@retval TRUE Device is a RAID controller.
@retval FALSE Device is not a RAID controller.
**/
/**
Macro that checks whether device is an ISA bridge.
@param _p Specified device.
@retval TRUE Device is an ISA bridge.
@retval FALSE Device is not an ISA bridge.
**/
/**
Macro that checks whether device is a PCI-to-PCI bridge.
@param _p Specified device.
@retval TRUE Device is a PCI-to-PCI bridge.
@retval FALSE Device is not a PCI-to-PCI bridge.
**/
/**
Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.
@param _p Specified device.
@retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge.
@retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.
**/
#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
/**
Macro that checks whether device is a 16550-compatible serial controller.
@param _p Specified device.
@retval TRUE Device is a 16550-compatible serial controller.
@retval FALSE Device is not a 16550-compatible serial controller.
**/
/**
Macro that checks whether device is a Universal Serial Bus controller.
@param _p Specified device.
@retval TRUE Device is a Universal Serial Bus controller.
@retval FALSE Device is not a Universal Serial Bus controller.
**/
//
// the definition of Header Type
//
#define HEADER_TYPE_DEVICE 0x00
#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
#define HEADER_TYPE_CARDBUS_BRIDGE 0x02
#define HEADER_TYPE_MULTI_FUNCTION 0x80
//
// Mask of Header type
//
#define HEADER_LAYOUT_CODE 0x7f
/**
Macro that checks whether device is a PCI-PCI bridge.
@param _p Specified device.
@retval TRUE Device is a PCI-PCI bridge.
@retval FALSE Device is not a PCI-PCI bridge.
**/
#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
/**
Macro that checks whether device is a CardBus bridge.
@param _p Specified device.
@retval TRUE Device is a CardBus bridge.
@retval FALSE Device is not a CardBus bridge.
**/
#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
/**
Macro that checks whether device is a multiple functions device.
@param _p Specified device.
@retval TRUE Device is a multiple functions device.
@retval FALSE Device is not a multiple functions device.
**/
///
/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,
///
#define PCI_BRIDGE_ROMBAR 0x38
#define PCI_MAX_BAR 0x0006
#define PCI_MAX_CONFIG_OFFSET 0x0100
#define PCI_VENDOR_ID_OFFSET 0x00
#define PCI_DEVICE_ID_OFFSET 0x02
#define PCI_COMMAND_OFFSET 0x04
#define PCI_PRIMARY_STATUS_OFFSET 0x06
#define PCI_REVISION_ID_OFFSET 0x08
#define PCI_CLASSCODE_OFFSET 0x09
#define PCI_CACHELINE_SIZE_OFFSET 0x0C
#define PCI_LATENCY_TIMER_OFFSET 0x0D
#define PCI_HEADER_TYPE_OFFSET 0x0E
#define PCI_BIST_OFFSET 0x0F
#define PCI_BASE_ADDRESSREG_OFFSET 0x10
#define PCI_CARDBUS_CIS_OFFSET 0x28
#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
#define PCI_SUBSYSTEM_ID_OFFSET 0x2E
#define PCI_EXPANSION_ROM_BASE 0x30
#define PCI_CAPBILITY_POINTER_OFFSET 0x34
//
// defined in PCI-to-PCI Bridge Architecture Specification
//
#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
///
/// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
///
#define PCI_INT_LINE_UNKNOWN 0xFF
///
/// PCI Access Data Format
///
typedef union {
struct {
} Bits;
#pragma pack()
//
// defined in PCI-to-PCI Bridge Architecture Specification
//
//
// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard
//
//
// Following are the PCI status control bit
//
///
/// defined in PC Card Standard
///
#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
#pragma pack(1)
//
// PCI Capability List IDs and records
//
#define EFI_PCI_CAPABILITY_ID_PMI 0x01
#define EFI_PCI_CAPABILITY_ID_AGP 0x02
#define EFI_PCI_CAPABILITY_ID_VPD 0x03
#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
#define EFI_PCI_CAPABILITY_ID_MSI 0x05
#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
///
/// Capabilities List Header
/// Section 6.7, PCI Local Bus Specification, 2.2
///
typedef struct {
///
/// Power Management Register Block Definition
/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2
///
typedef struct {
///
/// A.G.P Capability
/// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0
///
typedef struct {
///
/// VPD Capability Structure
/// Appendix I, PCI Local Bus Specification, 2.2
///
typedef struct {
///
/// Slot Numbering Capabilities Register
/// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2
///
typedef struct {
///
/// Message Capability Structure for 32-bit Message Address
/// Section 6.8.1, PCI Local Bus Specification, 2.2
///
typedef struct {
///
/// Message Capability Structure for 64-bit Message Address
/// Section 6.8.1, PCI Local Bus Specification, 2.2
///
typedef struct {
///
/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,
/// CompactPCI Hot Swap Specification PICMG 2.1, R1.0
///
typedef struct {
///
/// not finished - fields need to go here
///
#define DEVICE_ID_NOCARE 0xFFFF
#define PCI_ACPI_UNUSED 0
#define PCI_BAR_NOCHANGE 0
#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
#define PCI_BAR_IDX0 0x00
#define PCI_BAR_IDX1 0x01
#define PCI_BAR_IDX2 0x02
#define PCI_BAR_IDX3 0x03
#define PCI_BAR_IDX4 0x04
#define PCI_BAR_IDX5 0x05
#define PCI_BAR_ALL 0xFF
///
/// EFI PCI Option ROM definitions
///
#define EFI_ROOT_BRIDGE_LIST 'eprb'
#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
#define PCI_CODE_TYPE_PCAT_IMAGE 0x00
///
/// Standard PCI Expansion ROM Header
/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
///
typedef struct {
///
/// Legacy ROM Header Extensions
/// Section 6.3.3.1, PCI Local Bus Specification, 2.2
///
typedef struct {
///
/// PCI Data Structure Format
/// Section 6.3.1.2, PCI Local Bus Specification, 2.2
///
typedef struct {
///
/// EFI PCI Expansion ROM Header
/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
///
typedef struct {
typedef union {
#pragma pack()
#endif