4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Define the PPI to abstract the functions that enable IDE and SATA channels, and to retrieve
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync the base I/O port address for each of the enabled IDE and SATA channels.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncCopyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncThis program and the accompanying materials
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncare licensed and made available under the terms and conditions
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncof the BSD License which accompanies this distribution. The
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncfull text of the license may be found at
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncTHE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncWITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// Global ID for the PEI_ATA_CONTROLLER_PPI.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync 0xa45e60d1, 0xc719, 0x44aa, {0xb0, 0x7a, 0xaa, 0x77, 0x7f, 0x85, 0x90, 0x6d } \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// Forward declaration for the PEI_ATA_CONTROLLER_PPI.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsynctypedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// disable the IDE channels.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// This is designed for old generation chipset with PATA/SATA controllers.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// It may be ignored in PPI implementation for new generation chipset without PATA controller.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// enable the Primary IDE channel.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// This is designed for old generation chipset with PATA/SATA controllers.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// It may be ignored in PPI implementation for new generation chipset without PATA controller.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// enable the Secondary IDE channel.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// This is designed for old generation chipset with PATA/SATA controllers.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// It may be ignored in PPI implementation for new generation chipset without PATA controller.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// disable the SATA channel.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// This is designed for old generation chipset with PATA/SATA controllers.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// It may be ignored in PPI implementation for new generation chipset without PATA controller.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// enable the Primary SATA channel.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// This is designed for old generation chipset with PATA/SATA controllers.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// It may be ignored in PPI implementation for new generation chipset without PATA controller.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// enable the Secondary SATA channel.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// This is designed for old generation chipset with PATA/SATA controllers.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// It may be ignored in PPI implementation for new generation chipset without PATA controller.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// Structure that contains the base addresses for the IDE registers
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsynctypedef struct {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync /// Base I/O port address of the IDE controller's command block
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync /// Base I/O port address of the IDE controller's control block
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Sets IDE and SATA channels to an enabled or disabled state.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This service enables or disables the IDE and SATA channels specified by ChannelMask.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync It may ignore ChannelMask setting to enable or disable IDE and SATA channels based on the platform policy.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync The number of the enabled channels will be returned by GET_IDE_REGS_BASE_ADDR() function.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync If the new state is set, then EFI_SUCCESS is returned. If the new state can
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync not be set, then EFI_DEVICE_ERROR is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PeiServices The pointer to the PEI Services Table.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] This The pointer to this instance of the PEI_ATA_CONTROLLER_PPI.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] ChannelMask The bitmask that identifies the IDE and SATA channels to
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync enable or disable. This paramter is optional.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The IDE or SATA channels were enabled or disabled successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_DEVICE_ERROR The IDE or SATA channels could not be enabled or disabled.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Retrieves the I/O port base addresses for command and control registers of the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync enabled IDE/SATA channels.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This service fills in the structure poionted to by IdeRegsBaseAddr with the I/O
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync port base addresses for the command and control registers of the IDE and SATA
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync channels that were previously enabled in EnableAtaChannel(). The number of
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync enabled IDE and SATA channels is returned.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PeiServices The pointer to the PEI Services Table.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] This The pointer to this instance of the PEI_ATA_CONTROLLER_PPI.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[out] IdeRegsBaseAddr The pointer to caller allocated space to return the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync I/O port base addresses of the IDE and SATA channels
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync that were previosuly enabled with EnableAtaChannel().
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return The number of enabled IDE and SATA channels in the platform.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// This PPI contains services to enable and disable IDE and SATA channels and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/// retrieves the base I/O port addresses to the enabled IDE and SATA channels.