UhciQueue.c revision 4fd606d1f5abe38e1f42c38de1d2e895166bd0f4
/** @file
The UHCI register operation routines.
Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "Uhci.h"
/**
Map address of request structure buffer.
@param Uhc The UHCI device.
@param Request The user request buffer.
@param MappedAddr Mapped address of request.
@param Map Identificaion of this mapping to return.
@return EFI_SUCCESS Success.
@return EFI_DEVICE_ERROR Fail to map the user request.
**/
)
{
Len = sizeof (EFI_USB_DEVICE_REQUEST);
&Len,
&PhyAddr,
);
}
return Status;
}
/**
Map address of user data buffer.
@param Uhc The UHCI device.
@param Direction Direction of the data transfer.
@param Data The user data buffer.
@param Len Length of the user data.
@param PktId Packet identificaion.
@param MappedAddr Mapped address to return.
@param Map Identificaion of this mapping to return.
@return EFI_SUCCESS Success.
@return EFI_DEVICE_ERROR Fail to map the user data.
**/
)
{
switch (Direction) {
case EfiUsbDataIn:
//
// BusMasterWrite means cpu read
//
*PktId = INPUT_PACKET_ID;
Data,
Len,
&PhyAddr,
);
goto EXIT;
}
break;
case EfiUsbDataOut:
Data,
Len,
&PhyAddr,
);
goto EXIT;
}
break;
case EfiUsbNoData:
goto EXIT;
}
*MappedAddr = NULL;
break;
default:
}
EXIT:
return Status;
}
/**
Link the TD To QH.
@param Uhc The UHCI device.
@param Qh The queue head for the TD to link to.
@param Td The TD to link.
**/
)
{
}
/**
Unlink TD from the QH.
@param Qh The queue head to unlink from.
@param Td The TD to unlink.
**/
)
{
}
/**
Append a new TD To the previous TD.
@param Uhc The UHCI device.
@param PrevTd Previous UHCI_TD_SW to be linked to.
@param ThisTd TD to link.
**/
)
{
}
/**
Delete a list of TDs.
@param Uhc The UHCI device.
@param FirstTd TD link list head.
@return None.
**/
)
{
}
}
/**
Create an initialize a new queue head.
@param Uhc The UHCI device.
@param Interval The polling interval for the queue.
@return The newly created queue header.
**/
)
{
UHCI_QH_SW *Qh;
return NULL;
}
return Qh;
}
/**
Create and intialize a TD.
@param Uhc The UHCI device.
@return The newly allocated and initialized TD.
**/
)
{
UHCI_TD_SW *Td;
return NULL;
}
return Td;
}
/**
Create and initialize a TD for Setup Stage of a control transfer.
@param Uhc The UHCI device.
@param DevAddr Device address.
@param Request A pointer to cpu memory address of Device request.
@param RequestPhy A pointer to pci memory address of Device request.
@param IsLow Full speed or low speed.
@return The created setup Td Pointer.
**/
)
{
UHCI_TD_SW *Td;
return NULL;
}
return Td;
}
/**
Create a TD for data.
@param Uhc The UHCI device.
@param DevAddr Device address.
@param Endpoint Endpoint number.
@param DataPtr A pointer to cpu memory address of Data buffer.
@param DataPhyPtr A pointer to pci memory address of Data buffer.
@param Len Data length.
@param PktId Packet ID.
@param Toggle Data toggle value.
@param IsLow Full speed or low speed.
@return Data Td pointer if success, otherwise NULL.
**/
)
{
UHCI_TD_SW *Td;
//
// Code as length - 1, and the max valid length is 0x500
//
return NULL;
}
return Td;
}
/**
Create TD for the Status Stage of control transfer.
@param Uhc The UHCI device.
@param DevAddr Device address.
@param PktId Packet ID.
@param IsLow Full speed or low speed.
@return Status Td Pointer.
**/
)
{
UHCI_TD_SW *Td;
return NULL;
}
return Td;
}
/**
Create Tds list for Control Transfer.
@param Uhc The UHCI device.
@param DeviceAddr The device address.
@param DataPktId Packet Identification of Data Tds.
@param Request A pointer to cpu memory address of request structure buffer to transfer.
@param RequestPhy A pointer to pci memory address of request structure buffer to transfer.
@param Data A pointer to cpu memory address of user data buffer to transfer.
@param DataPhy A pointer to pci memory address of user data buffer to transfer.
@param DataLen Length of user data to transfer.
@param MaxPacket Maximum packet size for control transfer.
@param IsLow Full speed or low speed.
@return The Td list head for the control transfer.
**/
)
{
FirstDataTd = NULL;
PrevDataTd = NULL;
//
// Create setup packets for the transfer
//
return NULL;
}
//
// Create data packets for the transfer
//
DataToggle = 1;
while (DataLen > 0) {
//
// PktSize is the data load size in each Td.
//
Uhc,
0,
Data, //cpu memory address
DataPhy, //Pci memory address
);
goto FREE_TD;
}
if (FirstDataTd == NULL) {
} else {
}
DataToggle ^= 1;
PrevDataTd = DataTd;
}
//
// Status packet is on the opposite direction to data packets
//
if (OUTPUT_PACKET_ID == DataPktId) {
} else {
}
goto FREE_TD;
}
//
// Link setup Td -> data Tds -> status Td together
//
if (FirstDataTd != NULL) {
} else {
}
return SetupTd;
}
if (FirstDataTd != NULL) {
}
return NULL;
}
/**
@param Uhc USB_HC_DEV.
@param DevAddr Address of Device.
@param EndPoint Endpoint Number.
@param PktId Packet Identification of Data Tds.
@param Data A pointer to cpu memory address of user data buffer to transfer.
@param DataPhy A pointer to pci memory address of user data buffer to transfer.
@param DataLen Length of user data to transfer.
@param DataToggle Data Toggle Pointer.
@param IsLow Is Low Speed Device.
@return The Tds list head for the bulk transfer.
**/
)
{
FirstDataTd = NULL;
PrevDataTd = NULL;
//
// Create data packets for the transfer
//
while (DataLen > 0) {
//
// PktSize is the data load size that each Td.
//
}
Uhc,
Data,
);
goto FREE_TD;
}
if (PktId == INPUT_PACKET_ID) {
}
if (FirstDataTd == NULL) {
} else {
}
*DataToggle ^= 1;
PrevDataTd = DataTd;
}
return FirstDataTd;
if (FirstDataTd != NULL) {
}
return NULL;
}