EhciReg.h revision 4fd606d1f5abe38e1f42c38de1d2e895166bd0f4
/** @file
Private Header file for Usb Host Controller PEIM
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions
of the BSD License which accompanies this distribution. The
full text of the license may be found at
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _EFI_EHCI_REG_H_
#define _EFI_EHCI_REG_H_
//
// Capability register offset
//
#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
//
// Capability register bit definition
//
//
// Operational register offset
//
#define EHC_FRAME_LEN 1024
//
// Register bit definition
//
// (write clean) bits in USBSTS register
// they are WC (write clean)
//
// PCI Configuration Registers
//
#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
//
// Structure to map the hardware port states to the
// UEFI's port states.
//
typedef struct {
//
// Ehci Data and Ctrl Structures
//
#pragma pack(1)
typedef struct {
} USB_CLASSC;
#pragma pack()
/**
Read EHCI capability register.
@param Ehc The EHCI device.
@param Offset Capability register address.
@retval the register content read.
**/
)
;
/**
Read Ehc Operation register.
@param Ehc The EHCI device.
@param Offset The operation register offset.
@retval the register content read.
**/
)
;
/**
Write the data to the EHCI operation register.
@param Ehc The EHCI device.
@param Offset EHCI operation register offset.
@param Data The data to write.
**/
)
;
/**
Stop the legacy USB SMI support.
@param Ehc The EHCI device.
**/
)
;
/**
Set door bell and wait it to be ACKed by host controller.
This function is used to synchronize with the hardware.
@param Ehc The EHCI device.
@param Timeout The time to wait before abort (in millisecond, ms).
@retval EFI_TIMEOUT Time out happened while waiting door bell to set.
@retval EFI_SUCCESS Synchronized with the hardware.
**/
)
;
/**
Clear all the interrutp status bits, these bits
are Write-Clean.
@param Ehc The EHCI device.
**/
)
;
/**
Check whether Ehc is halted.
@param Ehc The EHCI device.
@retval TRUE The controller is halted.
@retval FALSE The controller isn't halted.
**/
)
;
/**
Check whether system error occurred.
@param Ehc The EHCI device.
@retval TRUE System error happened.
@retval FALSE No system error.
**/
)
;
/**
Reset the host controller.
@param Ehc The EHCI device.
@param Timeout Time to wait before abort (in millisecond, ms).
@retval EFI_TIMEOUT The transfer failed due to time out.
@retval Others Failed to reset the host.
**/
)
;
/**
Halt the host controller.
@param Ehc The EHCI device.
@param Timeout Time to wait before abort.
@retval EFI_TIMEOUT Failed to halt the controller before Timeout.
@retval EFI_SUCCESS The EHCI is halt.
**/
)
;
/**
Set the EHCI to run
@param Ehc The EHCI device.
@param Timeout Time to wait before abort.
@retval EFI_SUCCESS The EHCI is running.
@retval Others Failed to set the EHCI to run.
**/
EhcRunHC (
)
;
/**
Initialize the HC hardware.
EHCI spec lists the five things to do to initialize the hardware.
1. Program CTRLDSSEGMENT.
2. Set USBINTR to enable interrupts.
3. Set periodic list base.
4. Set USBCMD, interrupt threshold, frame list size etc.
5. Write 1 to CONFIGFLAG to route all ports to EHCI.
@param Ehc The EHCI device.
@retval EFI_SUCCESS The EHCI has come out of halt state.
@retval EFI_TIMEOUT Time out happened.
**/
)
;
#endif