4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncCopyright (c) 2004 - 2008, Intel Corporation. All rights reserved.<BR>
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncThis program and the accompanying materials
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncare licensed and made available under the terms and conditions of the BSD License
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncwhich accompanies this distribution. The full text of the license may be found at
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncTHE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncWITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncModule Name:
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync IA32, X64 and IPF Specific relocation fixups
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncRevision History
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define EXT_IMM64(Value, Address, Size, InstPos, ValPos) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Value |= (((UINT64)((*(Address) >> InstPos) & (((UINT64)1 << Size) - 1))) << ValPos)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define INS_IMM64(Value, Address, Size, InstPos, ValPos) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync *(UINT32*)Address = (*(UINT32*)Address & ~(((1 << Size) - 1) << InstPos)) | \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ((UINT32)((((UINT64)Value >> ValPos) & (((UINT64)1 << Size) - 1))) << InstPos)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncRoutine Description:
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Performs an IA-32 specific relocation fixup
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reloc - Pointer to the relocation record
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Fixup - Pointer to the address to fix up
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync FixupData - Pointer to a buffer to log the fixups
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Adjust - The offset to adjust the fixup
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync EFI_UNSUPPORTED - Unsupported now
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncRoutine Description:
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Performs an Itanium-based specific relocation fixup
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Reloc - Pointer to the relocation record
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Fixup - Pointer to the address to fix up
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync FixupData - Pointer to a buffer to log the fixups
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Adjust - The offset to adjust the fixup
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Status code
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync *FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Align it to bundle address before fixing up the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // 64-bit immediate value of the movl instruction.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Extract the lower 32 bits of IMM64 from bundle
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Update 64-bit address
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Insert IMM64 into bundle
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync *FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Performs an x64 specific relocation fixup
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Reloc Pointer to the relocation record
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Fixup Pointer to the address to fix up
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param FixupData Pointer to a buffer to log the fixups
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Adjust The offset to adjust the fixup
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval RETURN_SUCCESS Success to perform relocation
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval RETURN_UNSUPPORTED Unsupported.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync *FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Pass in a pointer to an ARM MOVT or MOVW immediate instruciton and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return the immediate data encoded in the instruction
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Instruction Pointer to ARM MOVT or MOVW immediate instruction
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return Immediate address encoded in the instruction
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Thumb2 is two 16-bit instructions working together. Not a single 32-bit instruction
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Example MOVT R0, #0 is 0x0000f2c0 or 0xf2c0 0x0000
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Movt = (*Instruction << 16) | (*(Instruction + 1));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // imm16 = imm4:i:imm3:imm8
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // imm4 -> Bit19:Bit16
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // i -> Bit26
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // imm3 -> Bit14:Bit12
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // imm8 -> Bit7:Bit0
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Address |= (UINT16)((Movt >> 4) & 0x0000f700); // imm4 imm3
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Address |= (((Movt & BIT26) != 0) ? BIT11 : 0); // i
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Update an ARM MOVT or MOVW immediate instruction immediate data.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Instruction Pointer to ARM MOVT or MOVW immediate instruction
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address New addres to patch into the instruction
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // First 16-bit chunk of instruciton
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Patch |= (((Address & BIT11) != 0) ? BIT10 : 0); // i
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Second 16-bit chunk of instruction
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Pass in a pointer to an ARM MOVW/MOVT instruciton pair and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return the immediate data encoded in the two` instruction
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Instructions Pointer to ARM MOVW/MOVT insturction pair
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return Immediate address encoded in the instructions
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync return (ThumbMovtImmediateAddress (Top) << 16) + ThumbMovtImmediateAddress (Word);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Update an ARM MOVW/MOVT immediate instruction instruction pair.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Instructions Pointer to ARM MOVW/MOVT instruction pair
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Address New addres to patch into the instructions
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ThumbMovtImmediatePatch (Word, (UINT16)(Address & 0xffff));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ThumbMovtImmediatePatch (Top, (UINT16)(Address >> 16));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Performs an ARM-based specific relocation fixup and is a no-op on other
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync instruction sets.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Reloc Pointer to the relocation record.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Fixup Pointer to the address to fix up.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param FixupData Pointer to a buffer to log the fixups.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Adjust The offset to adjust the fixup.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return Status code.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync FixupVal = ThumbMovwMovtImmediateAddress (Fixup16) + (UINT32)Adjust;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync *FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // break omitted - ARM instruction encoding not implemented