DevPciIch9.cpp revision ea0316554d23852601ee840c4a856339501411a4
/* $Id$ */
/** @file
* DevPCI - ICH9 southbridge PCI bus emulation Device.
*/
/*
* Copyright (C) 2010 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_DEV_PCI
/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
#define PCI_INCLUDE_PRIVATE
#include "../Builtins.h"
#include "MsiCommon.h"
/**
* PCI Bus instance.
*/
typedef struct PCIBus
{
/** Bus number. */
/** Number of bridges attached to the bus. */
/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
/** Array of bridges attached to the bus. */
/** R3 pointer to the device instance. */
/** Pointer to the PCI R3 helpers. */
/** R0 pointer to the device instance. */
/** Pointer to the PCI R0 helpers. */
/** RC pointer to the device instance. */
/** Pointer to the PCI RC helpers. */
/** The PCI device for the PCI bridge. */
/** @def PCI_IRQ_PINS
* Number of pins for interrupts (PIRQ#0...PIRQ#3)
*/
#define PCI_IRQ_PINS 4
/** @def PCI_APIC_IRQ_PINS
* Number of pins for interrupts if the APIC is used.
*/
#define PCI_APIC_IRQ_PINS 8
/**
* PCI Globals - This is the host-to-pci bridge and the root bus.
*/
typedef struct
{
/** R3 pointer to the device instance. */
/** R0 pointer to the device instance. */
/** RC pointer to the device instance. */
#if HC_ARCH_BITS == 64
#endif
/** I/O APIC irq levels */
#if 1 /* Will be moved into the BIOS soon. */
/** The next I/O port address which the PCI BIOS will use. */
/** The next MMIO address which the PCI BIOS will use. */
/** Actual bus number. */
#endif
/* Physical address of PCI config space MMIO region */
/* Length of PCI config space MMIO region */
/** Config register. */
/** PCI bus which is attached to the host-to-PCI bridge. */
} PCIGLOBALS, *PPCIGLOBALS;
typedef struct {
} PciAddress;
/*******************************************************************************
* Defined Constants And Macros *
*******************************************************************************/
/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
* Saved state version of the ICH9 PCI bus device.
*/
#define VBOX_ICH9PCI_SAVED_STATE_VERSION 1
/** Converts a bus instance pointer to a device instance pointer. */
/** Converts a device instance pointer to a PCIGLOBALS pointer. */
/** Converts a device instance pointer to a PCIBUS pointer. */
/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer.
*/
#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, aPciBus)) )
/** @def PCI_LOCK
* Acquires the PDM lock. This is a NOP if locking is disabled. */
/** @def PCI_UNLOCK
* Releases the PDM lock. This is a NOP if locking is disabled. */
do { \
if (rc2 != VINF_SUCCESS) \
return rc2; \
} while (0)
#define PCI_UNLOCK(pDevIns) \
#ifndef VBOX_DEVICE_STRUCT_TESTCASE
PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
/* Prototypes */
static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel);
#ifdef IN_RING3
static int ich9pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName);
static DECLCALLBACK(uint32_t) ich9pciConfigRead(PCIDevice *aDev, uint32_t u32Address, unsigned len);
static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions);
#endif
// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
// mapping, we take n=6 approach
DECLINLINE(void) ich9pciPhysToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
{
pPciAddr->iDeviceFunc = (GCPhysAddr >> 15) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
}
{
}
{
}
PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
{
/*
* The PCI-to-PCI bridge specification defines how the interrupt pins
* are routed from the secondary to the primary bus (see chapter 9).
* iIrq gives the interrupt pin the pci device asserted.
* We change iIrq here according to the spec and call the SetIrq function
* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
*/
int iIrqPinBridge = iIrq;
uint8_t uDevFnBridge = 0;
/* Walk the chain until we reach the host bus. */
do
{
/* Get the parent. */
}
/**
* Port I/O Handler for PCI address OUT operations.
*
* @returns VBox status code.
*
* @param pDevIns The device instance.
* @param pvUser User argument - ignored.
* @param uPort Port number used for the OUT operation.
* @param u32 The value to output.
* @param cb The value size in bytes.
*/
PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
{
if (cb == 4)
{
}
return VINF_SUCCESS;
}
/**
* Port I/O Handler for PCI address IN operations.
*
* @returns VBox status code.
*
* @param pDevIns The device instance.
* @param pvUser User argument - ignored.
* @param uPort Port number used for the IN operation.
* @param pu32 Where to store the result.
* @param cb Number of bytes read.
*/
PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
{
if (cb == 4)
{
return VINF_SUCCESS;
}
return VERR_IOM_IOPORT_UNUSED;
}
{
{
return 0;
}
{
{
if (pBridgeDevice)
{
pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc, pAddr->iRegister, val, len);
}
#else
return VINF_IOM_HC_IOPORT_WRITE;
#endif
}
}
else
{
{
#ifdef IN_RING3
Log(("ich9pciConfigWrite: %s: addr=%02x val=%08x len=%d\n", aDev->name, pAddr->iRegister, val, len));
#else
return VINF_IOM_HC_IOPORT_WRITE;
#endif
}
}
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
return VINF_SUCCESS;
/* Compute destination device */
}
/**
* Port I/O Handler for PCI data OUT operations.
*
* @returns VBox status code.
*
* @param pDevIns The device instance.
* @param pvUser User argument - ignored.
* @param uPort Port number used for the OUT operation.
* @param u32 The value to output.
* @param cb The value size in bytes.
*/
PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
{
int rc = VINF_SUCCESS;
{
}
else
return rc;
}
{
{
*pu32 = 0;
return 0;
}
{
{
if (pBridgeDevice)
{
*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, len);
}
#else
return VINF_IOM_HC_IOPORT_READ;
#endif
}
}
else
{
{
#ifdef IN_RING3
Log(("ich9pciConfigRead: %s: addr=%02x val=%08x len=%d\n", aDev->name, pPciAddr->iRegister, *pu32, len));
#else
return VINF_IOM_HC_IOPORT_READ;
#endif
}
}
return VINF_SUCCESS;
}
{
*pu32 = 0xffffffff;
return VINF_SUCCESS;
return VINF_SUCCESS;
/* Compute destination device */
}
/**
* Port I/O Handler for PCI data IN operations.
*
* @returns VBox status code.
*
* @param pDevIns The device instance.
* @param pvUser User argument - ignored.
* @param uPort Port number used for the IN operation.
* @param pu32 Where to store the result.
* @param cb Number of bytes read.
*/
PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
{
{
return rc;
}
return VERR_IOM_IOPORT_UNUSED;
}
/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
{
}
/* Add one more level up request on APIC input line */
{
}
/* Remove one level up request on APIC input line */
{
}
static void ich9pciApicSetIrq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int iForcedIrq)
{
/* This is only allowed to be called with a pointer to the root bus. */
if (iForcedIrq == -1)
{
int apic_irq, apic_level;
Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
{
/**
* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
* PDM_IRQ_LEVEL_HIGH bit set
*/
Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
}
} else {
Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
}
}
static void ich9pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
{
if (MSIIsEnabled(pPciDev))
{
return;
}
/* Check if the state changed. */
{
/* Send interrupt to I/O APIC only now. */
if (fIsAcpiDevice)
/*
* ACPI needs special treatment since SCI is hardwired and
* should not be affected by PCI IRQ routing tables at the
* same time SCI IRQ is shared in PCI sense hence this
* kludge (i.e. we fetch the hardwired value from ACPIs
* PCI device configuration space).
*/
else
}
}
PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
{
switch (cb)
{
case 1:
break;
case 2:
break;
case 4:
break;
default:
Assert(false);
break;
}
return rc;
}
PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
{
if (rc == VINF_SUCCESS)
{
switch (cb)
{
case 1:
break;
case 2:
break;
case 4:
break;
default:
Assert(false);
break;
}
}
return rc;
}
#ifdef IN_RING3
{
/* Search for a fitting bridge. */
{
/*
* Examine secondary and subordinate bus number.
* If the target bus is in the range we pass the request on to the bridge.
*/
("Device is not a PCI bridge but on the list of PCI bridges\n"));
return pBridgeTemp;
}
/* Nothing found. */
return NULL;
}
{
return (iRegion == PCI_ROM_SLOT) ?
}
#define INVALID_PCI_ADDRESS ~0U
{
{
int rc;
if (iRegionSize == 0)
continue;
{
/* port IO region */
if (iCmd & PCI_COMMAND_IOACCESS)
{
/* IO access allowed */
/* only 64K ioports on PC */
} else
}
else
{
/* MMIO region */
if (iCmd & PCI_COMMAND_MEMACCESS)
{
/* the ROM slot has a specific enable bit */
else
{
/* NOTE: we do not support wrapping */
/* XXX: as we cannot support really dynamic
mappings, we handle specific values as invalid
mappings. */
}
} else
}
/* now do the real mapping */
{
{
{
/* Port IO */
int devclass;
/* NOTE: specific hack for IDE in PC case:
only one byte must be mapped. */
/// @todo: do we need it?
{
}
else
{
}
}
else
{
{
/* unmap it. */
rc = pRegion->map_func(pDev, iRegion, NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
}
else
AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, pDev->name, iRegion, GCPhysBase, pRegion->size));
}
}
{
/* finally, map the region */
}
}
}
}
static DECLCALLBACK(int) ich9pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
{
/*
* Check input.
*/
if ( !pszName
|| !pPciDev
)
{
return VERR_INVALID_PARAMETER;
}
/*
* Register the device.
*/
}
static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg)
{
}
static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
{
/*
* Check input.
*/
if ( !pszName
|| !pPciDev
{
return VERR_INVALID_PARAMETER;
}
/*
* Register the device.
*/
}
static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
{
/*
* Validate.
*/
|| enmType == PCI_ADDRESS_SPACE_IO
("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
AssertMsgReturn( iLastSet != 0
/*
* Register the I/O region.
*/
/* Set type in the config space. */
return VINF_SUCCESS;
}
static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
{
if (ppfnReadOld)
if (ppfnWriteOld)
}
/**
* Saves a state of the PCI device.
*
* @returns VBox status code.
* @param pDevIns Device instance of the PCI Bus.
* @param pPciDev Pointer to PCI device.
* @param pSSM The handle to save the state to.
*/
static DECLCALLBACK(int) ich9pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
{
}
{
/*
* Iterate thru all the devices.
*/
{
if (pDev)
{
/* Device position */
SSMR3PutU32(pSSM, i);
/* PCI config registers */
/* IRQ pin state */
if (RT_FAILURE(rc))
return rc;
}
}
}
{
}
{
}
static void ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
{
LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
/* If the current bus is not the target bus search for the bus which contains the device. */
{
if (pBridgeDevice)
{
pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
}
}
else
{
/* This is the target bus, pass the write to the device. */
if (pPciDev)
{
Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
}
}
}
static uint32_t ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
{
LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
/* If the current bus is not the target bus search for the bus which contains the device. */
{
if (pBridgeDevice)
{
u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
}
}
else
{
/* This is the target bus, pass the read to the device. */
if (pPciDev)
{
Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
}
}
return u32Value;
}
/**
* Common routine for restoring the config registers of a PCI device.
*
* @param pDev The PCI device.
* @param pbSrcConfig The configuration register values to be loaded.
* @param fIsBridge Whether this is a bridge device or not.
*/
{
/*
* This table defines the fields for normal devices and bridge devices, and
* the order in which they need to be restored.
*/
static const struct PciField
{
const char *pszName;
} s_aFields[] =
{
/* off,cb,fW,fB, pszName */
/* The COMMAND register must come last as it requires the *ADDRESS*
registers to be restored before we pretent to change it from 0 to
whatever value the guest assigned it. */
};
#ifdef RT_STRICT
/* Check that we've got full register coverage. */
{
while (cb-- > 0)
{
off++;
}
}
{
}
#endif
/*
* Loop thru the fields covering the 64 bytes of standard registers.
*/
{
switch (cb)
{
case 1:
break;
case 2:
break;
case 4:
break;
default:
AssertFailed();
continue;
}
|| off == VBOX_PCI_COMMAND)
{
{
LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
else
LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
}
if (off == VBOX_PCI_COMMAND)
}
}
/*
* The device dependent registers.
*
* We will not use ConfigWrite here as we have no clue about the size
* of the registers, so the device is responsible for correctly
* restoring functionality governed by these registers.
*/
{
LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
}
}
/**
* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
*
* @returns VBox status code.
* @param pBus The bus which data is being loaded.
* @param pSSM The saved state handle.
* @param uVersion The data version.
* @param uPass The pass.
*/
static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
{
uint32_t i;
int rc;
/*
* Iterate thru all the devices and write 0 to the COMMAND register so
* that all the memory is unmapped before we start restoring the saved
* mapping locations.
*
* The register value is restored afterwards so we can do proper
* LogRels in pciR3CommonRestoreConfig.
*/
{
if (pDev)
{
}
}
/*
* Iterate all the devices.
*/
for (i = 0;; i++)
{
/* index / terminator */
if (RT_FAILURE(rc))
return rc;
break;
|| u32 < i)
{
return rc;
}
/* skip forward to the device checking that no new devices are present. */
for (; i < u32; i++)
{
if (pDev)
{
return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
}
}
/* get the data */
DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
if (RT_FAILURE(rc))
return rc;
/* check that it's still around. */
if (!pDev)
{
LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
continue;
}
/* match the vendor id assuming that this will never be changed. */
return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
/* commit the loaded device config. */
}
return VINF_SUCCESS;
}
/**
* Loads a saved PCI device state.
*
* @returns VBox status code.
* @param pDevIns Device instance of the PCI Bus.
* @param pPciDev Pointer to PCI device.
* @param pSSM The handle to the saved state.
*/
static DECLCALLBACK(int) ich9pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
{
}
static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
{
}
static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
{
}
static uint32_t ich9pciConfigRead(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
{
/* Set destination address */
/// @todo: device locking?
switch (len)
{
case 1:
u32Val &= 0xff;
break;
case 2:
u32Val &= 0xffff;
break;
}
return u32Val;
}
static void ich9pciConfigWrite(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
{
/* Set destination address */
/// @todo: device locking?
}
static void ich9pciSetRegionAddress(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint32_t addr)
{
/* Read memory type first. */
/* Read command register. */
if ( iRegion == PCI_ROM_SLOT )
else /* The region is MMIO. */
/* Write address of the device. */
/* enable memory mappings */
}
static void ich9pciBiosInitBridge(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
{
/* Temporary until we know how many other bridges are behind this one. */
/* Add position of this bridge into the array. */
/*
* The I/O range for the bridge must be aligned to a 4KB boundary.
* This does not change anything really as the access to the device is not going
* through the bridge but we want to be compliant to the spec.
*/
{
}
ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
{
}
ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
/* Save values to compare later to. */
/* Init devices behind the bridge and possibly other bridges as well. */
/* The number of bridges behind the this one is now available. */
/*
* Set I/O limit register. If there is no device with I/O space behind the bridge
* we set a lower value than in the base register.
* The result with a real bridge is that no I/O transactions are passed to the secondary
* interface. Again this doesn't really matter here but we want to be compliant to the spec.
*/
{
/* The upper boundary must be one byte less than a 4KB boundary. */
}
ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
/* Same with the MMIO limit register but with 1MB boundary here. */
if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
{
/* The upper boundary must be one byte less than a 1MB boundary. */
}
ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
/*
* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
* which may be behind a bridge. Thatswhy it is unconditionally disabled here atm by writing a higher value into
* the base register than in the limit register.
*/
}
static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
{
/* If device is present */
if (uVendor == 0xffff)
return;
switch (uDevClass)
{
case 0x0101:
/* IDE controller */
goto default_map;
break;
case 0x0300:
/* VGA controller */
if (uVendor != 0x80ee)
goto default_map;
/* VGA: map frame buffer to default Bochs VBE address */
/*
* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
* only the framebuffer (i.e., a memory region) is explicitly registered via
* ich9pciSetRegionAddress, so I/O decoding must be enabled manually.
*/
/* Enable I/O space access. */
1);
break;
case 0x0800:
/* PIC */
if (uVendor == 0x1014)
{
/* IBM */
/* MPIC & MPIC2 */
}
break;
case 0xff00:
if ((uVendor == 0x0106b)
{
/* macio bridge */
}
break;
case 0x0604:
/* PCI-to-PCI bridge. */
break;
default:
{
/* default memory mappings */
/*
* We ignore ROM region here.
*/
{
/* Calculate size. */
/* Clear resource information depending on resource type. */
u32Size &= ~(0x01);
else /* MMIO */
u32Size &= ~(0x0f);
/*
* Invert all bits and add 1 to get size of the region.
* (From PCI implementation note)
*/
else
Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, iRegion, uDevFn, uBus, u32Size));
if (u32Size)
{
Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, (fIsPio ? "I/O" : "MMIO"), iRegion, *paddr));
}
}
break;
}
}
/* map the interrupt */
if (uPin != 0)
{
uPin--;
/* We need to go up to the host bus to see which irq this device will assert there. */
while (cBridgeDepth != 0)
{
/* Get the pin the device would assert on the bridge. */
cBridgeDepth--;
}
#if 0
#endif
}
}
{
unsigned i;
/*
* Set the start addresses.
*/
/*
* Activate IRQ mappings.
*/
for (i = 0; i < 4; i++)
{
/* Set to trigger level. */
}
/* Tell to the PIC. */
if (rcStrict == VINF_SUCCESS)
if (rcStrict != VINF_SUCCESS)
{
}
/*
* Init the devices.
*/
for (i = 0; i < 256; i++)
{
Log2(("PCI: Initializing device %d (%#x)\n",
i, 0x80000000 | (i << 8)));
}
return VINF_SUCCESS;
}
{
{
AssertMsgReturn(false, ("Read from extended registers falled back to generic code\n"), 0);
}
if ( PCIIsMsiCapable(aDev)
)
{
}
0);
switch (len)
{
case 1:
case 2:
default:
case 4:
}
}
/**
* See paragraph 7.5 of PCI Express specification (p. 349) for definition of
* registers and their writability policy.
*/
{
{
AssertMsgReturnVoid(false, ("Write to extended registers falled back to generic code\n"));
}
if ( PCIIsMsiCapable(aDev)
)
{
return;
}
/* Fast case - update one of BARs or ROM address, 'while' only for 'break' */
while ( len == 4
&& ( ( u32Address >= VBOX_PCI_BASE_ADDRESS_0
|| ( u32Address >= VBOX_PCI_ROM_ADDRESS
)
)
{
int reg, regionSize;
reg = (u32Address >= VBOX_PCI_ROM_ADDRESS) ? PCI_ROM_SLOT : (u32Address - VBOX_PCI_BASE_ADDRESS_0) >> 2;
if (regionSize == 0)
break;
/* compute the stored value */
if (reg == PCI_ROM_SLOT) {
/* keep ROM enable bit */
} else {
}
return;
}
bool fUpdateMappings = false;
{
bool fWritable = false;
switch (PCIDevGetHeaderType(aDev))
{
case 0x00: /* normal device */
case 0x80: /* multi-function device */
switch (addr)
{
/* Read-only registers */
case VBOX_PCI_REVISION_ID:
case VBOX_PCI_CLASS_PROG:
case VBOX_PCI_CLASS_SUB:
case VBOX_PCI_CLASS_BASE:
case VBOX_PCI_HEADER_TYPE:
case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
case VBOX_PCI_CAPABILITY_LIST:
case VBOX_PCI_INTERRUPT_PIN:
fWritable = false;
break;
/* Others can be written */
default:
fWritable = true;
break;
}
break;
default:
case 0x01: /* bridge */
switch (addr)
{
/* Read-only registers */
case VBOX_PCI_REVISION_ID:
case VBOX_PCI_CLASS_PROG:
case VBOX_PCI_CLASS_SUB:
case VBOX_PCI_CLASS_BASE:
case VBOX_PCI_HEADER_TYPE:
case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
case VBOX_PCI_INTERRUPT_PIN:
fWritable = false;
break;
default:
fWritable = true;
break;
}
break;
}
switch (addr)
{
case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
fUpdateMappings = true;
break;
/* don't change reserved bits (11-15) */
fUpdateMappings = true;
break;
case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
/* don't change read-only bits => actually all lower bits are read-only */
/* status register, low part: clear bits by writing a '1' to the corresponding bit */
break;
/* don't change read-only bits */
/* status register, high part: clear bits by writing a '1' to the corresponding bit */
break;
default:
if (fWritable)
}
addr++;
val >>= 8;
}
if (fUpdateMappings)
/* if the command register is modified, we must modify the mappings */
}
static const struct {
const char* pszName;
} PciSlotAssignments[] = {
{
"piix3ide", 1, 1 // do we really need it?
},
{
"lan", 25, 0 /* LAN controller */
},
{
"hda", 27, 0 /* High Definition Audio */
},
{
"i82801", 30, 0 /* Host Controller */
},
{
"lpc", 31, 0 /* Low Pin Count bus */
},
{
"ahci", 31, 2 /* SATA controller */
},
{
"smbus", 31, 3 /* System Management Bus */
},
{
"thermal", 31, 6 /* Thermal controller */
},
};
{
{
{
}
}
/* Otherwise when assigning a slot, we need to make sure all its functions are available */
{
return iPos;
}
return -1;
}
{
;
}
{
/*
* Find device position
*/
if (iDev < 0)
{
if (iDev < 0)
{
AssertMsgFailed(("Couldn't find free spot!\n"));
return VERR_PDM_TOO_PCI_MANY_DEVICES;
}
}
/*
* Check if we can really take this slot, possibly by relocating
* its current habitant, if it wasn't hard assigned too.
*/
if (PCIIsRequestedDevfunc(pPciDev) &&
{
/*
* Smth like hasHardAssignedDevsInSlot(pBus, iDev >> 3) shall be use to make
* it compatible with DevPCI.cpp version, but this way we cannot assign
* in accordance with the chipset spec.
*/
AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
return VERR_INTERNAL_ERROR;
}
{
/* if we got here, we shall (and usually can) relocate the device */
{
AssertMsgFailed(("Couldn't find free spot!\n"));
return VERR_PDM_TOO_PCI_MANY_DEVICES;
}
/* Copy device function by function to its new position */
for (int i = 0; i < 8; i++)
{
continue;
Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->apDevices[iDev + i]->name, iDev + i, iRelDev + i));
}
}
/*
* Fill in device information.
*/
if (PCIIsPci2PciBridge(pPciDev))
{
AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
}
Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
return VINF_SUCCESS;
}
/**
* Info handler, device version.
*
* @param pDevIns Device instance which registered the info.
* @param pHlp Callback functions for doing output.
* @param pszArgs Argument string. Optional and specific to the handler.
*/
{
{
);
}
}
int iInstance,
{
int rc;
/*
* Validate and read configuration.
*/
if (!CFGMR3AreValuesValid(pCfg,
"IOAPIC\0"
"GCEnabled\0"
"R0Enabled\0"
"McfgBase\0"
"McfgLength\0"
))
/* query whether we got an IOAPIC */
bool fUseIoApic;
if (RT_FAILURE(rc))
N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
/* check if RC code is enabled. */
bool fGCEnabled;
if (RT_FAILURE(rc))
N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
/* check if R0 code is enabled. */
bool fR0Enabled;
if (RT_FAILURE(rc))
N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
/*
* Init data.
*/
/* Zero out everything */
/* And fill values */
if (!fUseIoApic)
N_("Must use IO-APIC with ICH9 chipset"));
if (RT_FAILURE(rc))
N_("Configuration error: Failed to read \"McfgBase\""));
if (RT_FAILURE(rc))
N_("Configuration error: Failed to read \"McfgLength\""));
pGlobals->aPciBus.papBridgesR3 = (PPCIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) * RT_ELEMENTS(pGlobals->aPciBus.apDevices));
/*
* Register bus
*/
if (RT_FAILURE(rc))
N_("Failed to register ourselves as a PCI Bus"));
N_("PCI helper version mismatch; got %#x expected %#x"),
/*
* Fill in PCI configs and add them to the bus.
*/
/**
* We emulate 82801IB ICH9 IO chip used in Q35,
*
* Stepping S-Spec Top Marking
*
* A2 SLA9M NH82801IB
*/
/* We register Host<->PCI controller on the bus */
/*
* Register I/O ports and save state.
*/
rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
if (RT_FAILURE(rc))
return rc;
rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
if (RT_FAILURE(rc))
return rc;
if (fGCEnabled)
{
rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
if (RT_FAILURE(rc))
return rc;
rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
if (RT_FAILURE(rc))
return rc;
}
if (fR0Enabled)
{
rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
if (RT_FAILURE(rc))
return rc;
rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
if (RT_FAILURE(rc))
return rc;
}
if (pGlobals->u64PciConfigMMioAddress != 0)
{
rc = PDMDevHlpMMIORegister(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength, pGlobals,
if (RT_FAILURE(rc))
{
return rc;
}
if (fGCEnabled)
{
0,
"ich9pciMcfgMMIOWrite",
"ich9pciMcfgMMIORead",
NULL);
if (RT_FAILURE(rc))
{
return rc;
}
}
if (fR0Enabled)
{
0,
"ich9pciMcfgMMIOWrite",
"ich9pciMcfgMMIORead",
NULL);
if (RT_FAILURE(rc))
{
return rc;
}
}
}
/** @todo: other chipset devices shall be registered too */
/** @todo: what to with bridges? */
return VINF_SUCCESS;
}
/**
* @copydoc FNPDMDEVRELOCATE
*/
{
/* Relocate RC pointers for the attached pci devices. */
{
}
}
/**
* @interface_method_impl{PDMDEVREG,pfnConstruct}
*/
int iInstance,
{
int rc;
/*
* Validate and read configuration.
*/
/* check if RC code is enabled. */
bool fGCEnabled;
if (RT_FAILURE(rc))
N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
/* check if R0 code is enabled. */
bool fR0Enabled;
if (RT_FAILURE(rc))
N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
/*
* Init data and register the PCI bus.
*/
pBus->papBridgesR3 = (PPCIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) * RT_ELEMENTS(pBus->apDevices));
if (RT_FAILURE(rc))
N_("Failed to register ourselves as a PCI Bus"));
N_("PCI helper version mismatch; got %#x expected %#x"),
/*
* Fill in PCI configs and add them to the bus.
*/
PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
/*
* This device does not generate interrupts. Interrupt delivery from
* devices attached to the bus is unaffected.
*/
/* Bridge-specific data */
/*
* Register this PCI bridge. The called function will take care on which bus we will get registered.
*/
if (RT_FAILURE(rc))
return rc;
/*
* The iBus property doesn't really represent the bus number
* because the guest and the BIOS can choose different bus numbers
* for them.
* The bus number is mainly for the setIrq function to indicate
* when the host bus is reached which will have iBus = 0.
* Thathswhy the + 1.
*/
/*
* Register SSM handlers. We use the same saved state version as for the host bridge
* to make changes easier.
*/
rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION, sizeof(*pBus) + 16*128, "pgm",
if (RT_FAILURE(rc))
return rc;
return VINF_SUCCESS;
}
/**
* @copydoc FNPDMDEVRESET
*/
{
/* Reset config space to default values. */
}
/**
* @copydoc FNPDMDEVRELOCATE
*/
{
/* Relocate RC pointers for the attached pci devices. */
{
}
}
/**
* The PCI bus device registration structure.
*/
const PDMDEVREG g_DevicePciIch9 =
{
/* u32Version */
/* szName */
"ich9pci",
/* szRCMod */
"VBoxDDGC.gc",
/* szR0Mod */
"VBoxDDR0.r0",
/* pszDescription */
"ICH9 PCI bridge",
/* fFlags */
/* fClass */
/* cMaxInstances */
1,
/* cbInstance */
sizeof(PCIGLOBALS),
/* pfnConstruct */
/* pfnDestruct */
NULL,
/* pfnRelocate */
/* pfnIOCtl */
NULL,
/* pfnPowerOn */
NULL,
/* pfnReset */
NULL,
/* pfnSuspend */
NULL,
/* pfnResume */
NULL,
/* pfnAttach */
NULL,
/* pfnDetach */
NULL,
/* pfnQueryInterface */
NULL,
/* pfnInitComplete */
NULL,
/* pfnPowerOff */
NULL,
/* pfnSoftReset */
NULL,
/* u32VersionEnd */
};
/**
* The device registration structure
* for the PCI-to-PCI bridge.
*/
const PDMDEVREG g_DevicePciIch9Bridge =
{
/* u32Version */
/* szName */
"ich9pcibridge",
/* szRCMod */
"VBoxDDGC.gc",
/* szR0Mod */
"VBoxDDR0.r0",
/* pszDescription */
"ICH9 PCI to PCI bridge",
/* fFlags */
/* fClass */
/* cMaxInstances */
~0,
/* cbInstance */
sizeof(PCIBUS),
/* pfnConstruct */
/* pfnDestruct */
NULL,
/* pfnRelocate */
/* pfnIOCtl */
NULL,
/* pfnPowerOn */
NULL,
/* pfnReset */
/* pfnSuspend */
NULL,
/* pfnResume */
NULL,
/* pfnAttach */
NULL,
/* pfnDetach */
NULL,
/* pfnQueryInterface */
NULL,
/* pfnInitComplete */
NULL,
/* pfnPowerOff */
NULL,
/* pfnSoftReset */
NULL,
/* u32VersionEnd */
};
#endif /* IN_RING3 */
#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */