DevPCI-new.cpp revision 728e645c59f8e1a91e241a104872626109a5a231
/* $Id$ */
/** @file
* DevPCI - PCI BUS Device.
*/
/*
* Copyright (C) 2010 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* you can redistribute it and/or modify it under the terms of the GNU
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_DEV_PCI
/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
#define PCI_INCLUDE_PRIVATE
#include <VBox/pci.h>
#include <VBox/pdmdev.h>
#include <iprt/asm.h>
#include <iprt/assert.h>
#include <iprt/string.h>
#include "../Builtins.h"
/**
* PCI Bus instance.
*/
typedef struct
{
/** Bus number. */
int32_t iBus;
/** Number of bridges attached to the bus. */
uint32_t cBridges;
/** Array of PCI devices. */
R3PTRTYPE(PPCIDEVICE) devices[256];
/** Array of bridges attached to the bus. */
R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
/** R3 pointer to the device instance. */
PPDMDEVINSR3 pDevInsR3;
/** Pointer to the PCI R3 helpers. */
PCPDMPCIHLPR3 pPciHlpR3;
/** R0 pointer to the device instance. */
PPDMDEVINSR0 pDevInsR0;
/** Pointer to the PCI R0 helpers. */
PCPDMPCIHLPR0 pPciHlpR0;
/** RC pointer to the device instance. */
PPDMDEVINSRC pDevInsRC;
/** Pointer to the PCI RC helpers. */
PCPDMPCIHLPRC pPciHlpRC;
/** The PCI device for the PCI bridge. */
PCIDEVICE PciDev;
} PCIBUS, *PPCIBUS;
/**
* PIIX3 ISA Bridge state.
*/
typedef struct
{
/** The PCI device of the bridge. */
PCIDEVICE dev;
} PIIX3, *PPIIX3;
/** @def PCI_IRQ_PINS
* Number of pins for interrupts (PIRQ#0...PIRQ#3)
*/
#define PCI_IRQ_PINS 4
/** @def PCI_APIC_IRQ_PINS
* Number of pins for interrupts if the APIC is used.
*/
#define PCI_APIC_IRQ_PINS 8
/**
* PCI Globals - This is the host-to-pci bridge and the root bus.
*/
typedef struct PCIGLOBALS
{
/** I/O APIC usage flag */
bool fUseIoApic;
/** R3 pointer to the device instance. */
PPDMDEVINSR3 pDevInsR3;
/** R0 pointer to the device instance. */
PPDMDEVINSR0 pDevInsR0;
/** RC pointer to the device instance. */
PPDMDEVINSRC pDevInsRC;
#if HC_ARCH_BITS == 64
uint32_t Alignment0;
#endif
/** ISA bridge state. */
PIIX3 PIIX3State;
/** PCI bus which is attached to the host-to-PCI bridge. */
PCIBUS PciBus;
} PCIGLOBALS;
/** Pointer to per VM data. */
typedef PCIGLOBALS *PPCIGLOBALS;
/*******************************************************************************
* Defined Constants And Macros *
*******************************************************************************/
/** Converts a bus instance pointer to a device instance pointer. */
#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
/** Converts a device instance pointer to a PCIGLOBALS pointer. */
#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
/** Converts a device instance pointer to a PCIBUS pointer. */
#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->PciBus))
#ifndef VBOX_DEVICE_STRUCT_TESTCASE
#ifdef IN_RING3
static DECLCALLBACK(int) pciConstruct(PPDMDEVINS pDevIns,
int iInstance,
PCFGMNODE pCfg)
{
int rc;
Assert(iInstance == 0);
/*
* Validate and read configuration.
*/
if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
/* query whether we got an IOAPIC */
bool fUseIoApic;
rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc,
N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
/* check if RC code is enabled. */
bool fGCEnabled;
rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc,
N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
/* check if R0 code is enabled. */
bool fR0Enabled;
rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc,
N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
/*
* Init data and register the PCI bus.
*/
PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
pGlobals->fUseIoApic = fUseIoApic;
return VINF_SUCCESS;
}
/**
* @copydoc FNPDMDEVRELOCATE
*/
static DECLCALLBACK(void) pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
{
}
/**
* @interface_method_impl{PDMDEVREG,pfnConstruct}
*/
static DECLCALLBACK(int) pcibridgeConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
{
int rc;
/*
* Validate and read configuration.
*/
if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
/* check if RC code is enabled. */
bool fGCEnabled;
rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc,
N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
/* check if R0 code is enabled. */
bool fR0Enabled;
rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc,
N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
return VINF_SUCCESS;
}
/**
* @copydoc FNPDMDEVRESET
*/
static DECLCALLBACK(void) pcibridgeReset(PPDMDEVINS pDevIns)
{
}
/**
* @copydoc FNPDMDEVRELOCATE
*/
static DECLCALLBACK(void) pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
{
}
/**
* The PCI bus device registration structure.
*/
const PDMDEVREG g_DevicePCI =
{
/* u32Version */
PDM_DEVREG_VERSION,
/* szName */
"pci",
/* szRCMod */
"VBoxDDGC.gc",
/* szR0Mod */
"VBoxDDR0.r0",
/* pszDescription */
"i440FX PCI bridge and PIIX3 ISA bridge.",
/* fFlags */
PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
/* fClass */
PDM_DEVREG_CLASS_BUS_PCI | PDM_DEVREG_CLASS_BUS_ISA,
/* cMaxInstances */
1,
/* cbInstance */
sizeof(PCIGLOBALS),
/* pfnConstruct */
pciConstruct,
/* pfnDestruct */
NULL,
/* pfnRelocate */
pciRelocate,
/* pfnIOCtl */
NULL,
/* pfnPowerOn */
NULL,
/* pfnReset */
NULL,
/* pfnSuspend */
NULL,
/* pfnResume */
NULL,
/* pfnAttach */
NULL,
/* pfnDetach */
NULL,
/* pfnQueryInterface */
NULL,
/* pfnInitComplete */
NULL,
/* pfnPowerOff */
NULL,
/* pfnSoftReset */
NULL,
/* u32VersionEnd */
PDM_DEVREG_VERSION
};
/**
* The device registration structure
* for the PCI-to-PCI bridge.
*/
const PDMDEVREG g_DevicePCIBridge =
{
/* u32Version */
PDM_DEVREG_VERSION,
/* szName */
"pcibridge",
/* szRCMod */
"VBoxDDGC.gc",
/* szR0Mod */
"VBoxDDR0.r0",
/* pszDescription */
"82801 Mobile PCI to PCI bridge",
/* fFlags */
PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
/* fClass */
PDM_DEVREG_CLASS_BUS_PCI,
/* cMaxInstances */
~0,
/* cbInstance */
sizeof(PCIBUS),
/* pfnConstruct */
pcibridgeConstruct,
/* pfnDestruct */
NULL,
/* pfnRelocate */
pcibridgeRelocate,
/* pfnIOCtl */
NULL,
/* pfnPowerOn */
NULL,
/* pfnReset */
pcibridgeReset,
/* pfnSuspend */
NULL,
/* pfnResume */
NULL,
/* pfnAttach */
NULL,
/* pfnDetach */
NULL,
/* pfnQueryInterface */
NULL,
/* pfnInitComplete */
NULL,
/* pfnPowerOff */
NULL,
/* pfnSoftReset */
NULL,
/* u32VersionEnd */
PDM_DEVREG_VERSION
};
#endif /* IN_RING3 */
#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */