DevIchIntelHDA.cpp revision b983e853ab932523e352309e70047689a7540823
/* $Id$ */
/** @file
* DevIchIntelHD - VBox ICH Intel HD Audio Controller.
*/
/*
* Copyright (C) 2006-2012 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_DEV_AUDIO
#include <iprt/asm-math.h>
#include "VBoxDD.h"
extern "C" {
#include "audio.h"
}
#include "DevCodec.h"
#define VBOX_WITH_INTEL_HDA
#if defined(VBOX_WITH_HP_HDA)
/* HP Pavilion dv4t-1300 */
# define HDA_PCI_VENDOR_ID 0x103c
# define HDA_PCI_DEICE_ID 0x30f7
#elif defined(VBOX_WITH_INTEL_HDA)
/* Intel HDA controller */
# define HDA_PCI_VENDOR_ID 0x8086
# define HDA_PCI_DEICE_ID 0x2668
#elif defined(VBOX_WITH_NVIDIA_HDA)
/* nVidia HDA controller */
# define HDA_PCI_VENDOR_ID 0x10de
# define HDA_PCI_DEICE_ID 0x0ac0
#else
#endif
PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb);
#define HDA_NREGS 112
/* Registers */
#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
* oss (15:12) - number of output streams supported
* iss (11:8) - number of input streams supported
* bss (7:3) - number of bidirectional streams supported
* bds (2:1) - number of serial data out signals supported
* b64sup (0) - 64 bit addressing supported.
*/
| ((b64sup) & 1))
#define ICH6_HDA_REG_GCTL (5)
#define ICH6_HDA_GCTL_RST_SHIFT (0)
#define ICH6_HDA_GCTL_FSH_SHIFT (1)
#define ICH6_HDA_GCTL_UR_SHIFT (8)
#define ICH6_HDA_STATES_SCSF 0x7
#define ICH6_HDA_GSTS_FSH_SHIFT (1)
#define ICH6_HDA_INTCTL_GIE_SHIFT 31
#define ICH6_HDA_INTCTL_CIE_SHIFT 30
#define ICH6_HDA_INTCTL_S0_SHIFT (0)
#define ICH6_HDA_INTCTL_S1_SHIFT (1)
#define ICH6_HDA_INTCTL_S2_SHIFT (2)
#define ICH6_HDA_INTCTL_S3_SHIFT (3)
#define ICH6_HDA_INTCTL_S4_SHIFT (4)
#define ICH6_HDA_INTCTL_S5_SHIFT (5)
#define ICH6_HDA_INTCTL_S6_SHIFT (6)
#define ICH6_HDA_INTCTL_S7_SHIFT (7)
/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
* the datasheet.
*/
#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
#define ICH6_HDA_INTSTS_S0_SHIFT (0)
#define ICH6_HDA_INTSTS_S1_SHIFT (1)
#define ICH6_HDA_INTSTS_S2_SHIFT (2)
#define ICH6_HDA_INTSTS_S3_SHIFT (3)
#define ICH6_HDA_INTSTS_S4_SHIFT (4)
#define ICH6_HDA_INTSTS_S5_SHIFT (5)
#define ICH6_HDA_INTSTS_S6_SHIFT (6)
#define ICH6_HDA_INTSTS_S7_SHIFT (7)
#define ICH6_HDA_CORBRP_RST_SHIFT 15
#define ICH6_HDA_CORBRP_WP_SHIFT 0
#define ICH6_HDA_CORBRP_WP_MASK 0xFF
#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
#define ICH6_HDA_CORBSIZE_SZ 0x3
/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
#define ICH6_HDA_ROI_DMA_SHIFT (2)
#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
#define ICH6_HDA_RIRBSIZE_SZ 0x3
#define ICH6_HDA_IRS_ICB_SHIFT (0)
#define ICH6_HDA_IRS_IRV_SHIFT (1)
#define DPBASE_ENABLED 1
#define DPBASE_ADDR_MASK (~0x7f)
/* Note: sdnum here _MUST_ be stream reg number [0,7] */
#define HDA_STREAM_REG2(pState, name, sdnum) (HDA_REG_IND((pState), ICH6_HDA_REG_SD0##name + (sdnum) * 10))
#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
#define ICH6_HDA_SDCTL_DIR_SHIFT (19)
#define ICH6_HDA_SDCTL_TP_SHIFT (18)
#define ICH6_HDA_SDCTL_STRIPE_MASK (0x3)
#define ICH6_HDA_SDCTL_STRIPE_SHIFT (16)
#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
#define ICH6_HDA_SDSTS_DE_SHIFT (4)
#define ICH6_HDA_SDSTS_FE_SHIFT (3)
#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
/*
* ICH6 datasheet defined limits for FIFOW values (18.2.38)
*/
#define HDA_SDFIFOW_8B (0x2)
#define HDA_SDFIFOW_16B (0x3)
#define HDA_SDFIFOW_32B (0x4)
/*
* ICH6 datasheet defines limits for FIFOS registers (18.2.39)
* formula: size - 1
* Other values not listed are not supported.
*/
#define ICH6_HDA_SDFMT_BASE_RATE_SHIFT (14)
#define ICH6_HDA_SDFMT_MULT_SHIFT (11)
#define ICH6_HDA_SDFMT_MULT_MASK (0x7)
#define ICH6_HDA_SDFMT_DIV_SHIFT (8)
#define ICH6_HDA_SDFMT_DIV_MASK (0x7)
#define ICH6_HDA_SDFMT_BITS_SHIFT (4)
#define ICH6_HDA_SDFMT_BITS_MASK (0x7)
#define SDFMT_BASE_RATE(pState, num) ((SDFMT(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
#define SDFMT_MULT(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
#define SDFMT_DIV(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
typedef struct HDABDLEDESC
{
bool fBdleCviIoc;
} HDABDLEDESC, *PHDABDLEDESC;
/** HDABDLEDESC field descriptors the v3+ saved state. */
static SSMFIELD const g_aHdaBDLEDescFields[] =
{
};
/** HDABDLEDESC field descriptors the v1 and v2 saved state. */
static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =
{
};
typedef struct HDASTREAMTRANSFERDESC
{
typedef struct INTELHDLinkState
{
/** Pointer to the device instance. */
/** Pointer to the connector of the attached audio driver. */
/** Pointer to the attached audio driver. */
/** The base interface for LUN\#0. */
/* Interrupt on completion */
bool fCviIoc;
/* pointer to CORB buf */
/* size in bytes of CORB buf */
/* pointer on RIRB buf */
/* size in bytes of RIRB buf */
/* indicates if HDA in reset. */
bool fInReset;
typedef struct PCIINTELHDLinkState
{
/** @todo r=bird: Why aren't these static? And why use DECLCALLBACK for
* internal functions? */
DECLCALLBACK(int) hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
DECLCALLBACK(int) hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
DECLCALLBACK(int) hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
DECLCALLBACK(int) hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
DECLCALLBACK(int) hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
DECLCALLBACK(int) hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
DECLCALLBACK(int) hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
DECLCALLBACK(int) hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
DECLCALLBACK(int) hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
DECLCALLBACK(int) hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
DECLCALLBACK(int) hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
DECLCALLBACK(int) hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
DECLCALLBACK(int) hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
DECLCALLBACK(int) hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
DECLCALLBACK(int) hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
DECLCALLBACK(int) hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
DECLCALLBACK(int) hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
DECLCALLBACK(int) hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
DECLCALLBACK(int) hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
DECLCALLBACK(int) hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
DECLCALLBACK(int) hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
DECLCALLBACK(int) hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
DECLCALLBACK(int) hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
DECLCALLBACK(int) hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
DECLCALLBACK(int) hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
DECLCALLBACK(int) hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
DECLCALLBACK(int) hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
DECLCALLBACK(int) hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
DECLCALLBACK(int) hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
DECLCALLBACK(int) hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
DECLCALLBACK(int) hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
DECLCALLBACK(int) hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
DECLCALLBACK(int) hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
DECLCALLBACK(int) hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
DECLCALLBACK(int) hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
DECLCALLBACK(int) hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
DECLINLINE(void) hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc);
static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
#ifdef LOG_ENABLED
#endif
/* see 302349 p 6.2*/
const static struct stIchIntelHDRegMap
{
/** Register offset in the register space. */
/** Size in bytes. Registers of size > 4 are in fact tables. */
/** Readable bits. */
/** Writable bits. */
/** Read callback. */
/** Write callback. */
/** Abbreviated name. */
const char *abbrev;
/** Full name. */
const char *name;
{
/* offset size read mask write mask read callback write callback abbrev full name */
/*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
{ 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
{ 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
{ 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
{ 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
{ 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
{ 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
{ 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
{ 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
{ 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
{ 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
{ 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
{ 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
/// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
{ 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
{ 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
{ 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
{ 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
{ 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
{ 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
{ 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
{ 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
{ 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
{ 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
{ 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
{ 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
{ 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
{ 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
{ 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
{ 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
{ 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
{ 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
{ 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
{ 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
{ 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
{ 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
{ 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
{ 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
{ 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
{ 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD0FIFOW", "ISD0 FIFO Watermark" },
{ 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
{ 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD0FMT" , "ISD0 Format" },
{ 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
{ 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
{ 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
{ 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
{ 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
{ 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
{ 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
{ 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD1FIFOW", "ISD1 FIFO Watermark" },
{ 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
{ 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD1FMT" , "ISD1 Format" },
{ 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
{ 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
{ 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
{ 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
{ 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
{ 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
{ 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
{ 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD2FIFOW", "ISD2 FIFO Watermark" },
{ 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
{ 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD2FMT" , "ISD2 Format" },
{ 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
{ 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
{ 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
{ 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
{ 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
{ 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
{ 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
{ 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
{ 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
{ 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD3FMT" , "ISD3 Format" },
{ 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
{ 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
{ 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
{ 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
{ 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
{ 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
{ 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
{ 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD0FIFOW", "OSD0 FIFO Watermark" },
{ 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD0FIFOS", "OSD0 FIFO Size" },
{ 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD0FMT" , "OSD0 Format" },
{ 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
{ 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
{ 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
{ 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
{ 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
{ 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
{ 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
{ 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD1FIFOW", "OSD1 FIFO Watermark" },
{ 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD1FIFOS", "OSD1 FIFO Size" },
{ 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD1FMT" , "OSD1 Format" },
{ 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
{ 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
{ 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
{ 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
{ 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
{ 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
{ 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
{ 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD2FIFOW", "OSD2 FIFO Watermark" },
{ 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD2FIFOS", "OSD2 FIFO Size" },
{ 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD2FMT" , "OSD2 Format" },
{ 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
{ 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
{ 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
{ 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
{ 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
{ 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
{ 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
{ 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD3FIFOW", "OSD3 FIFO Watermark" },
{ 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD3FIFOS", "OSD3 FIFO Size" },
{ 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD3FMT" , "OSD3 Format" },
{ 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
{ 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
};
{
(pState->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm*8, pStreamDesc->pu32Lpib, sizeof(uint32_t));
}
{
#if 0
{
case HDA_SDFIFOW_8B: return 8;
case HDA_SDFIFOW_16B: return 16;
case HDA_SDFIFOW_32B: return 32;
default:
AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pState, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
}
#endif
return 0;
}
{
bool fIrq = false;
if ( INTCTL_CIE(pState)
&& ( RIRBSTS_RINTFL(pState)
fIrq = true;
if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 0)
fIrq = true;
if (INTCTL_GIE(pState))
{
}
return VINF_SUCCESS;
}
{
int idxMiddle;
int idxLow = 0;
/* Aliases HDA spec 3.3.45 */
switch(u32Offset)
{
case 0x2084:
return HDA_REG_IND_NAME(SD0LPIB);
case 0x20A4:
return HDA_REG_IND_NAME(SD1LPIB);
case 0x20C4:
return HDA_REG_IND_NAME(SD2LPIB);
case 0x20E4:
return HDA_REG_IND_NAME(SD3LPIB);
case 0x2104:
return HDA_REG_IND_NAME(SD4LPIB);
case 0x2124:
return HDA_REG_IND_NAME(SD5LPIB);
case 0x2144:
return HDA_REG_IND_NAME(SD6LPIB);
case 0x2164:
return HDA_REG_IND_NAME(SD7LPIB);
}
while (1)
{
#ifdef DEBUG_vvl
&& idxLow >= 0));
#endif
|| idxHigh < 0)
break;
{
continue;
}
{
continue;
}
return idxMiddle;
}
return -1;
}
{
int rc = VINF_SUCCESS;
if (fLocal)
{
rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
if (RT_FAILURE(rc))
#ifdef DEBUG_CMD_BUFFER
uint8_t i = 0;
do
{
Log(("hda: corb%02x: ", i));
uint8_t j = 0;
do
{
const char *prefix;
prefix = "[R]";
prefix = "[W]";
else
j++;
} while (j < 8);
Log(("\n"));
i += 8;
} while(i != 0);
#endif
}
else
{
rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
if (RT_FAILURE(rc))
#ifdef DEBUG_CMD_BUFFER
uint8_t i = 0;
do {
Log(("hda: rirb%02x: ", i));
uint8_t j = 0;
do {
const char *prefix;
prefix = "[W]";
else
prefix = " ";
} while (++j < 8);
Log(("\n"));
i += 8;
} while (i != 0);
#endif
}
return rc;
}
{
int rc;
if (RT_FAILURE(rc))
{
corbRp++;
if (RT_FAILURE(rc))
(rirbWp)++;
else
if (RT_FAILURE(rc))
if ( (resp & CODEC_RESPONSE_UNSOLICITED)
{
Log(("hda: unexpected unsolicited response.\n"));
return rc;
}
break;
}
if (RIRBCTL_RIRB_RIC(pState))
{
}
if (RT_FAILURE(rc))
return rc;
}
static void hdaStreamReset(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
{
&& pBdle
&& pStreamDesc
&& u8Strm <= 7));
*pStreamDesc->pu32Lpib = 0;
*pStreamDesc->pu32Sts = 0;
/* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
* bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
HDA_STREAM_REG2(pState, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG2(pState, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
/* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
}
DECLCALLBACK(int) hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
{
*pu32Value = 0;
return VINF_SUCCESS;
}
DECLCALLBACK(int) hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
return VINF_SUCCESS;
}
/* U8 */
DECLCALLBACK(int) hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
{
}
DECLCALLBACK(int) hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
}
/* U16 */
DECLCALLBACK(int) hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
{
}
DECLCALLBACK(int) hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
}
/* U24 */
DECLCALLBACK(int) hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
{
}
DECLCALLBACK(int) hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
}
/* U32 */
DECLCALLBACK(int) hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
{
return VINF_SUCCESS;
}
DECLCALLBACK(int) hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
return VINF_SUCCESS;
}
DECLCALLBACK(int) hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
{
}
DECLCALLBACK(int) hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
{
/* exit reset state */
}
else
{
/* enter reset state*/
{
Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
}
}
{
/* Flush: GSTS:1 set, see 6.2.6*/
/* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/
}
return VINF_SUCCESS;
}
DECLCALLBACK(int) hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
return VINF_SUCCESS;
}
DECLCALLBACK(int) hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
{
uint32_t v = 0;
if ( RIRBSTS_RIRBOIS(pState)
|| RIRBSTS_RINTFL(pState)
v |= RT_BIT(30);
#define MARK_STREAM(pState, stream, v) do {(v) |= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
MARK_STREAM(pState, 0, v);
v |= v ? RT_BIT(31) : 0;
*pu32Value = v;
return VINF_SUCCESS;
}
DECLCALLBACK(int) hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
{
/* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
*pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(ICH6_HDASTATE_2_DEVINS(pState)) - pState->u64BaseTS, 24, 1000);
return VINF_SUCCESS;
}
DECLCALLBACK(int) hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
{
}
DECLCALLBACK(int) hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
else
return VINF_SUCCESS;
}
DECLCALLBACK(int) hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
return hdaCORBCmdProcess(pState);
return rc;
}
DECLCALLBACK(int) hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
return VINF_SUCCESS;
}
DECLCALLBACK(int) hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
int rc;
if (RT_FAILURE(rc))
return VINF_SUCCESS;
return VINF_SUCCESS;
return rc;
}
DECLCALLBACK(int) hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
{
}
DECLCALLBACK(int) hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
int rc = VINF_SUCCESS;
if (fInReset)
{
/* Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
* from reset
*/
Log(("hda: guest initiated exit of stream reset.\n"));
goto done;
}
else if (fReset)
{
/*
* Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
*/
switch (index)
{
case ICH6_HDA_REG_SD0CTL:
u8Strm = 0;
break;
case ICH6_HDA_REG_SD4CTL:
u8Strm = 4;
break;
default:
Log(("hda: changing SRST bit on non-attached stream\n"));
goto done;
}
Log(("hda: guest initiated enter to stream reset.\n"));
goto done;
}
/* we enter here to change DMA states only */
{
switch (index)
{
case ICH6_HDA_REG_SD0CTL:
break;
case ICH6_HDA_REG_SD4CTL:
break;
default:
Log(("hda: changing RUN bit on non-attached stream\n"));
goto done;
}
}
done:
if (RT_FAILURE(rc))
return rc;
}
DECLCALLBACK(int) hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
v &= ~(u32Value & v);
return VINF_SUCCESS;
}
DECLCALLBACK(int) hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
if (RT_FAILURE(rc))
return rc;
}
DECLCALLBACK(int) hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
switch (u32Value)
{
case HDA_SDFIFOW_8B:
case HDA_SDFIFOW_16B:
case HDA_SDFIFOW_32B:
default:
}
return VINF_SUCCESS;
}
/*
* Note this method could be called for changing value on Output Streams only (ICH6 datasheet 18.2.39)
*
*/
DECLCALLBACK(int) hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
switch (index)
{
/* SDInFIFOS is RO, n=0-3 */
case ICH6_HDA_REG_SD0FIFOS:
case ICH6_HDA_REG_SD1FIFOS:
case ICH6_HDA_REG_SD2FIFOS:
case ICH6_HDA_REG_SD3FIFOS:
Log(("hda: Guest tries change value of FIFO size of Input Stream\n"));
return VINF_SUCCESS;
case ICH6_HDA_REG_SD4FIFOS:
case ICH6_HDA_REG_SD5FIFOS:
case ICH6_HDA_REG_SD6FIFOS:
case ICH6_HDA_REG_SD7FIFOS:
switch(u32Value)
{
case HDA_SDONFIFO_16B:
case HDA_SDONFIFO_32B:
case HDA_SDONFIFO_64B:
case HDA_SDONFIFO_128B:
case HDA_SDONFIFO_192B:
case HDA_SDONFIFO_256B:
Log(("hda: 256-bit is unsupported, HDA is switched into 192-bit mode\n"));
default:
}
return VINF_SUCCESS;
default:
AssertMsgFailed(("Something weird happened with register lookup routine"));
}
return VINF_SUCCESS;
}
{
Assert((pAudSetting));
{
case 0: u32HzMult = 1; break;
default:
}
{
case 0: u32HzDiv = 1; break;
}
{
case 0:
break;
case 1:
break;
case 2:
break;
case 3:
break;
case 4:
break;
default:
AssertMsgFailed(("Unsupported"));
}
pAudSetting->endianness = 0;
}
DECLCALLBACK(int) hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
#ifdef VBOX_WITH_HDA_CODEC_EMU
/* @todo a bit more investigation is required here. */
int rc = 0;
/* no reason to reopen voice with same settings */
return VINF_SUCCESS;
switch (index)
{
case ICH6_HDA_REG_SD0FMT:
break;
case ICH6_HDA_REG_SD4FMT:
break;
default:
rc = 0;
}
#else
#endif
}
DECLCALLBACK(int) hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
if (RT_FAILURE(rc))
return rc;
}
DECLCALLBACK(int) hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
if (RT_FAILURE(rc))
return rc;
}
DECLCALLBACK(int) hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
{
int rc = VINF_SUCCESS;
/* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
return rc;
}
DECLCALLBACK(int) hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
int rc = VINF_SUCCESS;
/*
* if guest set the ICB bit of IRS register, HDA should process the verb in IC register,
* write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
*/
{
{
/*
* 3.4.3 defines behavior of immediate Command status register.
*/
return rc;
}
if (RT_FAILURE(rc))
if (RT_FAILURE(rc))
return rc;
}
/*
* Once the guest read the response, it should clean the IRV bit of the IRS register.
*/
return rc;
}
DECLCALLBACK(int) hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
{
}
/* The remaining bits are O, see 6.2.22 */
return VINF_SUCCESS;
}
DECLCALLBACK(int) hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
if (RT_FAILURE(rc))
switch(index)
{
case ICH6_HDA_REG_CORBLBASE:
break;
case ICH6_HDA_REG_CORBUBASE:
break;
case ICH6_HDA_REG_RIRLBASE:
break;
case ICH6_HDA_REG_RIRUBASE:
break;
case ICH6_HDA_REG_DPLBASE:
/* @todo: first bit has special meaning */
break;
case ICH6_HDA_REG_DPUBASE:
break;
default:
AssertMsgFailed(("Invalid index"));
}
Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
return rc;
}
DECLCALLBACK(int) hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
{
return hdaProcessInterrupt(pState);
}
#ifdef LOG_ENABLED
{
#if 0
uint32_t i;
for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
{
Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
}
for (i = 0; i < 8; ++i)
{
PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pState, 4) || i == SDCTL_NUM(pState, 0)? "[C]": " ",
i , counter));
}
#endif
}
#endif
static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
{
&& pBdle
&& pBdle->u32BdleMaxCvi));
PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
#ifdef LOG_ENABLED
#endif
}
static inline uint32_t hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
{
/*
* Number of bytes depends on the current position in buffer (u32BdleCviLen-u32BdleCviPos)
*/
/*
* we may increase the counter in range of [0, FIFOS + 1]
*/
/* sanity check to avoid overriding the backend audio buffer */
return 0;
return cb2Copy;
}
DECLINLINE(void) hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
{
Log(("hda:hdaBackendWriteTransferReported: cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
/* Assertion!!! Fewer than cbUnderFifoW bytes were copied.
* Probably we need to move the buffer, but it is rather hard to imagine a situation
* where it might happen.
*/
Assert((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy)); /* we assume that we write the entire buffer including unreported bytes */
if ( pBdle->cbUnderFifoW
Log(("hda:hdaBackendWriteTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
/* We always increment the position of DMA buffer counter because we're always reading into an intermediate buffer */
Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
/* We report all bytes (including previously unreported bytes) */
*pu32DMACursor += cbCopied;
/* Decrease the backend counter by the number of bytes we copied to the backend */
Log(("hda:hdaBackendWriteTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
}
DECLINLINE(void) hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
{
Log(("hda:hdaBackendReadTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
pBdle->cbUnderFifoW = 0;
Log(("hda:hdaBackendReadTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
}
DECLINLINE(void) hdaBackendTransferUnreported(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
{
Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
/* In case of a read transaction we're always copying from the backend buffer */
Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
}
static inline bool hdaIsTransferCountersOverlapped(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
{
/* don't touch BdleCvi counter on uninitialized descriptor */
if ( pBdle->u32BdleCviPos
{
pBdle->u32BdleCviPos = 0;
pBdle->u32BdleCvi++;
pBdle->u32BdleCvi = 0;
}
return fOnBufferEdge;
}
DECLINLINE(void) hdaStreamCounterUpdate(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbInc)
{
/*
* if we're below the FIFO Watermark, it's expected that HDA doesn't fetch anything.
* (ICH6 datasheet 18.2.38)
*/
if (!pBdle->cbUnderFifoW)
{
/*
* Assert. The buffer counters should never overlap.
*/
}
}
static inline bool hdaDoNextTransferCycle(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
{
bool fDoNextTransferLoop = true;
{
if ( !pBdle->cbUnderFifoW
&& pBdle->fBdleCviIoc)
{
/*
* @todo - more carefully investigate BCIS flag.
* Speech synthesis works fine on Mac Guest if this bit isn't set
* but in general sound quality gets worse.
*/
/*
* we should generate the interrupt if ICE bit of SDCTL register is set.
*/
}
fDoNextTransferLoop = false;
}
return fDoNextTransferLoop;
}
/*
* hdaReadAudio - copies samples from audio backend to DMA.
* Note: this function writes to the DMA buffer immediately, but "reports bytes" when all conditions are met (FIFOW)
*/
static uint32_t hdaReadAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
{
uint32_t cbTransferred = 0;
uint32_t cbBackendCopy = 0;
if (!cb2Copy)
{
/* if we enter here we can't report "unreported bits" */
*fStop = true;
goto done;
}
/*
* read from backend input line to the last unreported position or at the begining.
*/
/*
* write the HDA DMA buffer
*/
PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
/* Don't see any reason why cb2Copy would differ from cbBackendCopy */
else
{
*fStop = true;
}
done:
Log(("hda:ra: CVI(pos:%d, len:%d) cbTransferred: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
return cbTransferred;
}
static uint32_t hdaWriteAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
{
uint32_t cbTransferred = 0;
Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
/*
* Copy from DMA to the corresponding hdaBuffer (if there are any bytes from the previous unreported transfer we write at offset ''pBdle->cbUnderFifoW'')
*/
if (!cb2Copy)
{
*fStop = true;
goto done;
}
PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
/*
* Write to audio backend. we should ensure that we have enough bytes to copy to the backend.
*/
{
/*
* Feed the newly fetched samples, including unreported ones, to the backend.
*/
cbBackendCopy = AUD_write (pState->Codec.SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
}
else
{
/* Not enough bytes to be processed and reported, we'll try our luck next time around */
*fStop = true;
}
done:
Log(("hda:wa: CVI(pos:%d, len:%d, cbTransferred:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
return cbTransferred;
}
{
return VINF_SUCCESS;
}
DECLINLINE(void) hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc)
{
&& pBdle
&& pStreamDesc
&& u8Strm <= 7));
#ifdef LOG_ENABLED
if ( pBdle
&& pBdle->u32BdleMaxCvi)
{
Log(("Initialization of transfer descriptor:\n"));
}
#endif
}
{
bool fStop = false;
switch (src)
{
case PO_INDEX:
{
u8Strm = 4;
break;
}
case PI_INDEX:
{
u8Strm = 0;
break;
}
default:
return;
}
{
&& avail
&& stStreamDesc.u64BaseDMA);
/* Fetch the Buffer Descriptor Entry (BDE). */
switch (src)
{
case PO_INDEX:
break;
case PI_INDEX:
break;
default:
nBytes = 0;
fStop = true;
AssertMsgFailed(("Unsupported"));
}
/* Process end of buffer condition. */
}
}
/**
* Handle register read operation.
*
* Looks up and calls the appropriate handler.
*
* @note: During implementation, we discovered so-called "forgotten" or "hole" registers
* whose description is not listed in the RPM, datasheet, or spec.
*
* @returns VBox status code.
*
* @param pState The device state structure.
* @param uOffset Register offset in memory-mapped area.
* @param pv Where to place the value.
* @param cb Number of bytes to write.
* @thread EMT
*/
PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
{
int rc = VINF_SUCCESS;
Log(("hda: access to registers except GCTL is blocked while reset\n"));
if (idxReg == -1)
if (idxReg != -1)
{
/** @todo r=bird: Accesses crossing register boundraries aren't handled
* right from what I can tell? If they are, please explain
* what the rules are. */
switch(cb)
{
case 4:
/* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
case 8:
mask = 0xffffffff;
cb = 4;
break;
}
#if 0
/* Cross-register access. Mac guest hits this assert doing assumption 4 byte access to 3 byte registers e.g. {I,O}SDnCTL
*/
//Assert((cb <= s_ichIntelHDRegMap[idxReg].size - (offReg - s_ichIntelHDRegMap[idxReg].offset)));
{
if (RT_FAILURE(rc))
}
//Assert(((offReg - s_ichIntelHDRegMap[idxReg].offset) == 0));
#endif
return rc;
}
return rc;
}
/**
* Handle register write operation.
*
* Looks up and calls the appropriate handler.
*
* @returns VBox status code.
*
* @param pState The device state structure.
* @param uOffset Register offset in memory-mapped area.
* @param pv Where to fetch the value.
* @param cb Number of bytes to write.
* @thread EMT
*/
PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
{
int rc = VINF_SUCCESS;
Log(("hda: access to registers except GCTL is blocked while reset\n"));
if ( idxReg == -1
|| cb > 4)
if (idxReg != -1)
{
/** @todo r=bird: This looks like code for handling unaligned register
* accesses. If it isn't, then add a comment explaining what you're
* trying to do here. OTOH, if it is then it has the following
* issues:
* -# You're calculating the wrong new value for the register.
* -# You're not handling cross register accesses. Imagine a
* 4-byte write starting at CORBCTL, or a 8-byte write.
*
* nobody seems to be using it and it just adds complexity when reading
* the code.
*
*/
switch (cb)
{
case 1:
mask = 0xff;
break;
case 2:
mask = 0xffff;
break;
case 4:
case 8:
/* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
mask = 0xffffffff;
cb = 4;
break;
default:
}
/* cross-register access, see corresponding comment in hdaMMIORead */
#if 0
{
if (RT_FAILURE(rc))
}
#endif
u32NewValue <<= shift;
u32NewValue &= mask;
return rc;
}
return rc;
}
/**
* Callback function for mapping a PCI I/O region.
*
* @return VBox status code.
* @param pPciDev Pointer to PCI device.
* Use pPciDev->pDevIns to get the device instance.
* @param iRegion The region number.
* @param GCPhysAddress Physical address of the region.
* If iType is PCI_ADDRESS_SPACE_IO, this is an
* I/O port, else it's a physical address.
* This address is *NOT* relative
* to pci_mem_base like earlier!
* @param enmType One of the PCI_ADDRESS_SPACE_* values.
*/
{
int rc;
if (RT_FAILURE(rc))
return rc;
return VINF_SUCCESS;
}
/**
* Saves the state of the HDA device.
*
* @returns VBox status code.
* @param pDevIns The device instance.
* @param pSSM The handle to save the state to.
*/
{
/* Save Codec nodes states */
/* Save MMIO registers */
/* Save HDA dma counters */
SSMR3PutStructEx(pSSM, &pThis->hda.stOutBdle, sizeof(pThis->hda.stOutBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
SSMR3PutStructEx(pSSM, &pThis->hda.stMicBdle, sizeof(pThis->hda.stMicBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
SSMR3PutStructEx(pSSM, &pThis->hda.stInBdle, sizeof(pThis->hda.stInBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
return VINF_SUCCESS;
}
/**
* Loads a saved HDA device state.
*
* @returns VBox status code.
* @param pDevIns The device instance.
* @param pSSM The handle to the saved state.
* @param uVersion The data unit version number.
* @param uPass The data pass.
*/
static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
{
/*
* Load Codec nodes states.
*/
if (RT_FAILURE(rc))
return rc;
/*
* Load MMIO registers.
*/
switch (uVersion)
{
case HDA_SSM_VERSION_1:
/* Starting with r71199, we would save 112 instead of 113
registers due to some code cleanups. This only affected trunk
builds in the 4.1 development period. */
cRegs = 113;
{
&& VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
cRegs = 112;
}
break;
case HDA_SSM_VERSION_2:
case HDA_SSM_VERSION_3:
cRegs = 112;
break;
case HDA_SSM_VERSION:
break;
default:
}
{
}
else
{
}
/*
* Load HDA dma counters.
*/
PCSSMFIELD paFields = uVersion <= HDA_SSM_VERSION_2 ? g_aHdaBDLEDescFieldsOld : g_aHdaBDLEDescFields;
SSMR3GetStructEx(pSSM, &pThis->hda.stOutBdle, sizeof(pThis->hda.stOutBdle), fFlags, paFields, NULL);
SSMR3GetStructEx(pSSM, &pThis->hda.stMicBdle, sizeof(pThis->hda.stMicBdle), fFlags, paFields, NULL);
rc = SSMR3GetStructEx(pSSM, &pThis->hda.stInBdle, sizeof(pThis->hda.stInBdle), fFlags, paFields, NULL);
/*
* Update stuff after the state changes.
*/
AUD_set_active_in(pThis->hda.Codec.SwVoiceIn, SDCTL(&pThis->hda, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
AUD_set_active_out(pThis->hda.Codec.SwVoiceOut, SDCTL(&pThis->hda, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
return VINF_SUCCESS;
}
/**
* Reset notification.
*
* @returns VBox status.
* @param pDevIns The device instance data.
*
* @remark The original sources didn't install a reset handler, but it seems to
* make sense to me so we'll do it.
*/
{
Log(("hda: inter HDA reset.\n"));
else
else
{
if (u8Strm == 0)
else if(u8Strm == 4)
else
{
pBdle = &stEmptyBdle;
}
/* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
}
/* emulation of codec "wake up" (HDA spec 5.5.1 and 6.5)*/
Log(("hda: reset finished\n"));
}
/**
* @interface_method_impl{PDMIBASE,pfnQueryInterface}
*/
const char *pszIID)
{
return NULL;
}
{
int iReg = 0;
return iReg;
return -1;
}
{
&& iHdaIndex >= 0
pHlp->pfnPrintf(pHlp, "hda: %s: 0x%x\n", s_ichIntelHDRegMap[iHdaIndex].abbrev, pState->au32Regs[iHdaIndex]);
}
{
if (iHdaRegisterIndex != -1)
else
}
{
&& iHdaStrmIndex >= 0
&& iHdaStrmIndex < 7);
pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, CTL, iHdaStrmIndex));
pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, STS, iHdaStrmIndex));
pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOS, iHdaStrmIndex));
pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOW, iHdaStrmIndex));
}
{
/* todo: add args parsing */
return -1;
}
static DECLCALLBACK(void) hdaDbgStreamInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
{
if (iHdaStrmIndex != -1)
else
}
/* Codec debugger interface */
static DECLCALLBACK(void) hdaCodecDbgNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
{
else
}
static DECLCALLBACK(void) hdaCodecDbgSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
{
else
}
//#define HDA_AS_PCI_EXPRESS
/* Misc routines */
{
}
static const char *printHdaYesNo(bool fFlag)
{
}
static DECLCALLBACK(size_t)
void *pvUser)
{
return cb;
"SDCTL(raw: %#0x, strm:0x%x, dir:%s, tp:%s strip:%x, deie:%s, ioce:%s, run:%s, srst:%s)",
return cb;
}
static DECLCALLBACK(size_t)
void *pvUser)
{
return cb;
switch(sdFifos)
{
default:;
}
"SDFIFOS(raw: %#0x, sdfifos:%d B)",
u32Bytes);
return cb;
}
static DECLCALLBACK(size_t)
void *pvUser)
{
return cb;
switch(sdFifow)
{
}
"SDFIFOW(raw: %#0x, sdfifow:%d B)",
u32Bytes);
return cb;
}
static DECLCALLBACK(size_t)
void *pvUser)
{
return cb;
"SDSTS(raw: %#0x, fifordy:%s, dese:%s, fifoe:%s, bcis:%s)",
return cb;
}
/**
* This routine registers debugger info extensions and custom printf formatters
*/
{
int rc;
PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaDbgInfo);
PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaDbgStreamInfo);
PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaCodecDbgSelector);
#if 0
#endif
return rc;
}
/**
* @interface_method_impl{PDMDEVREG,pfnConstruct}
*/
{
int rc;
/*
* Validations.
*/
N_ ("Invalid configuration for the Intel HDA device"));
// poll some register(s).
/*
* Initialize data (most of it anyway).
*/
/* IBase */
/* PCI Device */
false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
#if defined(HDA_AS_PCI_EXPRESS)
#elif defined(VBOX_WITH_MSI_DEVICES)
#else
#endif
/// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
// of these values needs to be properly documented!
/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
/* Power Management */
#ifdef HDA_AS_PCI_EXPRESS
/* PCI Express */
/* Device flags */
/* version */ 0x1 |
/* MSI */ (100) << 9
);
/* Device capabilities */
/* Device control */
/* Device status */
/* Link caps */
/* Link control */
/* Link status */
/* Slot capabilities */
/* Slot control */
/* Slot status */
/* Root control */
/* Root capabilities */
/* Root status */
/* Device capabilities 2 */
/* Device control 2 */
/* Link control 2 */
/* Slot control 2 */
#endif
/*
* Register the PCI device.
*/
if (RT_FAILURE (rc))
return rc;
hdaMap);
if (RT_FAILURE (rc))
return rc;
#ifdef VBOX_WITH_MSI_DEVICES
if (RT_FAILURE (rc))
{
}
#endif
if (RT_FAILURE (rc))
return rc;
/*
* Attach driver.
*/
&s->pDrvBase, "Audio Driver Port");
if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
Log (("hda: No attached driver!\n"));
else if (RT_FAILURE (rc))
{
return rc;
}
if (RT_FAILURE(rc))
/* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
/*
* hdaReset shouldn't affects these registers.
*/
return VINF_SUCCESS;
}
/**
* @interface_method_impl{PDMDEVREG,pfnDestruct}
*/
{
return VINF_SUCCESS;
}
/**
* The device registration structure.
*/
const PDMDEVREG g_DeviceICH6_HDA =
{
/* u32Version */
/* szName */
"hda",
/* szRCMod */
"",
/* szR0Mod */
"",
/* pszDescription */
"Intel HD Audio Controller",
/* fFlags */
/* fClass */
/* cMaxInstances */
1,
/* cbInstance */
sizeof(PCIINTELHDLinkState),
/* pfnConstruct */
/* pfnDestruct */
/* pfnRelocate */
NULL,
/* pfnIOCtl */
NULL,
/* pfnPowerOn */
NULL,
/* pfnReset */
/* pfnSuspend */
NULL,
/* pfnResume */
NULL,
/* pfnAttach */
NULL,
/* pfnDetach */
NULL,
/* pfnQueryInterface. */
NULL,
/* pfnInitComplete */
NULL,
/* pfnPowerOff */
NULL,
/* pfnSoftReset */
NULL,
/* u32VersionEnd */
};