DevIchIntelHDA.cpp revision 48a5358f2f99d054c9b6a1a0f063c11c9addfe14
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync * DevIchIntelHD - VBox ICH Intel HD Audio Controller.
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync * Copyright (C) 2006-2010 Oracle Corporation
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * available from http://www.virtualbox.org. This file is free software;
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * you can redistribute it and/or modify it under the terms of the GNU
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * General Public License (GPL) as published by the Free Software
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync/*******************************************************************************
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync* Header Files *
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync*******************************************************************************/
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsyncextern "C" {
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync//#define USE_MIXER
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncPDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncPDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncstatic DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync/* Registers */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync#define STATESTS(pState) (HDA_REG((pState), STATESTS))
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define INTCTL_GIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define INTCTL_CIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define INTCTL_SX(pState, X) (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define INTCTL_SALL(pState) (INTCTL((pState)) & 0xFF)
0c94a8282c9042b02f022302a3d987746140eab9vboxsync/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
0c94a8282c9042b02f022302a3d987746140eab9vboxsync * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
0c94a8282c9042b02f022302a3d987746140eab9vboxsync * the datasheet.
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync#define INTSTS_GIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync#define INTSTS_CIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync#define INTSTS_SX(pState, X) (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define INTSTS_SANY(pState) (INTSTS((pState)) & 0xFF)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define CORBLBASE(pState) (HDA_REG((pState), CORBLBASE))
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define CORBUBASE(pState) (HDA_REG((pState), CORBUBASE))
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define CORBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync#define CORBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync/* till ich 10 sizes of CORB and RIRB are harcoded to 256 in real hw */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define RIRLBASE(pState) (HDA_REG((pState), RIRLBASE))
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define RIRUBASE(pState) (HDA_REG((pState), RIRUBASE))
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync#define RINTCNT(pState) (HDA_REG((pState), RINTCNT))
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync#define RINTCNT_N(pState) (RINTCNT((pState)) & 0xff)
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync#define RIRBCTL(pState) (HDA_REG((pState), RIRBCTL))
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync#define RIRBCTL_RIRB_RIC(pState) (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync#define RIRBCTL_RIRB_DMA(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define RIRBCTL_ROI(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define RIRBSTS_RINTFL(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define RIRBSTS_RIRBOIS(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define RIRBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define RIRBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define IRS_ICB(pState) (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define IRS_IRV(pState) (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define DPLBASE(pState) (HDA_REG((pState), DPLBASE))
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define DPUBASE(pState) (HDA_REG((pState), DPUBASE))
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define HDA_STREAM_REG(pState, name, num) (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define SDCTL(pState, num) HDA_REG((pState), SD(CTL, num))
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#define SDSTS(pState, num) HDA_REG((pState), SD(STS, num))
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define SDLPIB(pState, num) HDA_REG((pState), SD(LPIB, num))
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define SDLCBL(pState, num) HDA_REG((pState), SD(CBL, num))
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync#define SDLVI(pState, num) HDA_REG((pState), SD(LVI, num))
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
56970d3a1944c7c073d66266cd52449835221badvboxsync#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define SDFIFOS(pState, num) HDA_REG((pState), SD(FIFOS, num))
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define SDFMT(pState, num) (HDA_REG((pState), SD(FMT, num)))
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define SDFMT_BASE_RATE(pState, num) ((SDFMT(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync#define SDFMT_MULT(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define SDFMT_DIV(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define SDBDPL(pState, num) HDA_REG((pState), SD(BDPL, num))
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#define SDBDPU(pState, num) HDA_REG((pState), SD(BDPU, num))
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync/* Predicates */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsynctypedef struct HDABDLEDESC
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Pointer to the device instance. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Pointer to the connector of the attached audio driver. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Pointer to the attached audio driver. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** The base interface for LUN\#0. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* Interrupt on completition */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* pointer on CORB buf */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* size in bytes of CORB buf */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* pointer on RIRB buf */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* size in bytes of RIRB buf */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* indicates if HDA in reset. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PCIINTELHDLinkState *)(pPciDev))
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define ISD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, In, \
0c94a8282c9042b02f022302a3d987746140eab9vboxsync SDFMT_BASE_RATE(pState, 0), SDFMT_MULT(pState, 0), SDFMT_DIV(pState, 0)))
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define OSD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, Out, \
0c94a8282c9042b02f022302a3d987746140eab9vboxsync SDFMT_BASE_RATE(pState, 4), SDFMT_MULT(pState, 4), SDFMT_DIV(pState, 4)))
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncDECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncDECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncDECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncDECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncDECLCALLBACK(int)hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncDECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncDECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncDECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncDECLCALLBACK(int)hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncDECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncDECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncDECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncDECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncDECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncDECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncDECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncDECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncDECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncDECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncDECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncDECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncDECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncDECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncDECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncDECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncDECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncDECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncDECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncDECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsyncDECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsyncDECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsyncstatic int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset);
f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsyncstatic void fetch_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync/* see 302349 p 6.2*/
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncconst static struct stIchIntelHDRegMap
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync /** Register offset in the register space. */
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync /** Size in bytes. Registers of size > 4 are in fact tables. */
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync /** Readable bits. */
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync /** Writable bits. */
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync /** Read callback. */
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync int (*pfnRead)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync /** Write callback. */
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync int (*pfnWrite)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync /** Abbreviated name. */
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync const char *abbrev;
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync /** Full name. */
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync const char *name;
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync /* offset size read mask write mask read callback write callback abbrev full name */
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync //** @todo r=michaln: Are guests really not reading the WALCLK register at all?
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync //** @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
1379dfd407ada5fab15655776896f13b61a951fdvboxsync { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
1379dfd407ada5fab15655776896f13b61a951fdvboxsync { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadU16 , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
1379dfd407ada5fab15655776896f13b61a951fdvboxsync { 0x0008E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOW", "ISD0 FIFO Watermark" },
1379dfd407ada5fab15655776896f13b61a951fdvboxsync { 0x00090, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FMT" , "ISD0 Format" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x000AE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOW", "ISD1 FIFO Watermark" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x000B0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FMT" , "ISD1 Format" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x000CE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOW", "ISD2 FIFO Watermark" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x000D0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FMT" , "ISD2 Format" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x000F0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FMT" , "ISD3 Format" },
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x0010E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FIFOW", "OSD0 FIFO Watermark" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FIFOS", "OSD0 FIFO Size" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FMT" , "OSD0 Format" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x0012E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FIFOW", "OSD1 FIFO Watermark" },
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FIFOS", "OSD1 FIFO Size" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FMT" , "OSD1 Format" },
4f4cb69bca6bfda8f4d911759d1f3c6f528a173dvboxsync { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
a66ec044d2a64d926996cd24da5faadccb070be3vboxsync { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
a66ec044d2a64d926996cd24da5faadccb070be3vboxsync { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
a66ec044d2a64d926996cd24da5faadccb070be3vboxsync { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
a66ec044d2a64d926996cd24da5faadccb070be3vboxsync { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
a66ec044d2a64d926996cd24da5faadccb070be3vboxsync { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
a66ec044d2a64d926996cd24da5faadccb070be3vboxsync { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
a66ec044d2a64d926996cd24da5faadccb070be3vboxsync { 0x0014E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FIFOW", "OSD2 FIFO Watermark" },
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FIFOS", "OSD2 FIFO Size" },
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FMT" , "OSD2 Format" },
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
0c94a8282c9042b02f022302a3d987746140eab9vboxsync { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
0c94a8282c9042b02f022302a3d987746140eab9vboxsync { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
0c94a8282c9042b02f022302a3d987746140eab9vboxsync { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
0c94a8282c9042b02f022302a3d987746140eab9vboxsync { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x0016E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FIFOW", "OSD3 FIFO Watermark" },
0c94a8282c9042b02f022302a3d987746140eab9vboxsync { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FIFOS", "OSD3 FIFO Size" },
0c94a8282c9042b02f022302a3d987746140eab9vboxsync { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FMT" , "OSD3 Format" },
0c94a8282c9042b02f022302a3d987746140eab9vboxsync { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncstatic int hdaProcessInterrupt(INTELHDLinkState* pState)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync#define IS_INTERRUPT_OCCURED_AND_ENABLED(pState, num) \
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync && (SDSTS(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync bool fIrq = false;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
20f21077abf35d7b7b618acb159267933907407fvboxsync PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncstatic int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset)
20f21077abf35d7b7b618acb159267933907407fvboxsync //** @todo r=michaln: A linear search of an array with over 100 elements is very inefficient.
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync for (;index < (int)(sizeof(s_ichIntelHDRegMap)/sizeof(s_ichIntelHDRegMap[0])); ++index)
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync && u32Offset < s_ichIntelHDRegMap[index].offset + s_ichIntelHDRegMap[index].size)
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /* Aliases HDA spec 3.3.45 */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync case 0x2084:
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync case 0x20A4:
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync case 0x20C4:
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync case 0x20E4:
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync case 0x2104:
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync case 0x2124:
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync case 0x2144:
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync case 0x2164:
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncstatic int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync const char *prefix;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync } while (j < 8);
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync } while(i != 0);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync const char *prefix;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync Log((" %s%016lx", prefix, pState->pu64RirbBuf[i + j]));
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync } while (++j < 8);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync } while (i != 0);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic int hdaCORBCmdProcess(INTELHDLinkState *pState)
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsync RIRBSTS((pState)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
23d8f7aff045c2bade1b168fee79a3e4749e2345vboxsyncstatic void hdaStreamReset(INTELHDLinkState *pState, uint32_t u32Offset)
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync Log(("hda: reset of stream (%x) started\n", u32Offset));
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync Log(("hda: reset of stream (%x) finished\n", u32Offset));
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncDECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
76f3a3817b6b96f5beb30b76efebdf2d87090cf0vboxsyncDECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
9b1d52365befbce1af8f32d53c2e563ee9169501vboxsyncDECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
76f3a3817b6b96f5beb30b76efebdf2d87090cf0vboxsync Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffffff00) == 0);
9b1d52365befbce1af8f32d53c2e563ee9169501vboxsync return hdaRegReadU32(pState, offset, index, pu32Value);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncDECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return hdaRegWriteU32(pState, offset, index, u32Value);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncDECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffff0000) == 0);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return hdaRegReadU32(pState, offset, index, pu32Value);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncDECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return hdaRegWriteU32(pState, offset, index, u32Value);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncDECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xff000000) == 0);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return hdaRegReadU32(pState, offset, index, pu32Value);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncDECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return hdaRegWriteU32(pState, offset, index, u32Value);
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsyncDECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync *pu32Value = pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable;
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsyncDECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync pState->au32Regs[index] = (u32Value & s_ichIntelHDRegMap[index].writable)
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync | (pState->au32Regs[index] & ~s_ichIntelHDRegMap[index].writable);
81614fc60e096e714022d10d38b70a36b9b21d48vboxsyncDECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
a655881be920ead6948994168c5ee09e5798aa05vboxsync return hdaRegReadU32(pState, offset, index, pu32Value);
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsyncDECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync /* exit reset state */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* enter reset state*/
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* Flush: GSTS:1 set, see 6.2.6*/
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync GSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* DPLBASE and DPUBASE, should be initialized with initial value (see 6.2.6)*/
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncDECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync pState->au32Regs[index] = (v ^ nv) & v; /* write of 1 clears corresponding bit */
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncDECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync ( (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync#define MARK_STREAM(pState, stream, v) do {(v) |= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncDECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return hdaRegReadU16(pState, offset, index, pu32Value);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncDECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return hdaRegWriteU8(pState, offset, index, u32Value);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncDECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync int rc = hdaRegWriteU8(pState, offset, index, u32Value);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncDECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync v = (v ^ u32Value) & v;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncDECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync rc = hdaRegWriteU16(pState, offset, index, u32Value);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncDECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return hdaRegReadU24(pState, offset, index, pu32Value);
56970d3a1944c7c073d66266cd52449835221badvboxsync#define HDA_STREAM_BITMASK(offset) (1 << (((offset) - 0x80) >> 5))
56970d3a1944c7c073d66266cd52449835221badvboxsync#define HDA_IS_STREAM_IN_RESET(pState, offset) ((pState)->u8StreamsInReset & HDA_STREAM_BITMASK((offset)))
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncDECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST))
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync LogRel(("hda: guest has iniated hw stream reset\n"));
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync pState->u8StreamsInReset |= HDA_STREAM_BITMASK(offset);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync HDA_REG_IND(pState, index) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync LogRel(("hda: guest has iniated exit of stream reset\n"));
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync pState->u8StreamsInReset &= ~HDA_STREAM_BITMASK(offset);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync HDA_REG_IND(pState, index) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
2d66abeefb9716ed570bb5714884d3fe08629452vboxsync /* @todo: use right offsets for right streams */
2d66abeefb9716ed570bb5714884d3fe08629452vboxsync if (u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync AUD_set_active_in(ISD0FMT_TO_AUDIO_SELECTOR(pState), 1);
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync u64BaseDMA |= (((uint64_t)SDBDPU(pState, 4)) << 32);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync AUD_set_active_out(OSD0FMT_TO_AUDIO_SELECTOR(pState), 1);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync AUD_set_active_in(ISD0FMT_TO_AUDIO_SELECTOR(pState), 0);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync AUD_set_active_out(OSD0FMT_TO_AUDIO_SELECTOR(pState), 0);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync int rc = hdaRegWriteU24(pState, offset, index, u32Value);
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsyncDECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync && (INTCTL_SALL(pState) & (1 << ((offset - 0x83) >> 5))))
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsyncDECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
20f21077abf35d7b7b618acb159267933907407fvboxsync int rc = hdaRegWriteU32(pState, offset, index, u32Value);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsyncDECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync int rc = hdaRegWriteU32(pState, offset, index, u32Value);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncDECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync int rc = hdaRegWriteU32(pState, offset, index, u32Value);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncDECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* clear busy, result is ready */
56970d3a1944c7c073d66266cd52449835221badvboxsyncDECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
56970d3a1944c7c073d66266cd52449835221badvboxsync if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /*The rest of bits are O, see 6.2.22 */
56970d3a1944c7c073d66266cd52449835221badvboxsyncDECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
56970d3a1944c7c073d66266cd52449835221badvboxsync int rc = hdaRegWriteU32(pState, offset, index, u32Value);
56970d3a1944c7c073d66266cd52449835221badvboxsync pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
56970d3a1944c7c073d66266cd52449835221badvboxsync pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
56970d3a1944c7c073d66266cd52449835221badvboxsync /* @todo: first bit has special meaning */
56970d3a1944c7c073d66266cd52449835221badvboxsync pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
56970d3a1944c7c073d66266cd52449835221badvboxsync Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
56970d3a1944c7c073d66266cd52449835221badvboxsyncDECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
56970d3a1944c7c073d66266cd52449835221badvboxsyncstatic void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
56970d3a1944c7c073d66266cd52449835221badvboxsync PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), u64BaseDMA + i*16, bdle, 16);
56970d3a1944c7c073d66266cd52449835221badvboxsync Log(("hda: %s bdle[%d] a:%lx, len:%x, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc));
56970d3a1944c7c073d66266cd52449835221badvboxsync for (i = 0; i < 8; ++i)
56970d3a1944c7c073d66266cd52449835221badvboxsync PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
56970d3a1944c7c073d66266cd52449835221badvboxsync Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pState, 4) || i == SDCTL_NUM(pState, 0)? "[C]": " ",
56970d3a1944c7c073d66266cd52449835221badvboxsyncstatic void fetch_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
56970d3a1944c7c073d66266cd52449835221badvboxsync Assert((u64BaseDMA && pBdle && pBdle->u32BdleMaxCvi));
56970d3a1944c7c073d66266cd52449835221badvboxsync PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
56970d3a1944c7c073d66266cd52449835221badvboxsync pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
56970d3a1944c7c073d66266cd52449835221badvboxsyncstatic uint32_t read_audio(INTELHDLinkState *pState, int avail, bool *fStop)
56970d3a1944c7c073d66266cd52449835221badvboxsync /* todo: add input line detection */
56970d3a1944c7c073d66266cd52449835221badvboxsync SWVoiceIn *voice = ISD0FMT_TO_AUDIO_SELECTOR(pState);
56970d3a1944c7c073d66266cd52449835221badvboxsync u32Rest = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
56970d3a1944c7c073d66266cd52449835221badvboxsync Log (("hda: read_audio max=%x to_copy=%x copied=%x\n",
56970d3a1944c7c073d66266cd52449835221badvboxsync PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, tmpbuf, copied);
56970d3a1944c7c073d66266cd52449835221badvboxsyncstatic uint32_t write_audio(INTELHDLinkState *pState, int avail, bool *fStop)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync u32Rest = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, tmpbuf, to_copy);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync copied = AUD_write (OSD0FMT_TO_AUDIO_SELECTOR(pState), tmpbuf, to_copy);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync Log (("hda: write_audio max=%x to_copy=%x copied=%x\n",
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncDECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsyncDECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync bool fStop = false;
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync u64BaseDMA |= (((uint64_t)SDBDPU(pState, 4)) << 32);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync u64BaseDMA |= (((uint64_t)SDBDPU(pState, 0)) << 32);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if ( !(u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* Fetch the Buffer Descriptor Entry (BDE). */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* Update the buffer position and handle Cyclic Buffer Length (CBL) wraparound. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* Optionally write back the current DMA position. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync (pState->u64DPBase & DPBASE_ADDR_MASK) + u8Strm*8, pu32Lpib, sizeof(*pu32Lpib));
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* Process end of buffer condition. */
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync fStop = true; /* Give the guest a chance to refill (or empty) buffers. */
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync * Handle register read operation.
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync * Looks up and calls appropriate handler.
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync * @note: while implementation was detected so called "forgotten" or "hole" registers
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync * which description is missed in RPM, datasheet or spec.
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync * @returns VBox status code.
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync * @param pState The device state structure.
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync * @param uOffset Register offset in memory-mapped frame.
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync * @param pv Where to fetch the value.
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync * @param cb Number of bytes to write.
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync * @thread EMT
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsyncPDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync Log(("hda: access to registers except GCTL is blocked while reset\n"));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync rc = s_ichIntelHDRegMap[index].pfnRead(&pThis->hda, u32Offset, index, &v);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync Log(("hda: read %s[%x/%x]\n", s_ichIntelHDRegMap[index].abbrev, v, *(uint32_t *)pv));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync Log(("hda: hole at %X is accessed for read\n", u32Offset));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * Handle register write operation.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * Looks up and calls appropriate handler.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @returns VBox status code.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @param pState The device state structure.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @param uOffset Register offset in memory-mapped frame.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @param pv Where to fetch the value.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @param cb Number of bytes to write.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @thread EMT
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncPDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync Log(("hda: access to registers except GCTL is blocked while reset\n"));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync *(uint32_t *)pv = ((v & mask) | (*(uint32_t *)pv & ~mask)) >> shift;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync rc = s_ichIntelHDRegMap[index].pfnWrite(&pThis->hda, u32Offset, index, *(uint32_t *)pv);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync Log(("hda: write %s:(%x) %x => %x\n", s_ichIntelHDRegMap[index].abbrev, *(uint32_t *)pv, v, pThis->hda.au32Regs[index]));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync Log(("hda: hole at %X is accessed for write\n", u32Offset));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * Callback function for mapping a PCI I/O region.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @return VBox status code.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @param pPciDev Pointer to PCI device.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * Use pPciDev->pDevIns to get the device instance.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @param iRegion The region number.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @param GCPhysAddress Physical address of the region.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * If iType is PCI_ADDRESS_SPACE_IO, this is an
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * I/O port, else it's a physical address.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * This address is *NOT* relative
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * to pci_mem_base like earlier!
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @param enmType One of the PCI_ADDRESS_SPACE_* values.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncstatic DECLCALLBACK(int) hdaMap (PPCIDEVICE pPciDev, int iRegion,
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync PCIINTELHDLinkState *pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * Saves a state of the HDA device.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @returns VBox status code.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @param pDevIns The device instance.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @param pSSMHandle The handle to save the state to.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncstatic DECLCALLBACK(int) hdaSaveExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync /* Save Codec nodes states */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync /* Save MMIO registers */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync SSMR3PutMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync /* Save HDA dma counters */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync SSMR3PutMem (pSSMHandle, &pThis->hda.stOutBdle, sizeof (HDABDLEDESC));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync SSMR3PutMem (pSSMHandle, &pThis->hda.stMicBdle, sizeof (HDABDLEDESC));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync SSMR3PutMem (pSSMHandle, &pThis->hda.stInBdle, sizeof (HDABDLEDESC));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * Loads a saved HDA device state.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @returns VBox status code.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @param pDevIns The device instance.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @param pSSMHandle The handle to the saved state.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @param uVersion The data unit version number.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @param uPass The data pass.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncstatic DECLCALLBACK(int) hdaLoadExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync /* Load Codec nodes states */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync AssertMsgReturn (uVersion == HDA_SSM_VERSION, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync /* Load MMIO registers */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync SSMR3GetMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync /* Load HDA dma counters */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync SSMR3GetMem (pSSMHandle, &pThis->hda.stOutBdle, sizeof (HDABDLEDESC));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync SSMR3GetMem (pSSMHandle, &pThis->hda.stMicBdle, sizeof (HDABDLEDESC));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync SSMR3GetMem (pSSMHandle, &pThis->hda.stInBdle, sizeof (HDABDLEDESC));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync AUD_set_active_in(ISD0FMT_TO_AUDIO_SELECTOR(&pThis->hda), SDCTL(&pThis->hda, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync AUD_set_active_out(OSD0FMT_TO_AUDIO_SELECTOR(&pThis->hda), SDCTL(&pThis->hda, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync pThis->hda.u64CORBBase |= ((uint64_t)CORBUBASE(&pThis->hda)) << 32;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync pThis->hda.u64RIRBBase |= ((uint64_t)RIRUBASE(&pThis->hda)) << 32;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync pThis->hda.u64DPBase |= ((uint64_t)DPUBASE(&pThis->hda)) << 32;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * Reset notification.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @returns VBox status.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @param pDevIns The device instance data.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @remark The original sources didn't install a reset handler, but it seems to
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * make sense to me so we'll do it.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncstatic DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync pThis->hda.au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync pThis->hda.au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync //** @todo r=michaln: There should be LogRel statements when the guest initializes
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync // or resets the HDA chip, and possibly also when opening the PCM streams.
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync memset(pThis->hda.pu32CorbBuf, 0, pThis->hda.cbCorbBuf);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync pThis->hda.pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->hda.cbCorbBuf);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync memset(pThis->hda.pu64RirbBuf, 0, pThis->hda.cbRirbBuf);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync pThis->hda.pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->hda.cbRirbBuf);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync /* Accoding to ICH6 datasheet, 0x40000 is default value for stream descriptor register 23:20
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * bits are reserved for stream number 18.2.33 */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync /* emulateion of codec "wake up" HDA spec (5.5.1 and 6.5)*/
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @interface_method_impl{PDMIBASE,pfnQueryInterface}
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncstatic DECLCALLBACK(void *) hdaQueryInterface (struct PDMIBASE *pInterface,
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync const char *pszIID)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync PCIINTELHDLinkState *pThis = RT_FROM_MEMBER(pInterface, PCIINTELHDLinkState, hda.IBase);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->hda.IBase);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync//#define HDA_AS_PCI_EXPRESS
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * @interface_method_impl{PDMDEVREG,pfnConstruct}
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncstatic DECLCALLBACK(int) hdaConstruct (PPDMDEVINS pDevIns, int iInstance,
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync * Validations.
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync return PDMDEV_SET_ERROR (pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync N_ ("Invalid configuration for the INTELHD device"));
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync // ** @todo r=michaln: This device may need R0/RC enabling, especially if guests
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync // poll some register(s).
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync * Initialize data (most of it anyway).
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* IBase */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* PCI Device (the assertions will be removed later) */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Linux kernel has whitelist for MSI-enabled HDA, this card seems to be there. */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetDeviceId (&pThis->dev, 0x30f7); /* HP Pavilion dv4t-1300 */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetVendorId (&pThis->dev, 0x8086); /* 00 ro - intel. */
f40cc8247b1da75ce42e73e6c557ec29b8f830a5vboxsync PCIDevSetDeviceId (&pThis->dev, 0x2668); /* 02 ro - 82801 / 82801aa(?). */
f40cc8247b1da75ce42e73e6c557ec29b8f830a5vboxsync PCIDevSetVendorId (&pThis->dev, 0x10de); /* nVidia */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync# error "Please specify your HDA device vendor/device IDs"
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetStatus (&pThis->dev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetClassSub (&pThis->dev, 0x03); /* 0a ro - scc; 03 == HDA. */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - MMIO */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetCapabilityList (&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync //** @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync // of these values needs to be properly documented!
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Power Management */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetByte(&pThis->dev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetByte(&pThis->dev, 0x50 + 1, 0x0); /* next */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetWord(&pThis->dev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* PCI Express */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetByte (&pThis->dev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetByte (&pThis->dev, 0x80 + 1, 0x60); /* next */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Device flags */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Device capabilities */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PCIDevSetDWord (&pThis->dev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Device control */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Device status */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Link caps */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Link control */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Link status */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync /* Slot capabilities */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync /* Slot control */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Slot status */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Root control */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Root capabilities */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Root status */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Device capabilities 2 */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Device control 2 */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Link control 2 */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Slot control 2 */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync * Register the PCI device.
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync rc = PDMDevHlpPCIIORegionRegister (pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM,
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync rc = PDMDevHlpSSMRegister (pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync * Attach driver.
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync AssertMsgFailed (("Failed to attach INTELHD LUN #0! rc=%Rrc\n", rc));
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync rc = codecConstruct(&pThis->hda.Codec, /* ALC885_CODEC */ STAC9220_CODEC);
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync verb F20 should provide device/codec recognition. */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync PCIDevSetSubSystemVendorId (&pThis->dev, pThis->hda.Codec.u16VendorId); /* 2c ro - intel.) */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync PCIDevSetSubSystemId (&pThis->dev, pThis->hda.Codec.u16DeviceId); /* 2e ro. */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync * hdaReset shouldn't affects these registers.
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync * @interface_method_impl{PDMDEVREG,pfnDestruct}
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsyncstatic DECLCALLBACK(int) hdaDestruct (PPDMDEVINS pDevIns)
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync * The device registration structure.
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync /* u32Version */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync /* szName */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync /* szRCMod */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync /* szR0Mod */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync /* pszDescription */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync "ICH IntelHD Audio Controller",
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync /* fFlags */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync /* fClass */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync /* cMaxInstances */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync /* cbInstance */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync /* pfnConstruct */
9540ab73f6cd0c76f44f6bbfe73f89ac145390b8vboxsync /* pfnDestruct */
8f7ee9e453c60b3b699799538a45950b35266665vboxsync /* pfnRelocate */
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync /* pfnIOCtl */
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync /* pfnPowerOn */
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync /* pfnReset */
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync /* pfnSuspend */
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync /* pfnResume */
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync /* pfnAttach */
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync /* pfnDetach */
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync /* pfnQueryInterface. */
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync /* pfnInitComplete */
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync /* pfnPowerOff */
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync /* pfnSoftReset */
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync /* u32VersionEnd */