#define LOG_GROUP LOG_GROUP_DEV_AUDIO

#include <VBox/vmm/pdmdev.h>

#include <VBox/version.h>

#include <iprt/assert.h>

#include <iprt/uuid.h>

#include <iprt/string.h>

#include <iprt/mem.h>

#include <iprt/asm.h>

#include <iprt/asm-math.h>

#include "VBoxDD.h"

extern "C" {

#include "audio.h"

}

#include "DevIchHdaCodec.h"

#define VBOX_WITH_INTEL_HDA

#if defined(VBOX_WITH_HP_HDA)

# define HDA_PCI_VENDOR_ID 0x103c

# define HDA_PCI_DEICE_ID 0x30f7

#elif defined(VBOX_WITH_INTEL_HDA)

# define HDA_PCI_VENDOR_ID 0x8086

# define HDA_PCI_DEICE_ID 0x2668

#elif defined(VBOX_WITH_NVIDIA_HDA)

# define HDA_PCI_VENDOR_ID 0x10de

# define HDA_PCI_DEICE_ID 0x0ac0

#else

# error "Please specify your HDA device vendor/device IDs"

#endif

#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO

#define HDA_NREGS 112

#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x

#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x

#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK

#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)

#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT

#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[(x)])

#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))

#define HDA_REG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))

#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))

#define HDA_REG_SVALUE(pThis, reg, val) (HDA_REG_VALUE(pThis, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))

#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/

#define GCAP(pThis) (HDA_REG((pThis), GCAP))

#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \

( (((oss) & 0xF) << 12) \

| (((iss) & 0xF) << 8) \

| (((bss) & 0x1F) << 3) \

| (((bds) & 0x3) << 2) \

| ((b64sup) & 1))

#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */

#define VMIN(pThis) (HDA_REG((pThis), VMIN))

#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */

#define VMAJ(pThis) (HDA_REG((pThis), VMAJ))

#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */

#define OUTPAY(pThis) (HDA_REG((pThis), OUTPAY))

#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */

#define INPAY(pThis) (HDA_REG((pThis), INPAY))

#define ICH6_HDA_REG_GCTL (5)

#define ICH6_HDA_GCTL_RST_SHIFT (0)

#define ICH6_HDA_GCTL_FSH_SHIFT (1)

#define ICH6_HDA_GCTL_UR_SHIFT (8)

#define GCTL(pThis) (HDA_REG((pThis), GCTL))

#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */

#define WAKEEN(pThis) (HDA_REG((pThis), WAKEEN))

#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */

#define STATESTS(pThis) (HDA_REG((pThis), STATESTS))

#define ICH6_HDA_STATES_SCSF 0x7

#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/

#define ICH6_HDA_GSTS_FSH_SHIFT (1)

#define GSTS(pThis) (HDA_REG(pThis, GSTS))

#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */

#define ICH6_HDA_INTCTL_GIE_SHIFT 31

#define ICH6_HDA_INTCTL_CIE_SHIFT 30

#define ICH6_HDA_INTCTL_S0_SHIFT (0)

#define ICH6_HDA_INTCTL_S1_SHIFT (1)

#define ICH6_HDA_INTCTL_S2_SHIFT (2)

#define ICH6_HDA_INTCTL_S3_SHIFT (3)

#define ICH6_HDA_INTCTL_S4_SHIFT (4)

#define ICH6_HDA_INTCTL_S5_SHIFT (5)

#define ICH6_HDA_INTCTL_S6_SHIFT (6)

#define ICH6_HDA_INTCTL_S7_SHIFT (7)

#define INTCTL(pThis) (HDA_REG((pThis), INTCTL))

#define INTCTL_GIE(pThis) (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))

#define INTCTL_CIE(pThis) (HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE))

#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))

#define INTCTL_SALL(pThis) (INTCTL((pThis)) & 0xFF)

#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */

#define SSYNC(pThis) (HDA_REG((pThis), SSYNC))

#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */

#define ICH6_HDA_INTSTS_GIS_SHIFT (31)

#define ICH6_HDA_INTSTS_CIS_SHIFT (30)

#define ICH6_HDA_INTSTS_S0_SHIFT (0)

#define ICH6_HDA_INTSTS_S1_SHIFT (1)

#define ICH6_HDA_INTSTS_S2_SHIFT (2)

#define ICH6_HDA_INTSTS_S3_SHIFT (3)

#define ICH6_HDA_INTSTS_S4_SHIFT (4)

#define ICH6_HDA_INTSTS_S5_SHIFT (5)

#define ICH6_HDA_INTSTS_S6_SHIFT (6)

#define ICH6_HDA_INTSTS_S7_SHIFT (7)

#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))

#define INTSTS(pThis) (HDA_REG((pThis), INTSTS))

#define INTSTS_GIS(pThis) (HDA_REG_FLAG_VALUE((pThis), INTSTS, GIS)

#define INTSTS_CIS(pThis) (HDA_REG_FLAG_VALUE((pThis), INTSTS, CIS)

#define INTSTS_SX(pThis, X) (HDA_REG_FLAG_VALUE(pThis), INTSTS, S##X)

#define INTSTS_SANY(pThis) (INTSTS((pThis)) & 0xFF)

#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */

#define CORBLBASE(pThis) (HDA_REG((pThis), CORBLBASE))

#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */

#define CORBUBASE(pThis) (HDA_REG((pThis), CORBUBASE))

#define ICH6_HDA_REG_CORBWP 15 /* 48 */

#define ICH6_HDA_REG_CORBRP 16 /* 4A */

#define ICH6_HDA_CORBRP_RST_SHIFT 15

#define ICH6_HDA_CORBRP_WP_SHIFT 0

#define ICH6_HDA_CORBRP_WP_MASK 0xFF

#define CORBRP(pThis) (HDA_REG(pThis, CORBRP))

#define CORBWP(pThis) (HDA_REG(pThis, CORBWP))

#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */

#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)

#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)

#define CORBCTL(pThis) (HDA_REG(pThis, CORBCTL))

#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */

#define CORBSTS(pThis) (HDA_REG(pThis, CORBSTS))

#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)

#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */

#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0

#define ICH6_HDA_CORBSIZE_SZ 0x3

#define CORBSIZE_SZ(pThis) (HDA_REG(pThis, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)

#define CORBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)

#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */

#define RIRLBASE(pThis) (HDA_REG((pThis), RIRLBASE))

#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */

#define RIRUBASE(pThis) (HDA_REG((pThis), RIRUBASE))

#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */

#define ICH6_HDA_RIRBWP_RST_SHIFT (15)

#define ICH6_HDA_RIRBWP_WP_MASK 0xFF

#define RIRBWP(pThis) (HDA_REG(pThis, RIRBWP))

#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */

#define RINTCNT(pThis) (HDA_REG((pThis), RINTCNT))

#define RINTCNT_N(pThis) (RINTCNT((pThis)) & 0xff)

#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */

#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)

#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)

#define ICH6_HDA_ROI_DMA_SHIFT (2)

#define RIRBCTL(pThis) (HDA_REG((pThis), RIRBCTL))

#define RIRBCTL_RIRB_RIC(pThis) (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))

#define RIRBCTL_RIRB_DMA(pThis) (HDA_REG_FLAG_VALUE((pThis), RIRBCTL, DMA)

#define RIRBCTL_ROI(pThis) (HDA_REG_FLAG_VALUE((pThis), RIRBCTL, ROI))

#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */

#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)

#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)

#define RIRBSTS(pThis) (HDA_REG(pThis, RIRBSTS))

#define RIRBSTS_RINTFL(pThis) (HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL))

#define RIRBSTS_RIRBOIS(pThis) (HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS))

#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */

#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0

#define ICH6_HDA_RIRBSIZE_SZ 0x3

#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)

#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)

#define ICH6_HDA_REG_IC 27 /* 0x60 */

#define IC(pThis) (HDA_REG(pThis, IC))

#define ICH6_HDA_REG_IR 28 /* 0x64 */

#define IR(pThis) (HDA_REG(pThis, IR))

#define ICH6_HDA_REG_IRS 29 /* 0x68 */

#define ICH6_HDA_IRS_ICB_SHIFT (0)

#define ICH6_HDA_IRS_IRV_SHIFT (1)

#define IRS(pThis) (HDA_REG(pThis, IRS))

#define IRS_ICB(pThis) (HDA_REG_FLAG_VALUE(pThis, IRS, ICB))

#define IRS_IRV(pThis) (HDA_REG_FLAG_VALUE(pThis, IRS, IRV))

#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */

#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))

#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */

#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))

#define DPBASE_ENABLED 1

#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)

#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)

#define HDA_STREAM_REG(pThis, name, num) (HDA_REG((pThis), N_(HDA_STREAM_REG_DEF(name, num))))

#define HDA_STREAM_REG2(pThis, name, sdnum) (HDA_REG_IND((pThis), ICH6_HDA_REG_SD0##name + (sdnum) * 10))

#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */

#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */

#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */

#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */

#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */

#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */

#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */

#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */

#define SD(func, num) SD##num##func

#define SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))

#define SDCTL_NUM(pThis, num) ((SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))

#define ICH6_HDA_SDCTL_NUM_MASK (0xF)

#define ICH6_HDA_SDCTL_NUM_SHIFT (20)

#define ICH6_HDA_SDCTL_DIR_SHIFT (19)

#define ICH6_HDA_SDCTL_TP_SHIFT (18)

#define ICH6_HDA_SDCTL_STRIPE_MASK (0x3)

#define ICH6_HDA_SDCTL_STRIPE_SHIFT (16)

#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)

#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)

#define ICH6_HDA_SDCTL_ICE_SHIFT (2)

#define ICH6_HDA_SDCTL_RUN_SHIFT (1)

#define ICH6_HDA_SDCTL_SRST_SHIFT (0)

#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */

#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */

#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */

#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */

#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */

#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */

#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */

#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */

#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))

#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)

#define ICH6_HDA_SDSTS_DE_SHIFT (4)

#define ICH6_HDA_SDSTS_FE_SHIFT (3)

#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)

#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */

#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */

#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */

#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */

#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */

#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */

#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */

#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */

#define SDLPIB(pThis, num) HDA_REG((pThis), SD(LPIB, num))

#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */

#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */

#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */

#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */

#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */

#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */

#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */

#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */

#define SDLCBL(pThis, num) HDA_REG((pThis), SD(CBL, num))

#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */

#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */

#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */

#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */

#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */

#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */

#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */

#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */

#define SDLVI(pThis, num) HDA_REG((pThis), SD(LVI, num))

#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */

#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */

#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */

#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */

#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */

#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */

#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */

#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */

#define HDA_SDFIFOW_8B (0x2)

#define HDA_SDFIFOW_16B (0x3)

#define HDA_SDFIFOW_32B (0x4)

#define SDFIFOW(pThis, num) HDA_REG((pThis), SD(FIFOW, num))

#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */

#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */

#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */

#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */

#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */

#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */

#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */

#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */

#define HDA_SDONFIFO_16B (0x0F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */

#define HDA_SDONFIFO_32B (0x1F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */

#define HDA_SDONFIFO_64B (0x3F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */

#define HDA_SDONFIFO_128B (0x7F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */

#define HDA_SDONFIFO_192B (0xBF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */

#define HDA_SDONFIFO_256B (0xFF) /* 20-, 24-bit Output Streams */

#define HDA_SDINFIFO_120B (0x77) /* 8-, 16-, 20-, 24-, 32-bit Input Streams */

#define HDA_SDINFIFO_160B (0x9F) /* 20-, 24-bit Input Streams Streams */

#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))

#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */

#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */

#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */

#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */

#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */

#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */

#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */

#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */

#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))

#define ICH6_HDA_SDFMT_BASE_RATE_SHIFT (14)

#define ICH6_HDA_SDFMT_MULT_SHIFT (11)

#define ICH6_HDA_SDFMT_MULT_MASK (0x7)

#define ICH6_HDA_SDFMT_DIV_SHIFT (8)

#define ICH6_HDA_SDFMT_DIV_MASK (0x7)

#define ICH6_HDA_SDFMT_BITS_SHIFT (4)

#define ICH6_HDA_SDFMT_BITS_MASK (0x7)

#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))

#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))

#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))

#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */

#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */

#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */

#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */

#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */

#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */

#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */

#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */

#define SDBDPL(pThis, num) HDA_REG((pThis), SD(BDPL, num))

#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */

#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */

#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */

#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */

#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */

#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */

#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */

#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */

#define SDBDPU(pThis, num) HDA_REG((pThis), SD(BDPU, num))

typedef struct HDABDLEDESC

{

uint64_t u64BdleCviAddr;

uint32_t u32BdleMaxCvi;

uint32_t u32BdleCvi;

uint32_t u32BdleCviLen;

uint32_t u32BdleCviPos;

bool fBdleCviIoc;

uint32_t cbUnderFifoW;

uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];

} HDABDLEDESC, *PHDABDLEDESC;

typedef struct HDASTREAMTRANSFERDESC

{

uint64_t u64BaseDMA;

uint32_t u32Ctl;

uint32_t *pu32Sts;

uint8_t u8Strm;

uint32_t *pu32Lpib;

uint32_t u32Cbl;

uint32_t u32Fifos;

} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;

typedef struct HDASTATE

{

/** The PCI device structure. */

PCIDevice PciDev;

/** Pointer to the device instance. */

PPDMDEVINSR3 pDevIns;

/** Pointer to the connector of the attached audio driver. */

PPDMIAUDIOCONNECTOR pDrv;

/** Pointer to the attached audio driver. */

PPDMIBASE pDrvBase;

/** The base interface for LUN\#0. */

PDMIBASE IBase;

RTGCPHYS MMIOBaseAddr;

uint32_t au32Regs[HDA_NREGS];

HDABDLEDESC StInBdle;

HDABDLEDESC StOutBdle;

HDABDLEDESC StMicBdle;

/** Interrupt on completion */

bool fCviIoc;

uint64_t u64CORBBase;

uint64_t u64RIRBBase;

uint64_t u64DPBase;

/** pointer to CORB buf */

uint32_t *pu32CorbBuf;

/** size in bytes of CORB buf */

uint32_t cbCorbBuf;

/** pointer on RIRB buf */

uint64_t *pu64RirbBuf;

/** size in bytes of RIRB buf */

uint32_t cbRirbBuf;

/** indicates if HDA in reset. */

bool fInReset;

/** The HDA codec state. */

HDACODEC Codec;

/** 1.2.3.4.5.6.7. - someone please tell me what I'm counting! - .8.9.10... */

uint8_t u8Counter;

uint64_t u64BaseTS;

} HDASTATE;

typedef HDASTATE *PHDASTATE;

#define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \

( AUDIO_FORMAT_SELECTOR(&(pThis)->Codec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )

#define OSD0FMT_TO_AUDIO_SELECTOR(pThis) \

( AUDIO_FORMAT_SELECTOR(&(pThis)->Codec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )

static FNPDMDEVRESET hdaReset;

static int hdaRegReadUnimplemented(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);

static int hdaRegWriteUnimplemented(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);

static int hdaRegReadGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);

static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);

static int hdaRegReadSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);

static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);

static int hdaRegReadGCAP(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);

static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);

static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);

static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);

static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);

static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);

static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);

static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);

static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);

static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);

static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);

static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);

static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);

static int hdaRegReadSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);

static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);

static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);

static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);

static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);

static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);

static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);

static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);

static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);

static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);

static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);

static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);

static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);

static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);

static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);

static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);

static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);

DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,

PHDASTREAMTRANSFERDESC pStreamDesc);

static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);

#ifdef LOG_ENABLED

static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);

#endif

static const struct HDAREGDESC

{

/** Register offset in the register space. */

uint32_t offset;

/** Size in bytes. Registers of size > 4 are in fact tables. */

uint32_t size;

/** Readable bits. */

uint32_t readable;

/** Writable bits. */

uint32_t writable;

/** Read callback. */

int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);

/** Write callback. */

int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);

/** Abbreviated name. */

const char *abbrev;

/** Full name. */

const char *name;

} g_aHdaRegMap[HDA_NREGS] =

{

/* offset size read mask write mask read callback write callback abbrev full name */

/*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/

{ 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },

{ 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },

{ 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },

{ 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },

{ 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },

{ 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },

{ 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },

{ 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },

{ 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },

{ 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },

{ 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },

{ 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },

/// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?

{ 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },

{ 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },

{ 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },

{ 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },

#ifdef OLD_REGISTER_TABLE

{ 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },

#else /** @todo 18.2.17 indicates that the 15th bit can be read as well as and written. hdaRegReadU8 is wrong, a special reader should be used. */

{ 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },

#endif

{ 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },

{ 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },

{ 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },

{ 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },

{ 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },

{ 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },

{ 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },

{ 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },

{ 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },

{ 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },

{ 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },

{ 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },

#ifdef OLD_REGISTER_TABLE

{ 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },

#else /* 18.2.30 as well as the table says 16-bit. Linux accesses it as a 16-bit register. */

{ 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },

#endif

{ 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },

{ 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },

{ 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },

{ 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },

{ 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },

{ 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },

{ 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },

{ 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD0FIFOW", "ISD0 FIFO Watermark" },

{ 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },

{ 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD0FMT" , "ISD0 Format" },

{ 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },

{ 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },

{ 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },

{ 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },

{ 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },

{ 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },

{ 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },

{ 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD1FIFOW", "ISD1 FIFO Watermark" },

{ 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },

{ 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD1FMT" , "ISD1 Format" },

{ 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },

{ 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },

{ 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },

{ 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },

{ 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },

{ 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },

{ 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },

{ 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD2FIFOW", "ISD2 FIFO Watermark" },

{ 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },

{ 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD2FMT" , "ISD2 Format" },

{ 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },

{ 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },

{ 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },

{ 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },

{ 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },

{ 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },

{ 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },

{ 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },

{ 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },

{ 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD3FMT" , "ISD3 Format" },

{ 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },

{ 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },

{ 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },

{ 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },

{ 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },

{ 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },

{ 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },

{ 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD0FIFOW", "OSD0 FIFO Watermark" },

{ 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD0FIFOS", "OSD0 FIFO Size" },

{ 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD0FMT" , "OSD0 Format" },

{ 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },

{ 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },

{ 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },

{ 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },

{ 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },

{ 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },

{ 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },

{ 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD1FIFOW", "OSD1 FIFO Watermark" },

{ 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD1FIFOS", "OSD1 FIFO Size" },

{ 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD1FMT" , "OSD1 Format" },

{ 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },

{ 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },

{ 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },

{ 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },

{ 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },

{ 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },

{ 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },

{ 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD2FIFOW", "OSD2 FIFO Watermark" },

{ 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD2FIFOS", "OSD2 FIFO Size" },

{ 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD2FMT" , "OSD2 Format" },

{ 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },

{ 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },

{ 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },

{ 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },

{ 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },

{ 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },

{ 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },

{ 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD3FIFOW", "OSD3 FIFO Watermark" },

{ 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD3FIFOS", "OSD3 FIFO Size" },

{ 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD3FMT" , "OSD3 Format" },

{ 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },

{ 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },

};

static const struct

{

/** The alias register offset. */

uint32_t offReg;

/** The register index. */

int idxAlias;

} g_aHdaRegAliases[] =

{

{ 0x2084, HDA_REG_IND_NAME(SD0LPIB) },

{ 0x20a4, HDA_REG_IND_NAME(SD1LPIB) },

{ 0x20c4, HDA_REG_IND_NAME(SD2LPIB) },

{ 0x20e4, HDA_REG_IND_NAME(SD3LPIB) },

{ 0x2104, HDA_REG_IND_NAME(SD4LPIB) },

{ 0x2124, HDA_REG_IND_NAME(SD5LPIB) },

{ 0x2144, HDA_REG_IND_NAME(SD6LPIB) },

{ 0x2164, HDA_REG_IND_NAME(SD7LPIB) },

};

static SSMFIELD const g_aHdaBDLEDescFields[] =

{

SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),

SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),

SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),

SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),

SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),

SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),

SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),

SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),

SSMFIELD_ENTRY_TERM()

};

static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =

{

SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),

SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),

SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),

SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),

SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),

SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),

SSMFIELD_ENTRY_PAD_HC_AUTO(3, 3),

SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),

SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),

SSMFIELD_ENTRY_TERM()

};

static uint32_t const g_afMasks[5] =

{

UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)

};

DECLINLINE(void) hdaUpdatePosBuf(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)

{

if (pThis->u64DPBase & DPBASE_ENABLED)

PDMDevHlpPCIPhysWrite(pThis->pDevIns,

(pThis->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm * 8,

pStreamDesc->pu32Lpib, sizeof(uint32_t));

}

DECLINLINE(uint32_t) hdaFifoWToSz(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)

{

#if 0

switch(HDA_STREAM_REG2(pThis, FIFOW, pStreamDesc->u8Strm))

{

case HDA_SDFIFOW_8B: return 8;

case HDA_SDFIFOW_16B: return 16;

case HDA_SDFIFOW_32B: return 32;

default:

AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pThis, pStreamDesc->u8Strm), pStreamDesc->u8Strm));

}

#endif

return 0;

}

static int hdaProcessInterrupt(PHDASTATE pThis)

{

#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \

( INTCTL_SX((pThis), num) \

&& (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))

bool fIrq = false;

if ( INTCTL_CIE(pThis)

&& ( RIRBSTS_RINTFL(pThis)

|| RIRBSTS_RIRBOIS(pThis)

|| (STATESTS(pThis) & WAKEEN(pThis))))

fIrq = true;

if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)

|| IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))

fIrq = true;

if (INTCTL_GIE(pThis))

{

Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));

PDMDevHlpPCISetIrq(pThis->pDevIns, 0 , fIrq);

}

return VINF_SUCCESS;

}

static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)

{

/*

if (offReg >= g_aHdaRegAliases[0].offReg)

{

for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)

if (offReg == g_aHdaRegAliases[i].offReg)

return g_aHdaRegAliases[i].idxAlias;

Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);

return -1;

}

/*

int idxEnd = RT_ELEMENTS(g_aHdaRegMap);

int idxLow = 0;

for (;;)

{

int idxMiddle = idxLow + (idxEnd - idxLow) / 2;

if (offReg < g_aHdaRegMap[idxMiddle].offset)

{

if (idxLow == idxMiddle)

break;

idxEnd = idxMiddle;

}

else if (offReg > g_aHdaRegMap[idxMiddle].offset)

{

idxLow = idxMiddle + 1;

if (idxLow >= idxEnd)

break;

}

else

return idxMiddle;

}

#ifdef RT_STRICT

for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)

Assert(g_aHdaRegMap[i].offset != offReg);

#endif

return -1;

}

static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)

{

/*

if (offReg >= g_aHdaRegAliases[0].offReg)

{

for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)

{

uint32_t off = offReg - g_aHdaRegAliases[i].offReg;

if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)

return g_aHdaRegAliases[i].idxAlias;

}

Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);

return -1;

}

/*

int idxEnd = RT_ELEMENTS(g_aHdaRegMap);

int idxLow = 0;

for (;;)

{

int idxMiddle = idxLow + (idxEnd - idxLow) / 2;

if (offReg < g_aHdaRegMap[idxMiddle].offset)

{

if (idxLow == idxMiddle)

break;

idxEnd = idxMiddle;

}

else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)

{

idxLow = idxMiddle + 1;

if (idxLow >= idxEnd)

break;

}

else

return idxMiddle;

}

#ifdef RT_STRICT

for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)

Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);

#endif

return -1;

}

static int hdaCmdSync(PHDASTATE pThis, bool fLocal)

{

int rc = VINF_SUCCESS;

if (fLocal)

{

Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));

rc = PDMDevHlpPhysRead(pThis->pDevIns, pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);

if (RT_FAILURE(rc))

AssertRCReturn(rc, rc);

#ifdef DEBUG_CMD_BUFFER

uint8_t i = 0;

do

{

Log(("hda: corb%02x: ", i));

uint8_t j = 0;

do

{

const char *prefix;

if ((i + j) == CORBRP(pThis))

prefix = "[R]";

else if ((i + j) == CORBWP(pThis))

prefix = "[W]";

else

prefix = " "; /* three spaces */

Log(("%s%08x", prefix, pThis->pu32CorbBuf[i + j]));

j++;

} while (j < 8);

Log(("\n"));

i += 8;

} while(i != 0);

#endif

}

else

{

Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));

rc = PDMDevHlpPCIPhysWrite(pThis->pDevIns, pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);

if (RT_FAILURE(rc))

AssertRCReturn(rc, rc);

#ifdef DEBUG_CMD_BUFFER

uint8_t i = 0;

do {

Log(("hda: rirb%02x: ", i));

uint8_t j = 0;

do {

const char *prefix;

if ((i + j) == RIRBWP(pThis))

prefix = "[W]";

else

prefix = " ";

Log((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));

} while (++j < 8);

Log(("\n"));

i += 8;

} while (i != 0);

#endif

}

return rc;

}

static int hdaCORBCmdProcess(PHDASTATE pThis)

{

int rc;

uint8_t corbRp;

uint8_t corbWp;

uint8_t rirbWp;

PFNHDACODECVERBPROCESSOR pfn = (PFNHDACODECVERBPROCESSOR)NULL;

rc = hdaCmdSync(pThis, true);

if (RT_FAILURE(rc))

AssertRCReturn(rc, rc);

corbRp = CORBRP(pThis);

corbWp = CORBWP(pThis);

rirbWp = RIRBWP(pThis);

Assert((corbWp != corbRp));

Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pThis), CORBWP(pThis), RIRBWP(pThis)));

while (corbRp != corbWp)

{

uint32_t cmd;

uint64_t resp;

pfn = NULL;

corbRp++;

cmd = pThis->pu32CorbBuf[corbRp];

rc = pThis->Codec.pfnLookup(&pThis->Codec, cmd, &pfn);

if (RT_FAILURE(rc))

AssertRCReturn(rc, rc);

Assert(pfn);

(rirbWp)++;

if (RT_LIKELY(pfn))

rc = pfn(&pThis->Codec, cmd, &resp);

else

rc = VERR_INVALID_FUNCTION;

if (RT_FAILURE(rc))

AssertRCReturn(rc, rc);

Log(("hda: verb:%08x->%016lx\n", cmd, resp));

if ( (resp & CODEC_RESPONSE_UNSOLICITED)

&& !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))

{

Log(("hda: unexpected unsolicited response.\n"));

pThis->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;

return rc;

}

pThis->pu64RirbBuf[rirbWp] = resp;

pThis->u8Counter++;

if (pThis->u8Counter == RINTCNT_N(pThis))

break;

}

pThis->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;

pThis->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;

rc = hdaCmdSync(pThis, false);

Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pThis), CORBWP(pThis), RIRBWP(pThis)));

if (RIRBCTL_RIRB_RIC(pThis))

{

RIRBSTS((pThis)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);

pThis->u8Counter = 0;

rc = hdaProcessInterrupt(pThis);

}

if (RT_FAILURE(rc))

AssertRCReturn(rc, rc);

return rc;

}

static void hdaStreamReset(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)

{

Log(("hda: reset of stream (%d) started\n", u8Strm));

Assert(( pThis

&& pBdle

&& pStreamDesc

&& u8Strm <= 7));

memset(pBdle, 0, sizeof(HDABDLEDESC));

*pStreamDesc->pu32Lpib = 0;

*pStreamDesc->pu32Sts = 0;

/* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20

HDA_STREAM_REG2(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG2(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));

/* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */

HDA_STREAM_REG2(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;

HDA_STREAM_REG2(pThis, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;

HDA_STREAM_REG2(pThis, CBL, u8Strm) = 0;

HDA_STREAM_REG2(pThis, LVI, u8Strm) = 0;

HDA_STREAM_REG2(pThis, FMT, u8Strm) = 0;

HDA_STREAM_REG2(pThis, BDPU, u8Strm) = 0;

HDA_STREAM_REG2(pThis, BDPL, u8Strm) = 0;

Log(("hda: reset of stream (%d) finished\n", u8Strm));

}

static int hdaRegReadUnimplemented(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)

{

*pu32Value = 0;

return VINF_SUCCESS;

}

static int hdaRegWriteUnimplemented(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

return VINF_SUCCESS;

}

static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)

{

Assert(((pThis->au32Regs[iReg] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);

return hdaRegReadU32(pThis, iReg, pu32Value);

}

static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

Assert((u32Value & 0xffffff00) == 0);

return hdaRegWriteU32(pThis, iReg, u32Value);

}

static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)

{

Assert(((pThis->au32Regs[iReg] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);

return hdaRegReadU32(pThis, iReg, pu32Value);

}

static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

Assert((u32Value & 0xffff0000) == 0);

return hdaRegWriteU32(pThis, iReg, u32Value);

}

static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)

{

Assert(((pThis->au32Regs[iReg] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);

return hdaRegReadU32(pThis, iReg, pu32Value);

}

static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

Assert((u32Value & 0xff000000) == 0);

return hdaRegWriteU32(pThis, iReg, u32Value);

}

static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)

{

*pu32Value = pThis->au32Regs[iReg] & g_aHdaRegMap[iReg].readable;

return VINF_SUCCESS;

}

static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

pThis->au32Regs[iReg] = (u32Value & g_aHdaRegMap[iReg].writable)

| (pThis->au32Regs[iReg] & ~g_aHdaRegMap[iReg].writable);

return VINF_SUCCESS;

}

static int hdaRegReadGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)

{

return hdaRegReadU32(pThis, iReg, pu32Value);

}

static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))

{

/* exit reset state */

GCTL(pThis) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);

pThis->fInReset = false;

}

else

{

/* enter reset state*/

if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)

|| HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))

{

Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",

HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",

HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));

}

hdaReset(pThis->pDevIns);

GCTL(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);

pThis->fInReset = true;

}

if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))

{

/* Flush: GSTS:1 set, see 6.2.6*/

GSTS(pThis) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */

/* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/

}

return VINF_SUCCESS;

}

static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

uint32_t v = pThis->au32Regs[iReg];

uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;

pThis->au32Regs[iReg] &= ~(v & nv); /* write of 1 clears corresponding bit */

return VINF_SUCCESS;

}

static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)

{

uint32_t v = 0;

if ( RIRBSTS_RIRBOIS(pThis)

|| RIRBSTS_RINTFL(pThis)

|| HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)

|| STATESTS(pThis))

v |= RT_BIT(30);

#define HDA_IS_STREAM_EVENT(pThis, stream) \

( (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \

|| (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \

|| (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))

#define MARK_STREAM(pThis, stream, v) do { (v) |= HDA_IS_STREAM_EVENT((pThis),stream) ? RT_BIT((stream)) : 0; } while(0)

MARK_STREAM(pThis, 0, v);

MARK_STREAM(pThis, 1, v);

MARK_STREAM(pThis, 2, v);

MARK_STREAM(pThis, 3, v);

MARK_STREAM(pThis, 4, v);

MARK_STREAM(pThis, 5, v);

MARK_STREAM(pThis, 6, v);

MARK_STREAM(pThis, 7, v);

v |= v ? RT_BIT(31) : 0;

*pu32Value = v;

return VINF_SUCCESS;

}

static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)

{

/* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */

*pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->pDevIns)

- pThis->u64BaseTS, 24, 1000);

return VINF_SUCCESS;

}

static int hdaRegReadGCAP(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)

{

return hdaRegReadU16(pThis, iReg, pu32Value);

}

static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))

CORBRP(pThis) = 0;

#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO

else

return hdaRegWriteU8(pThis, iReg, u32Value);

#endif

return VINF_SUCCESS;

}

static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

int rc = hdaRegWriteU8(pThis, iReg, u32Value);

AssertRC(rc);

if ( CORBWP(pThis) != CORBRP(pThis)

&& HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)

return hdaCORBCmdProcess(pThis);

return rc;

}

static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

uint32_t v = CORBSTS(pThis);

CORBSTS(pThis) &= ~(v & u32Value);

return VINF_SUCCESS;

}

static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

int rc;

rc = hdaRegWriteU16(pThis, iReg, u32Value);

if (RT_FAILURE(rc))

AssertRCReturn(rc, rc);

if (CORBWP(pThis) == CORBRP(pThis))

return VINF_SUCCESS;

if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))

return VINF_SUCCESS;

rc = hdaCORBCmdProcess(pThis);

return rc;

}

static int hdaRegReadSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)

{

return hdaRegReadU24(pThis, iReg, pu32Value);

}

static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));

bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));

bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));

bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));

if (fInReset)

{

/*

Assert((!fReset));

Log(("hda: guest initiated exit of stream reset.\n"));

}

else if (fReset)

{

/*

uint8_t u8Strm = 0;

PHDABDLEDESC pBdle = NULL;

HDASTREAMTRANSFERDESC StreamDesc;

Assert((!fInRun && !fRun));

switch (iReg)

{

case ICH6_HDA_REG_SD0CTL:

u8Strm = 0;

pBdle = &pThis->StInBdle;

break;

case ICH6_HDA_REG_SD4CTL:

u8Strm = 4;

pBdle = &pThis->StOutBdle;

break;

default:

Log(("hda: changing SRST bit on non-attached stream\n"));

return hdaRegWriteU24(pThis, iReg, u32Value);

}

Log(("hda: guest initiated enter to stream reset.\n"));

hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);

hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);

}

else

{

/* we enter here to change DMA states only */

if ( (fInRun && !fRun)

|| (fRun && !fInRun))

{

Assert((!fReset && !fInReset));

switch (iReg)

{

case ICH6_HDA_REG_SD0CTL:

AUD_set_active_in(pThis->Codec.SwVoiceIn, fRun);

break;

case ICH6_HDA_REG_SD4CTL:

AUD_set_active_out(pThis->Codec.SwVoiceOut, fRun);

break;

default:

Log(("hda: changing RUN bit on non-attached stream\n"));

break;

}

}

}

return hdaRegWriteU24(pThis, iReg, u32Value);

}

static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

uint32_t v = HDA_REG_IND(pThis, iReg);

v &= ~(u32Value & v);

HDA_REG_IND(pThis, iReg) = v;

hdaProcessInterrupt(pThis);

return VINF_SUCCESS;

}

static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

int rc = hdaRegWriteU32(pThis, iReg, u32Value);

if (RT_FAILURE(rc))

AssertRCReturn(rc, VINF_SUCCESS);

return rc;

}

static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

switch (u32Value)

{

case HDA_SDFIFOW_8B:

case HDA_SDFIFOW_16B:

case HDA_SDFIFOW_32B:

return hdaRegWriteU16(pThis, iReg, u32Value);

default:

Log(("hda: Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));

return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);

}

return VINF_SUCCESS;

}

static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

switch (iReg)

{

/* SDInFIFOS is RO, n=0-3 */

case ICH6_HDA_REG_SD0FIFOS:

case ICH6_HDA_REG_SD1FIFOS:

case ICH6_HDA_REG_SD2FIFOS:

case ICH6_HDA_REG_SD3FIFOS:

Log(("hda: Guest tries change value of FIFO size of Input Stream\n"));

return VINF_SUCCESS;

case ICH6_HDA_REG_SD4FIFOS:

case ICH6_HDA_REG_SD5FIFOS:

case ICH6_HDA_REG_SD6FIFOS:

case ICH6_HDA_REG_SD7FIFOS:

switch(u32Value)

{

case HDA_SDONFIFO_16B:

case HDA_SDONFIFO_32B:

case HDA_SDONFIFO_64B:

case HDA_SDONFIFO_128B:

case HDA_SDONFIFO_192B:

return hdaRegWriteU16(pThis, iReg, u32Value);

case HDA_SDONFIFO_256B:

Log(("hda: 256-bit is unsupported, HDA is switched into 192-bit mode\n"));

default:

return hdaRegWriteU16(pThis, iReg, HDA_SDONFIFO_192B);

}

return VINF_SUCCESS;

default:

AssertMsgFailed(("Something weird happened with register lookup routine"));

}

return VINF_SUCCESS;

}

static void hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pAudSetting)

{

Assert((pAudSetting));

#define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))

uint32_t u32Hz = (u32SdFmt & ICH6_HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;

uint32_t u32HzMult = 1;

uint32_t u32HzDiv = 1;

switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_MULT_MASK, ICH6_HDA_SDFMT_MULT_SHIFT))

{

case 0: u32HzMult = 1; break;

case 1: u32HzMult = 2; break;

case 2: u32HzMult = 3; break;

case 3: u32HzMult = 4; break;

default:

Log(("hda: unsupported multiplier %x\n", u32SdFmt));

}

switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_DIV_MASK, ICH6_HDA_SDFMT_DIV_SHIFT))

{

case 0: u32HzDiv = 1; break;

case 1: u32HzDiv = 2; break;

case 2: u32HzDiv = 3; break;

case 3: u32HzDiv = 4; break;

case 4: u32HzDiv = 5; break;

case 5: u32HzDiv = 6; break;

case 6: u32HzDiv = 7; break;

case 7: u32HzDiv = 8; break;

}

pAudSetting->freq = u32Hz * u32HzMult / u32HzDiv;

switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_BITS_MASK, ICH6_HDA_SDFMT_BITS_SHIFT))

{

case 0:

Log(("hda: %s requested 8-bit\n", __FUNCTION__));

pAudSetting->fmt = AUD_FMT_S8;

break;

case 1:

Log(("hda: %s requested 16-bit\n", __FUNCTION__));

pAudSetting->fmt = AUD_FMT_S16;

break;

case 2:

Log(("hda: %s requested 20-bit\n", __FUNCTION__));

break;

case 3:

Log(("hda: %s requested 24-bit\n", __FUNCTION__));

break;

case 4:

Log(("hda: %s requested 32-bit\n", __FUNCTION__));

pAudSetting->fmt = AUD_FMT_S32;

break;

default:

AssertMsgFailed(("Unsupported"));

}

pAudSetting->nchannels = (u32SdFmt & 0xf) + 1;

pAudSetting->fmt = AUD_FMT_S16;

pAudSetting->endianness = 0;

#undef EXTRACT_VALUE

}

static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

#ifdef VBOX_WITH_HDA_CODEC_EMU

/** @todo a bit more investigation is required here. */

int rc = 0;

audsettings_t as;

/* no reason to reopen voice with same settings */

if (u32Value == HDA_REG_IND(pThis, iReg))

return VINF_SUCCESS;

hdaSdFmtToAudSettings(u32Value, &as);

switch (iReg)

{

case ICH6_HDA_REG_SD0FMT:

rc = hdaCodecOpenVoice(&pThis->Codec, PI_INDEX, &as);

break;

case ICH6_HDA_REG_SD4FMT:

rc = hdaCodecOpenVoice(&pThis->Codec, PO_INDEX, &as);

break;

default:

Log(("HDA: attempt to change format on %d\n", iReg));

rc = 0;

}

return hdaRegWriteU16(pThis, iReg, u32Value);

#else

return hdaRegWriteU16(pThis, iReg, u32Value);

#endif

}

static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

int rc = hdaRegWriteU32(pThis, iReg, u32Value);

if (RT_FAILURE(rc))

AssertRCReturn(rc, VINF_SUCCESS);

return rc;

}

static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

int rc = hdaRegWriteU32(pThis, iReg, u32Value);

if (RT_FAILURE(rc))

AssertRCReturn(rc, VINF_SUCCESS);

return rc;

}

static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)

{

int rc = VINF_SUCCESS;

/* regarding 3.4.3 we should mark IRS as busy in case CORB is active */

if ( CORBWP(pThis) != CORBRP(pThis)

|| HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))

IRS(pThis) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */

rc = hdaRegReadU32(pThis, iReg, pu32Value);

return rc;

}

static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

int rc = VINF_SUCCESS;

PFNHDACODECVERBPROCESSOR pfn = NULL;

uint64_t resp;

/*

if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)

&& !IRS_ICB(pThis))

{

uint32_t cmd = IC(pThis);

if (CORBWP(pThis) != CORBRP(pThis))

{

/*

LogRel(("hda: guest attempted process immediate verb (%x) with active CORB\n", cmd));

return rc;

}

IRS(pThis) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */

Log(("hda: IC:%x\n", cmd));

rc = pThis->Codec.pfnLookup(&pThis->Codec, cmd, &pfn);

if (RT_FAILURE(rc))

AssertRCReturn(rc, rc);

rc = pfn(&pThis->Codec, cmd, &resp);

if (RT_FAILURE(rc))

AssertRCReturn(rc, rc);

IR(pThis) = (uint32_t)resp;

Log(("hda: IR:%x\n", IR(pThis)));

IRS(pThis) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */

IRS(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */

return rc;

}

/*

if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)

&& IRS_IRV(pThis))

IRS(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);

return rc;

}

static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))

{

RIRBWP(pThis) = 0;

}

/* The remaining bits are O, see 6.2.22 */

return VINF_SUCCESS;

}

static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

int rc = hdaRegWriteU32(pThis, iReg, u32Value);

if (RT_FAILURE(rc))

AssertRCReturn(rc, rc);

switch(iReg)

{

case ICH6_HDA_REG_CORBLBASE:

pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);

pThis->u64CORBBase |= pThis->au32Regs[iReg];

break;

case ICH6_HDA_REG_CORBUBASE:

pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);

pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iReg] << 32);

break;

case ICH6_HDA_REG_RIRLBASE:

pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);

pThis->u64RIRBBase |= pThis->au32Regs[iReg];

break;

case ICH6_HDA_REG_RIRUBASE:

pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);

pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iReg] << 32);

break;

case ICH6_HDA_REG_DPLBASE:

/** @todo: first bit has special meaning */

pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);

pThis->u64DPBase |= pThis->au32Regs[iReg];

break;

case ICH6_HDA_REG_DPUBASE:

pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);

pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iReg] << 32);

break;

default:

AssertMsgFailed(("Invalid index"));

}

Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));

return rc;

}

static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)

{

uint8_t v = RIRBSTS(pThis);

RIRBSTS(pThis) &= ~(v & u32Value);

return hdaProcessInterrupt(pThis);

}

#ifdef LOG_ENABLED

static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)

{

#if 0

uint64_t addr;

uint32_t len;

uint32_t ioc;

uint8_t bdle[16];

uint32_t counter;

uint32_t i;

uint32_t sum = 0;

Assert(pBdle && pBdle->u32BdleMaxCvi);

for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)

{

PDMDevHlpPhysRead(pThis->pDevIns, u64BaseDMA + i*16, bdle, 16);

addr = *(uint64_t *)bdle;

len = *(uint32_t *)&bdle[8];

ioc = *(uint32_t *)&bdle[12];

Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));

sum += len;

}

Log(("hda: sum: %d\n", sum));

for (i = 0; i < 8; ++i)

{

PDMDevHlpPhysRead(pThis->pDevIns, (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));

Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pThis, 4) || i == SDCTL_NUM(pThis, 0)? "[C]": " ",

i , counter));

}

#endif

}

#endif

static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)

{

uint8_t bdle[16];

Assert(( pStreamDesc->u64BaseDMA

&& pBdle

&& pBdle->u32BdleMaxCvi));

PDMDevHlpPhysRead(pThis->pDevIns, pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);

pBdle->u64BdleCviAddr = *(uint64_t *)bdle;

pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];

pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;

#ifdef LOG_ENABLED

dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);

#endif

}

DECLINLINE(uint32_t) hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,

uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)

{

uint32_t cb2Copy;

/*

Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */

cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;

/*

cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);

Assert((u32SoundBackendBufferBytesAvail > 0));

/* sanity check to avoid overriding the backend audio buffer */

cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);

cb2Copy = RT_MIN(cb2Copy, u32CblLimit);

if (cb2Copy <= pBdle->cbUnderFifoW)

return 0;

cb2Copy -= pBdle->cbUnderFifoW; /* forcibly reserve the amount of unreported bytes to copy */

return cb2Copy;

}

DECLINLINE(void) hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,

uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)

{

Log(("hda:hdaBackendWriteTransferReported: cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",

cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));

Assert((cbCopied));

Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));

/* Assertion!!! Fewer than cbUnderFifoW bytes were copied.

Assert((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy)); /* we assume that we write the entire buffer including unreported bytes */

if ( pBdle->cbUnderFifoW

&& pBdle->cbUnderFifoW <= cbCopied)

Log(("hda:hdaBackendWriteTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));

pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);

Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Incorrect assumption */

/* We always increment the position of DMA buffer counter because we're always reading into an intermediate buffer */

pBdle->u32BdleCviPos += cbArranged2Copy;

Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */

/* We report all bytes (including previously unreported bytes) */

*pu32DMACursor += cbCopied;

/* Decrease the backend counter by the number of bytes we copied to the backend */

*pu32BackendBufferCapacity -= cbCopied;

Log(("hda:hdaBackendWriteTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",

pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));

}

DECLINLINE(void) hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,

uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)

{

Assert((cbCopied, cbArranged2Copy));

*pu32BackendBufferCapacity -= cbCopied;

pBdle->u32BdleCviPos += cbCopied;

Log(("hda:hdaBackendReadTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));

*pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;

pBdle->cbUnderFifoW = 0;

Log(("hda:hdaBackendReadTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",

pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));

}

DECLINLINE(void) hdaBackendTransferUnreported(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,

uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)

{

Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));

pBdle->u32BdleCviPos += cbCopied;

pBdle->cbUnderFifoW += cbCopied;

/* In case of a read transaction we're always copying from the backend buffer */

if (pu32BackendBufferCapacity)

*pu32BackendBufferCapacity -= cbCopied;

Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));

Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pThis, pStreamDesc)));

}

DECLINLINE(bool) hdaIsTransferCountersOverlapped(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)

{

bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl

|| pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);

Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));

if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)

*pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;

hdaUpdatePosBuf(pThis, pStreamDesc);

/* don't touch BdleCvi counter on uninitialized descriptor */

if ( pBdle->u32BdleCviPos

&& pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)

{

pBdle->u32BdleCviPos = 0;

pBdle->u32BdleCvi++;

if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)

pBdle->u32BdleCvi = 0;

}

return fOnBufferEdge;

}

DECLINLINE(void) hdaStreamCounterUpdate(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,

uint32_t cbInc)

{

/*

if (!pBdle->cbUnderFifoW)

{

*pStreamDesc->pu32Lpib += cbInc;

/*

Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));

hdaUpdatePosBuf(pThis, pStreamDesc);

}

}

static bool hdaDoNextTransferCycle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)

{

bool fDoNextTransferLoop = true;

if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen

|| *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)

{

if ( !pBdle->cbUnderFifoW

&& pBdle->fBdleCviIoc)

{

/**

*pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);

/*

if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))

hdaProcessInterrupt(pThis);

}

fDoNextTransferLoop = false;

}

return fDoNextTransferLoop;

}

static uint32_t hdaReadAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)

{

PHDABDLEDESC pBdle = &pThis->StInBdle;

uint32_t cbTransferred = 0;

uint32_t cb2Copy = 0;

uint32_t cbBackendCopy = 0;

Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));

cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);

if (!cb2Copy)

/* if we enter here we can't report "unreported bits" */

*fStop = true;

else

{

/*

cbBackendCopy = AUD_read(pThis->Codec.SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);

/*

PDMDevHlpPCIPhysWrite(pThis->pDevIns, pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);

/* Don't see any reason why cb2Copy would differ from cbBackendCopy */

Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */

if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pThis, 0))

hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);

else

{

hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);

*fStop = true;

}

}

Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));

Log(("hda:ra: CVI(pos:%d, len:%d) cbTransferred: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));

return cbTransferred;

}

static uint32_t hdaWriteAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)

{

PHDABDLEDESC pBdle = &pThis->StOutBdle;

uint32_t cbTransferred = 0;

uint32_t cb2Copy = 0; /* local byte counter (on local buffer) */

uint32_t cbBackendCopy = 0; /* local byte counter, how many bytes copied to backend */

Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));

cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);

/*

if (!cb2Copy)

*fStop = true;

else

{

PDMDevHlpPhysRead(pThis->pDevIns, pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);

/*

if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pThis, pStreamDesc))

{

/*

cbBackendCopy = AUD_write (pThis->Codec.SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);

hdaBackendWriteTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);

}

else

{

/* Not enough bytes to be processed and reported, we'll try our luck next time around */

hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cb2Copy, NULL);

*fStop = true;

}

}

Assert(cbTransferred <= SDFIFOS(pThis, 4) + 1);

Log(("hda:wa: CVI(pos:%d, len:%d, cbTransferred:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));

return cbTransferred;

}

DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)

{

PHDASTATE pThis = (PHDASTATE)pCodec->pvHDAState;

NOREF(pThis);

return VINF_SUCCESS;

}

DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,