DevIchHda.cpp revision 5f80794f0fac6c6ae43bf4d2baaef60babb2a7c7
/* $Id$ */
/** @file
* DevIchHda - VBox ICH Intel HD Audio Controller.
*
* Implemented against the specifications found in "High Definition Audio
* Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
* HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
*/
/*
* Copyright (C) 2006-2013 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_DEV_AUDIO
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
#endif
#include <iprt/asm-math.h>
#ifdef IN_RING3
#endif
#include "VBoxDD.h"
#ifndef VBOX_WITH_PDM_AUDIO_DRIVER
extern "C" {
#include "audio.h"
}
#endif
#include "DevIchHdaCodec.h"
/*******************************************************************************
* Defined Constants And Macros *
*******************************************************************************/
//#define HDA_AS_PCI_EXPRESS
#define VBOX_WITH_INTEL_HDA
#if defined(VBOX_WITH_HP_HDA)
/* HP Pavilion dv4t-1300 */
# define HDA_PCI_VENDOR_ID 0x103c
# define HDA_PCI_DEVICE_ID 0x30f7
#elif defined(VBOX_WITH_INTEL_HDA)
/* Intel HDA controller */
# define HDA_PCI_VENDOR_ID 0x8086
# define HDA_PCI_DEVICE_ID 0x2668
#elif defined(VBOX_WITH_NVIDIA_HDA)
/* nVidia HDA controller */
# define HDA_PCI_VENDOR_ID 0x10de
# define HDA_PCI_DEVICE_ID 0x0ac0
#else
#endif
/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
* updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
* is read only except for bit 15 like the HDA spec states.
*
* Btw. the CORBRPRST implementation is incomplete according to both docs (sw
* writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
#define HDA_NREGS 114
#define HDA_NREGS_SAVED 112
/**
* NB: Register values stored in memory (au32Regs[]) are indexed through
* the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
* register descriptors in g_aHdaRegMap[] are indexed through the
* HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
*
* The au32Regs[] layout is kept unchanged for saved state
* compatibility. */
/* Registers */
#define HDA_REG_IND_NAME(x) HDA_REG_##x
#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
#define HDA_RMX_GCAP 0
/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
* oss (15:12) - number of output streams supported
* iss (11:8) - number of input streams supported
* bss (7:3) - number of bidirectional streams supported
* bds (2:1) - number of serial data out signals supported
* b64sup (0) - 64 bit addressing supported.
*/
| ((b64sup) & 1))
#define HDA_RMX_VMIN 1
#define HDA_RMX_VMAJ 2
#define HDA_RMX_OUTPAY 3
#define HDA_RMX_INPAY 4
#define HDA_RMX_GCTL 5
#define HDA_GCTL_RST_SHIFT 0
#define HDA_GCTL_FSH_SHIFT 1
#define HDA_GCTL_UR_SHIFT 8
#define HDA_RMX_WAKEEN 6
#define HDA_RMX_STATESTS 7
#define HDA_STATES_SCSF 0x7
#define HDA_RMX_GSTS 8
#define HDA_GSTS_FSH_SHIFT 1
#define HDA_RMX_OUTSTRMPAY 112
#define HDA_RMX_INSTRMPAY 113
#define HDA_RMX_INTCTL 9
#define HDA_INTCTL_GIE_SHIFT 31
#define HDA_INTCTL_CIE_SHIFT 30
#define HDA_INTCTL_S0_SHIFT 0
#define HDA_INTCTL_S1_SHIFT 1
#define HDA_INTCTL_S2_SHIFT 2
#define HDA_INTCTL_S3_SHIFT 3
#define HDA_INTCTL_S4_SHIFT 4
#define HDA_INTCTL_S5_SHIFT 5
#define HDA_INTCTL_S6_SHIFT 6
#define HDA_INTCTL_S7_SHIFT 7
#define HDA_RMX_INTSTS 10
#define HDA_INTSTS_GIS_SHIFT 31
#define HDA_INTSTS_CIS_SHIFT 30
#define HDA_INTSTS_S0_SHIFT 0
#define HDA_INTSTS_S1_SHIFT 1
#define HDA_INTSTS_S2_SHIFT 2
#define HDA_INTSTS_S3_SHIFT 3
#define HDA_INTSTS_S4_SHIFT 4
#define HDA_INTSTS_S5_SHIFT 5
#define HDA_INTSTS_S6_SHIFT 6
#define HDA_INTSTS_S7_SHIFT 7
#define HDA_RMX_WALCLK /* Not defined! */
/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
* the datasheet.
*/
#define HDA_RMX_SSYNC 12
#define HDA_RMX_CORBLBASE 13
#define HDA_RMX_CORBUBASE 14
#define HDA_RMX_CORBWP 15
#define HDA_RMX_CORBRP 16
#define HDA_CORBRP_RST_SHIFT 15
#define HDA_CORBRP_WP_SHIFT 0
#define HDA_CORBRP_WP_MASK 0xFF
#define HDA_RMX_CORBCTL 17
#define HDA_CORBCTL_DMA_SHIFT 1
#define HDA_CORBCTL_CMEIE_SHIFT 0
#define HDA_RMX_CORBSTS 18
#define HDA_CORBSTS_CMEI_SHIFT 0
#define HDA_RMX_CORBSIZE 19
#define HDA_CORBSIZE_SZ_CAP 0xF0
#define HDA_CORBSIZE_SZ 0x3
/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
#define HDA_RMX_RIRBLBASE 20
#define HDA_RMX_RIRBUBASE 21
#define HDA_RMX_RIRBWP 22
#define HDA_RIRBWP_RST_SHIFT 15
#define HDA_RIRBWP_WP_MASK 0xFF
#define HDA_RMX_RINTCNT 23
#define HDA_RMX_RIRBCTL 24
#define HDA_RIRBCTL_RIC_SHIFT 0
#define HDA_RIRBCTL_DMA_SHIFT 1
#define HDA_ROI_DMA_SHIFT 2
#define HDA_RMX_RIRBSTS 25
#define HDA_RIRBSTS_RINTFL_SHIFT 0
#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
#define HDA_RMX_RIRBSIZE 26
#define HDA_RIRBSIZE_SZ_CAP 0xF0
#define HDA_RIRBSIZE_SZ 0x3
#define HDA_RMX_IC 27
#define HDA_RMX_IR 28
#define HDA_RMX_IRS 29
#define HDA_IRS_ICB_SHIFT 0
#define HDA_IRS_IRV_SHIFT 1
#define HDA_RMX_DPLBASE 30
#define HDA_RMX_DPUBASE 31
#define DPBASE_ENABLED 1
/* Note: sdnum here _MUST_ be stream reg number [0,7] */
#define HDA_RMX_SD0CTL 32
#define SDCTL_NUM(pThis, num) ((SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
#define HDA_SDCTL_NUM_MASK 0xF
#define HDA_SDCTL_NUM_SHIFT 20
#define HDA_SDCTL_DIR_SHIFT 19
#define HDA_SDCTL_TP_SHIFT 18
#define HDA_SDCTL_STRIPE_MASK 0x3
#define HDA_SDCTL_STRIPE_SHIFT 16
#define HDA_SDCTL_DEIE_SHIFT 4
#define HDA_SDCTL_FEIE_SHIFT 3
#define HDA_SDCTL_ICE_SHIFT 2
#define HDA_SDCTL_RUN_SHIFT 1
#define HDA_SDCTL_SRST_SHIFT 0
#define HDA_RMX_SD0STS 33
#define HDA_SDSTS_FIFORDY_SHIFT 5
#define HDA_SDSTS_DE_SHIFT 4
#define HDA_SDSTS_FE_SHIFT 3
#define HDA_SDSTS_BCIS_SHIFT 2
#define HDA_RMX_SD0LPIB 34
#define HDA_RMX_SD0CBL 35
#define HDA_RMX_SD0LVI 36
#define HDA_RMX_SD0FIFOW 37
/*
* ICH6 datasheet defined limits for FIFOW values (18.2.38)
*/
#define HDA_SDFIFOW_8B 0x2
#define HDA_SDFIFOW_16B 0x3
#define HDA_SDFIFOW_32B 0x4
#define HDA_RMX_SD0FIFOS 38
/*
* ICH6 datasheet defines limits for FIFOS registers (18.2.39)
* formula: size - 1
* Other values not listed are not supported.
*/
#define HDA_RMX_SD0FMT 39
#define HDA_SDFMT_BASE_RATE_SHIFT 14
#define HDA_SDFMT_MULT_SHIFT 11
#define HDA_SDFMT_MULT_MASK 0x7
#define HDA_SDFMT_DIV_SHIFT 8
#define HDA_SDFMT_DIV_MASK 0x7
#define HDA_SDFMT_BITS_SHIFT 4
#define HDA_SDFMT_BITS_MASK 0x7
#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
#define HDA_RMX_SD0BDPL 40
#define HDA_RMX_SD0BDPU 41
/*******************************************************************************
* Structures and Typedefs *
*******************************************************************************/
typedef struct HDABDLEDESC
{
bool fBdleCviIoc;
} HDABDLEDESC, *PHDABDLEDESC;
typedef struct HDASTREAMTRANSFERDESC
{
/**
* ICH Intel HD Audio Controller state.
*/
typedef struct HDASTATE
{
/** The PCI device structure. */
/** R3 Pointer to the device instance. */
/** R0 Pointer to the device instance. */
/** R0 Pointer to the device instance. */
/** Pointer to the connector of the attached audio driver. */
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
#else
#endif
/** Pointer to the attached audio driver. */
/** The base interface for LUN\#0. */
/** pointer to CORB buf */
/** size in bytes of CORB buf */
/** pointer on RIRB buf */
/** size in bytes of RIRB buf */
/** indicates if HDA in reset. */
bool fInReset;
/** Interrupt on completion */
bool fCviIoc;
/** Flag whether the R0 part is enabled. */
bool fR0Enabled;
/** Flag whether the RC part is enabled. */
bool fRCEnabled;
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
/** The HDA codec state. */
#else
#endif
/** 1.2.3.4.5.6.7. - someone please tell me what I'm counting! - .8.9.10... */
} HDASTATE;
/** Pointer to the ICH Intel HD Audio Controller state. */
#define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \
( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )
#define OSD0FMT_TO_AUDIO_SELECTOR(pThis) \
( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
#ifndef VBOX_DEVICE_STRUCT_TESTCASE
static FNPDMDEVRESET hdaReset;
#ifdef IN_RING3
#ifdef LOG_ENABLED
#endif
#endif
/*******************************************************************************
* Global Variables *
*******************************************************************************/
/* see 302349 p 6.2*/
static const struct HDAREGDESC
{
/** Register offset in the register space. */
/** Size in bytes. Registers of size > 4 are in fact tables. */
/** Readable bits. */
/** Writable bits. */
/** Read callback. */
/** Write callback. */
/** Index into the register storage array. */
/** Abbreviated name. */
const char *abbrev;
} g_aHdaRegMap[HDA_NREGS] =
/* Turn a short register name into an memory index and a stringized name. */
/* Same as above for an input stream ('I' prefixed). */
/* Same as above for an output stream ('O' prefixed). */
/* Same as above for a register *not* stored in memory. */
{
/* offset size read mask write mask read callback write callback abbrev */
/*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- */
{ 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(GCAP) }, /* Global Capabilities */
{ 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMIN) }, /* Minor Version */
{ 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMAJ) }, /* Major Version */
{ 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTPAY) }, /* Output Payload Capabilities */
{ 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INPAY) }, /* Input Payload Capabilities */
{ 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , RA(GCTL) }, /* Global Control */
{ 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , RA(WAKEEN) }, /* Wake Enable */
{ 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , RA(STATESTS) }, /* State Change Status */
{ 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , RA(GSTS) }, /* Global Status */
{ 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTSTRMPAY)}, /* Output Stream Payload Capability */
{ 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INSTRMPAY) }, /* Input Stream Payload Capability */
{ 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(INTCTL) }, /* Interrupt Control */
{ 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , RA(INTSTS) }, /* Interrupt Status */
{ 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , UA(WALCLK) }, /* Wall Clock Counter */
/// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
{ 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(SSYNC) }, /* Stream Synchronization */
{ 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(CORBLBASE) }, /* CORB Lower Base Address */
{ 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(CORBUBASE) }, /* CORB Upper Base Address */
{ 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , RA(CORBWP) }, /* CORB Write Pointer */
{ 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , RA(CORBRP) }, /* CORB Read Pointer */
{ 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , RA(CORBCTL) }, /* CORB Control */
{ 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , RA(CORBSTS) }, /* CORB Status */
{ 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(CORBSIZE) }, /* CORB Size */
{ 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBLBASE) }, /* RIRB Lower Base Address */
{ 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBUBASE) }, /* RIRB Upper Base Address */
{ 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , RA(RIRBWP) }, /* RIRB Write Pointer */
{ 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , RA(RINTCNT) }, /* Response Interrupt Count */
{ 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , RA(RIRBCTL) }, /* RIRB Control */
{ 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , RA(RIRBSTS) }, /* RIRB Status */
{ 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(RIRBSIZE) }, /* RIRB Size */
{ 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , RA(IC) }, /* Immediate Command */
{ 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , RA(IR) }, /* Immediate Response */
{ 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , RA(IRS) }, /* Immediate Command Status */
{ 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , RA(DPLBASE) }, /* MA Position Lower Base */
{ 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(DPUBASE) }, /* DMA Position Upper Base */
{ 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD0CTL) }, /* Input Stream Descriptor 0 (ICD0) Control */
{ 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD0STS) }, /* ISD0 Status */
{ 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0LPIB) }, /* ISD0 Link Position In Buffer */
{ 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0CBL) }, /* ISD0 Cyclic Buffer Length */
{ 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD0LVI) }, /* ISD0 Last Valid Index */
{ 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD0FIFOW) }, /* ISD0 FIFO Watermark */
{ 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD0FIFOS) }, /* ISD0 FIFO Size */
{ 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD0FMT) }, /* ISD0 Format */
{ 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD0BDPL) }, /* ISD0 Buffer Descriptor List Pointer-Lower Base Address */
{ 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD0BDPU) }, /* ISD0 Buffer Descriptor List Pointer-Upper Base Address */
{ 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD1CTL) }, /* Input Stream Descriptor 1 (ISD1) Control */
{ 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD1STS) }, /* ISD1 Status */
{ 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1LPIB) }, /* ISD1 Link Position In Buffer */
{ 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1CBL) }, /* ISD1 Cyclic Buffer Length */
{ 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD1LVI) }, /* ISD1 Last Valid Index */
{ 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD1FIFOW) }, /* ISD1 FIFO Watermark */
{ 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD1FIFOS) }, /* ISD1 FIFO Size */
{ 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD1FMT) }, /* ISD1 Format */
{ 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD1BDPL) }, /* ISD1 Buffer Descriptor List Pointer-Lower Base Address */
{ 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD1BDPU) }, /* ISD1 Buffer Descriptor List Pointer-Upper Base Address */
{ 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD2CTL) }, /* Input Stream Descriptor 2 (ISD2) Control */
{ 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD2STS) }, /* ISD2 Status */
{ 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2LPIB) }, /* ISD2 Link Position In Buffer */
{ 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2CBL) }, /* ISD2 Cyclic Buffer Length */
{ 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD2LVI) }, /* ISD2 Last Valid Index */
{ 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD2FIFOW) }, /* ISD2 FIFO Watermark */
{ 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD2FIFOS) }, /* ISD2 FIFO Size */
{ 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD2FMT) }, /* ISD2 Format */
{ 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD2BDPL) }, /* ISD2 Buffer Descriptor List Pointer-Lower Base Address */
{ 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD2BDPU) }, /* ISD2 Buffer Descriptor List Pointer-Upper Base Address */
{ 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD3CTL) }, /* Input Stream Descriptor 3 (ISD3) Control */
{ 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD3STS) }, /* ISD3 Status */
{ 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3LPIB) }, /* ISD3 Link Position In Buffer */
{ 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3CBL) }, /* ISD3 Cyclic Buffer Length */
{ 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD3LVI) }, /* ISD3 Last Valid Index */
{ 0x000EE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD3FIFOW) }, /* ISD3 FIFO Watermark */
{ 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD3FIFOS) }, /* ISD3 FIFO Size */
{ 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD3FMT) }, /* ISD3 Format */
{ 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD3BDPL) }, /* ISD3 Buffer Descriptor List Pointer-Lower Base Address */
{ 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD3BDPU) }, /* ISD3 Buffer Descriptor List Pointer-Upper Base Address */
{ 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD4CTL) }, /* Output Stream Descriptor 0 (OSD0) Control */
{ 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD4STS) }, /* OSD0 Status */
{ 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4LPIB) }, /* OSD0 Link Position In Buffer */
{ 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4CBL) }, /* OSD0 Cyclic Buffer Length */
{ 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD4LVI) }, /* OSD0 Last Valid Index */
{ 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD4FIFOW) }, /* OSD0 FIFO Watermark */
{ 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD4FIFOS) }, /* OSD0 FIFO Size */
{ 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD4FMT) }, /* OSD0 Format */
{ 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD4BDPL) }, /* OSD0 Buffer Descriptor List Pointer-Lower Base Address */
{ 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD4BDPU) }, /* OSD0 Buffer Descriptor List Pointer-Upper Base Address */
{ 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD5CTL) }, /* Output Stream Descriptor 0 (OSD1) Control */
{ 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD5STS) }, /* OSD1 Status */
{ 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5LPIB) }, /* OSD1 Link Position In Buffer */
{ 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5CBL) }, /* OSD1 Cyclic Buffer Length */
{ 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD5LVI) }, /* OSD1 Last Valid Index */
{ 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD5FIFOW) }, /* OSD1 FIFO Watermark */
{ 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD5FIFOS) }, /* OSD1 FIFO Size */
{ 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD5FMT) }, /* OSD1 Format */
{ 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD5BDPL) }, /* OSD1 Buffer Descriptor List Pointer-Lower Base Address */
{ 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD5BDPU) }, /* OSD1 Buffer Descriptor List Pointer-Upper Base Address */
{ 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD6CTL) }, /* Output Stream Descriptor 0 (OSD2) Control */
{ 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD6STS) }, /* OSD2 Status */
{ 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6LPIB) }, /* OSD2 Link Position In Buffer */
{ 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6CBL) }, /* OSD2 Cyclic Buffer Length */
{ 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD6LVI) }, /* OSD2 Last Valid Index */
{ 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD6FIFOW) }, /* OSD2 FIFO Watermark */
{ 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD6FIFOS) }, /* OSD2 FIFO Size */
{ 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD6FMT) }, /* OSD2 Format */
{ 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD6BDPL) }, /* OSD2 Buffer Descriptor List Pointer-Lower Base Address */
{ 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD6BDPU) }, /* OSD2 Buffer Descriptor List Pointer-Upper Base Address */
{ 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD7CTL) }, /* Output Stream Descriptor 0 (OSD3) Control */
{ 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD7STS) }, /* OSD3 Status */
{ 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7LPIB) }, /* OSD3 Link Position In Buffer */
{ 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7CBL) }, /* OSD3 Cyclic Buffer Length */
{ 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD7LVI) }, /* OSD3 Last Valid Index */
{ 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD7FIFOW) }, /* OSD3 FIFO Watermark */
{ 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD7FIFOS) }, /* OSD3 FIFO Size */
{ 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD7FMT) }, /* OSD3 Format */
{ 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD7BDPL) }, /* OSD3 Buffer Descriptor List Pointer-Lower Base Address */
{ 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD7BDPU) }, /* OSD3 Buffer Descriptor List Pointer-Upper Base Address */
};
/**
* HDA register aliases (HDA spec 3.3.45).
* @remarks Sorted by offReg.
*/
static const struct
{
/** The alias register offset. */
/** The register index. */
int idxAlias;
} g_aHdaRegAliases[] =
{
{ 0x2084, HDA_REG_SD0LPIB },
{ 0x20a4, HDA_REG_SD1LPIB },
{ 0x20c4, HDA_REG_SD2LPIB },
{ 0x20e4, HDA_REG_SD3LPIB },
{ 0x2104, HDA_REG_SD4LPIB },
{ 0x2124, HDA_REG_SD5LPIB },
{ 0x2144, HDA_REG_SD6LPIB },
{ 0x2164, HDA_REG_SD7LPIB },
};
#ifdef IN_RING3
/** HDABDLEDESC field descriptors the v3+ saved state. */
static SSMFIELD const g_aHdaBDLEDescFields[] =
{
};
/** HDABDLEDESC field descriptors the v1 and v2 saved state. */
static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =
{
};
#endif
/**
* 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
*/
{
};
#ifdef IN_RING3
{
}
#endif
{
#if 0
{
case HDA_SDFIFOW_8B: return 8;
case HDA_SDFIFOW_16B: return 16;
case HDA_SDFIFOW_32B: return 32;
default:
AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pThis, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
}
#endif
return 0;
}
{
bool fIrq = false;
fIrq = true;
if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
fIrq = true;
{
}
return VINF_SUCCESS;
}
/**
* Looks up a register at the exact offset given by @a offReg.
*
* @returns Register index on success, -1 if not found.
* @param pThis The HDA device state.
* @param offReg The register offset.
*/
{
/*
* Aliases.
*/
{
for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
return g_aHdaRegAliases[i].idxAlias;
return -1;
}
/*
* Binary search the
*/
int idxLow = 0;
for (;;)
{
{
break;
}
{
break;
}
else
return idxMiddle;
}
#ifdef RT_STRICT
for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
#endif
return -1;
}
/**
* Looks up a register covering the offset given by @a offReg.
*
* @returns Register index on success, -1 if not found.
* @param pThis The HDA device state.
* @param offReg The register offset.
*/
{
/*
* Aliases.
*/
{
for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
{
return g_aHdaRegAliases[i].idxAlias;
}
return -1;
}
/*
* Binary search the
*/
int idxLow = 0;
for (;;)
{
{
break;
}
{
break;
}
else
return idxMiddle;
}
#ifdef RT_STRICT
for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
#endif
return -1;
}
#ifdef IN_RING3
{
int rc = VINF_SUCCESS;
if (fLocal)
{
rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
if (RT_FAILURE(rc))
#ifdef DEBUG_CMD_BUFFER
uint8_t i = 0;
do
{
Log(("hda: corb%02x: ", i));
uint8_t j = 0;
do
{
const char *prefix;
prefix = "[R]";
prefix = "[W]";
else
j++;
} while (j < 8);
Log(("\n"));
i += 8;
} while(i != 0);
#endif
}
else
{
rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
if (RT_FAILURE(rc))
#ifdef DEBUG_CMD_BUFFER
uint8_t i = 0;
do {
Log(("hda: rirb%02x: ", i));
uint8_t j = 0;
do {
const char *prefix;
prefix = "[W]";
else
prefix = " ";
} while (++j < 8);
Log(("\n"));
i += 8;
} while (i != 0);
#endif
}
return rc;
}
{
int rc;
if (RT_FAILURE(rc))
{
corbRp++;
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
#else
#endif
if (RT_FAILURE(rc))
(rirbWp)++;
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
{
}
#else
#endif
else
if (RT_FAILURE(rc))
if ( (resp & CODEC_RESPONSE_UNSOLICITED)
{
Log(("hda: unexpected unsolicited response.\n"));
return rc;
}
break;
}
{
}
if (RT_FAILURE(rc))
return rc;
}
#endif
static void hdaStreamReset(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
{
&& pBdle
&& pStreamDesc
&& u8Strm <= 7));
*pStreamDesc->pu32Lpib = 0;
*pStreamDesc->pu32Sts = 0;
/* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
* bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
HDA_STREAM_REG(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
/* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
}
/* Register access handlers. */
{
*pu32Value = 0;
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
/* U8 */
{
Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
}
{
}
/* U16 */
{
Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
}
{
}
/* U24 */
{
Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
}
{
}
/* U32 */
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
{
/* exit reset state */
}
else
{
#ifdef IN_RING3
/* enter reset state*/
{
Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
}
#else
return VINF_IOM_R3_MMIO_WRITE;
#endif
}
{
/* Flush: GSTS:1 set, see 6.2.6*/
/* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/
}
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
uint32_t v = 0;
v |= RT_BIT(30);
#define MARK_STREAM(pThis, stream, v) do { (v) |= HDA_IS_STREAM_EVENT((pThis),stream) ? RT_BIT((stream)) : 0; } while(0)
MARK_STREAM(pThis, 0, v);
v |= v ? RT_BIT(31) : 0;
*pu32Value = v;
return VINF_SUCCESS;
}
{
/* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
return VINF_SUCCESS;
}
{
#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
else
#endif
return VINF_SUCCESS;
}
{
#ifdef IN_RING3
return hdaCORBCmdProcess(pThis);
return rc;
#else
return VINF_IOM_R3_MMIO_WRITE;
#endif
}
{
return VINF_SUCCESS;
}
{
#ifdef IN_RING3
int rc;
if (RT_FAILURE(rc))
return VINF_SUCCESS;
return VINF_SUCCESS;
return rc;
#else
return VINF_IOM_R3_MMIO_WRITE;
#endif
}
{
if (fInReset)
{
/*
* Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
* from reset
*/
Log(("hda: guest initiated exit of stream reset.\n"));
}
else if (fReset)
{
#ifdef IN_RING3
/*
* Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
*/
switch (iReg)
{
case HDA_REG_SD0CTL:
u8Strm = 0;
break;
case HDA_REG_SD4CTL:
u8Strm = 4;
break;
default:
Log(("hda: changing SRST bit on non-attached stream\n"));
}
Log(("hda: guest initiated enter to stream reset.\n"));
#else
return VINF_IOM_R3_MMIO_WRITE;
#endif
}
else
{
#ifdef IN_RING3
/* we enter here to change DMA states only */
{
switch (iReg)
{
case HDA_REG_SD0CTL:
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
#else
#endif
break;
case HDA_REG_SD4CTL:
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
#else
#endif
break;
default:
Log(("hda: changing RUN bit on non-attached stream\n"));
break;
}
}
#else
return VINF_IOM_R3_MMIO_WRITE;
#endif
}
}
{
v &= ~(u32Value & v);
return VINF_SUCCESS;
}
{
if (RT_FAILURE(rc))
return rc;
}
{
switch (u32Value)
{
case HDA_SDFIFOW_8B:
case HDA_SDFIFOW_16B:
case HDA_SDFIFOW_32B:
default:
}
return VINF_SUCCESS;
}
/**
* @note This method could be called for changing value on Output Streams
* only (ICH6 datasheet 18.2.39)
*/
{
switch (iReg)
{
/* SDInFIFOS is RO, n=0-3 */
case HDA_REG_SD0FIFOS:
case HDA_REG_SD1FIFOS:
case HDA_REG_SD2FIFOS:
case HDA_REG_SD3FIFOS:
Log(("hda: Guest tries change value of FIFO size of Input Stream\n"));
return VINF_SUCCESS;
case HDA_REG_SD4FIFOS:
case HDA_REG_SD5FIFOS:
case HDA_REG_SD6FIFOS:
case HDA_REG_SD7FIFOS:
switch(u32Value)
{
case HDA_SDONFIFO_16B:
case HDA_SDONFIFO_32B:
case HDA_SDONFIFO_64B:
case HDA_SDONFIFO_128B:
case HDA_SDONFIFO_192B:
case HDA_SDONFIFO_256B:
Log(("hda: 256-bit is unsupported, HDA is switched into 192-bit mode\n"));
default:
}
return VINF_SUCCESS;
default:
AssertMsgFailed(("Something weird happened with register lookup routine"));
}
return VINF_SUCCESS;
}
#ifdef IN_RING3
# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
static void hdaSdFmtToAudSettings(uint32_t u32SdFmt, uint32_t * pFrequency, uint32_t * pChannels, audfmt_e *pFormat, uint32_t *pEndian)
# else
# endif
{
# ifndef VBOX_WITH_PDM_AUDIO_DRIVER
Assert((pAudSetting));
# endif
{
case 0: u32HzMult = 1; break;
default:
}
{
case 0: u32HzDiv = 1; break;
}
# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
# else
# endif
{
case 0:
# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
*pFormat = AUD_FMT_S8;
# else
# endif
break;
case 1:
# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
*pFormat = AUD_FMT_S16;
# else
# endif
break;
case 2:
break;
case 3:
break;
case 4:
# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
*pFormat = AUD_FMT_S32;
# else
# endif
break;
default:
AssertMsgFailed(("Unsupported"));
}
# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
*pFormat = AUD_FMT_S16;
*pEndian = 0;
# else
pAudSetting->endianness = 0;
# endif
}
#endif
{
#ifdef IN_RING3
# ifdef VBOX_WITH_HDA_CODEC_EMU
/** @todo a bit more investigation is required here. */
int rc = 0;
/* no reason to reopen voice with same settings */
return VINF_SUCCESS;
# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
# else
# endif
switch (iReg)
{
case HDA_REG_SD0FMT:
# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
# else
# endif
break;
case HDA_REG_SD4FMT:
# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
# else
# endif
break;
default:
rc = 0;
}
# else
# endif
#else
return VINF_IOM_R3_MMIO_WRITE;
#endif
}
{
if (RT_FAILURE(rc))
return rc;
}
{
if (RT_FAILURE(rc))
return rc;
}
{
int rc = VINF_SUCCESS;
/* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
return rc;
}
{
int rc = VINF_SUCCESS;
/*
* if guest set the ICB bit of IRS register, HDA should process the verb in IC register,
* write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
*/
{
#ifdef IN_RING3
{
/*
* 3.4.3 defines behavior of immediate Command status register.
*/
return rc;
}
# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
# else
# endif
if (RT_FAILURE(rc))
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
#else
#endif
if (RT_FAILURE(rc))
#else
#endif
return rc;
}
/*
* Once the guest read the response, it should clean the IRV bit of the IRS register.
*/
return rc;
}
{
{
}
/* The remaining bits are O, see 6.2.22 */
return VINF_SUCCESS;
}
{
if (RT_FAILURE(rc))
switch(iReg)
{
case HDA_REG_CORBLBASE:
break;
case HDA_REG_CORBUBASE:
break;
case HDA_REG_RIRBLBASE:
break;
case HDA_REG_RIRBUBASE:
break;
case HDA_REG_DPLBASE:
/** @todo: first bit has special meaning */
break;
case HDA_REG_DPUBASE:
break;
default:
AssertMsgFailed(("Invalid index"));
}
Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
return rc;
}
{
return hdaProcessInterrupt(pThis);
}
#ifdef IN_RING3
#ifdef LOG_ENABLED
{
#if 0
uint32_t i;
for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
{
Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
}
for (i = 0; i < 8; ++i)
{
PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pThis, 4) || i == SDCTL_NUM(pThis, 0)? "[C]": " ",
i , counter));
}
#endif
}
#endif
{
&& pBdle
&& pBdle->u32BdleMaxCvi));
PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
#ifdef LOG_ENABLED
#endif
}
DECLINLINE(uint32_t) hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
{
/*
* Number of bytes depends on the current position in buffer (u32BdleCviLen-u32BdleCviPos)
*/
/*
* we may increase the counter in range of [0, FIFOS + 1]
*/
/* sanity check to avoid overriding the backend audio buffer */
return 0;
return cb2Copy;
}
DECLINLINE(void) hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
{
Log(("hda:hdaBackendWriteTransferReported: cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
/* Assertion!!! Fewer than cbUnderFifoW bytes were copied.
* Probably we need to move the buffer, but it is rather hard to imagine a situation
* where it might happen.
*/
Assert((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy)); /* we assume that we write the entire buffer including unreported bytes */
if ( pBdle->cbUnderFifoW
Log(("hda:hdaBackendWriteTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
/* We always increment the position of DMA buffer counter because we're always reading into an intermediate buffer */
Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
/* We report all bytes (including previously unreported bytes) */
*pu32DMACursor += cbCopied;
/* Decrease the backend counter by the number of bytes we copied to the backend */
Log(("hda:hdaBackendWriteTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
}
DECLINLINE(void) hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
{
Log(("hda:hdaBackendReadTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
pBdle->cbUnderFifoW = 0;
Log(("hda:hdaBackendReadTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
}
DECLINLINE(void) hdaBackendTransferUnreported(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
{
Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
/* In case of a read transaction we're always copying from the backend buffer */
Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
}
DECLINLINE(bool) hdaIsTransferCountersOverlapped(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
{
/* don't touch BdleCvi counter on uninitialized descriptor */
if ( pBdle->u32BdleCviPos
{
pBdle->u32BdleCviPos = 0;
pBdle->u32BdleCvi++;
pBdle->u32BdleCvi = 0;
}
return fOnBufferEdge;
}
DECLINLINE(void) hdaStreamCounterUpdate(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
{
/*
* if we're below the FIFO Watermark, it's expected that HDA doesn't fetch anything.
* (ICH6 datasheet 18.2.38)
*/
if (!pBdle->cbUnderFifoW)
{
/*
* Assert. The buffer counters should never overlap.
*/
}
}
static bool hdaDoNextTransferCycle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
{
bool fDoNextTransferLoop = true;
{
if ( !pBdle->cbUnderFifoW
&& pBdle->fBdleCviIoc)
{
/**
* @todo - more carefully investigate BCIS flag.
* Speech synthesis works fine on Mac Guest if this bit isn't set
* but in general sound quality gets worse.
*/
/*
* we should generate the interrupt if ICE bit of SDCTL register is set.
*/
}
fDoNextTransferLoop = false;
}
return fDoNextTransferLoop;
}
/*
* hdaReadAudio - copies samples from audio backend to DMA.
* Note: this function writes to the DMA buffer immediately, but "reports bytes" when all conditions are met (FIFOW)
*/
static uint32_t hdaReadAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
{
uint32_t cbTransferred = 0;
uint32_t cbBackendCopy = 0;
if (!cb2Copy)
/* if we enter here we can't report "unreported bits" */
*fStop = true;
else
{
/*
* read from backend input line to the last unreported position or at the begining.
*/
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
//cbBackendCopy = pThis->pDrv[0]->pfnRead(pThis->pDrv[0], pThis->pCodec[0]->SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
//cbBackendCopy = pThis->pDrv[0]->pfnRead(pThis->pDrv[0], pThis->pCodec[1]->SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
#else
#endif
/*
* write the HDA DMA buffer
*/
PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
/* Don't see any reason why cb2Copy would differ from cbBackendCopy */
else
{
*fStop = true;
}
}
Log(("hda:ra: CVI(pos:%d, len:%d) cbTransferred: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
return cbTransferred;
}
static uint32_t hdaWriteAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
{
uint32_t cbTransferred = 0;
Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
/*
* Copy from DMA to the corresponding hdaBuffer (if there are any bytes from the
* previous unreported transfer we write at offset 'pBdle->cbUnderFifoW').
*/
if (!cb2Copy)
*fStop = true;
else
{
PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
/*
* Write to audio backend. we should ensure that we have enough bytes to copy to the backend.
*/
{
/*
* Feed the newly fetched samples, including unreported ones, to the backend.
*/
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
cbBackendCopy = pThis->pDrv[lun]->pfnWrite(pThis->pDrv[lun], pThis->pCodec[lun]->SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
#else
cbBackendCopy = AUD_write (pThis->pCodec->SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
#endif
}
else
{
/* Not enough bytes to be processed and reported, we'll try our luck next time around */
*fStop = true;
}
}
Log(("hda:wa: CVI(pos:%d, len:%d, cbTransferred:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
return cbTransferred;
}
/**
* @interface_method_impl{HDACODEC,pfnReset}
*/
{
return VINF_SUCCESS;
}
{
#ifdef LOG_ENABLED
if ( pBdle
&& pBdle->u32BdleMaxCvi)
{
Log(("Initialization of transfer descriptor:\n"));
}
#endif
}
/**
* @interface_method_impl{HDACODEC,pfnTransfer}
*/
{
switch (src)
{
case PO_INDEX:
{
u8Strm = 4;
break;
}
case PI_INDEX:
{
u8Strm = 0;
break;
}
default:
return;
}
bool fStop = false;
{
&& avail
&& StreamDesc.u64BaseDMA);
/* Fetch the Buffer Descriptor Entry (BDE). */
switch (src)
{
case PO_INDEX:
break;
case PI_INDEX:
break;
default:
cb = 0;
fStop = true;
AssertMsgFailed(("Unsupported"));
}
/* Process end of buffer condition. */
}
}
#endif
/* MMIO callbacks */
/**
* @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
*
* @note During implementation, we discovered so-called "forgotten" or "hole"
* registers whose description is not listed in the RPM, datasheet, or
* spec.
*/
PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
{
int rc;
/*
* Look up and log.
*/
#ifdef LOG_ENABLED
#endif
#define NEW_READ_CODE
#ifdef NEW_READ_CODE
Log(("hda: access to registers except GCTL is blocked while reset\n"));
if (idxRegDsc == -1)
if (idxRegDsc != -1)
{
/* ASSUMES gapless DWORD at end of map. */
{
/*
* Straight forward DWORD access.
*/
}
else
{
/*
* Multi register read (unless there are trailing gaps).
* ASSUMES that only DWORD reads have sideeffects.
*/
unsigned cbLeft = 4;
do
{
if (rc != VINF_SUCCESS)
break;
idxRegDsc++;
if (rc == VINF_SUCCESS)
else
}
}
else
{
}
#else
if (idxRegDsc != -1)
{
/** @todo r=bird: Accesses crossing register boundraries aren't handled
* right from what I can tell? If they are, please explain
* what the rules are. */
switch(cb)
{
case 4:
/* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
case 8:
mask = 0xffffffff;
cb = 4;
break;
}
#if 0
/* Cross-register access. Mac guest hits this assert doing assumption 4 byte access to 3 byte registers e.g. {I,O}SDnCTL
*/
//Assert((cb <= g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset)));
{
if (RT_FAILURE(rc))
}
//Assert(((offReg - g_aHdaRegMap[idxRegDsc].offset) == 0));
#endif
}
else
{
rc = VINF_SUCCESS;
}
#endif
/*
* Log the outcome.
*/
#ifdef LOG_ENABLED
if (cbLog == 4)
else if (cbLog == 2)
else if (cbLog == 1)
#endif
return rc;
}
{
Log(("hda: access to registers except GCTL is blocked while reset\n")); /** @todo where is this enforced? */
#ifdef LOG_ENABLED
#endif
return rc;
}
/**
* @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
*/
PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
{
int rc;
/*
* The behavior of accesses that aren't aligned on natural boundraries is
* undefined. Just reject them outright.
*/
/** @todo IOM could check this, it could also split the 8 byte accesses for us. */
return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
/*
* Look up and log the access.
*/
else
{
u64Value = 0; /* shut up gcc. */
}
#ifdef LOG_ENABLED
if (idxRegDsc == -1)
else if (cb == 4)
Log(("hdaMMIOWrite: @%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
else if (cb == 2)
Log(("hdaMMIOWrite: @%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
else if (cb == 1)
Log(("hdaMMIOWrite: @%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
#endif
#define NEW_WRITE_CODE
#ifdef NEW_WRITE_CODE
/*
* Try for a direct hit first.
*/
/*
* Partial or multiple register access, loop thru the requested memory.
*/
else
{
/* If it's an access beyond the start of the register, shift the input
value and fill in missing bits. Natural alignment rules means we
will only see 1 or 2 byte accesses of this kind, so no risk of
shifting out input values. */
{
uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
Log(("hdaMMIOWrite: Within register, supplied %u leading bits: %#llx -> %#llx ...\n",
}
/* Loop thru the write area, it may cover multiple registers. */
rc = VINF_SUCCESS;
for (;;)
{
if (idxRegDsc != -1)
{
{
Log(("hdaMMIOWrite: Supplying missing bits (%#x): %#llx -> %#llx ...\n",
}
}
else
{
cbReg = 1;
}
if (rc != VINF_SUCCESS)
break;
break;
/* advance */
if (idxRegDsc == -1)
else
{
idxRegDsc++;
idxRegDsc = -1;
}
}
}
#else
if (idxRegDsc != -1)
{
/** @todo r=bird: This looks like code for handling unaligned register
* accesses. If it isn't, then add a comment explaining what you're
* trying to do here. OTOH, if it is then it has the following
* issues:
* -# You're calculating the wrong new value for the register.
* -# You're not handling cross register accesses. Imagine a
* 4-byte write starting at CORBCTL, or a 8-byte write.
*
* nobody seems to be using it and it just adds complexity when reading
* the code.
*
*/
switch (cb)
{
case 1:
mask = 0xff;
break;
case 2:
mask = 0xffff;
break;
case 4:
case 8:
/* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
mask = 0xffffffff;
cb = 4;
break;
default:
}
/* cross-register access, see corresponding comment in hdaMMIORead */
u32NewValue <<= shift;
u32NewValue &= mask;
}
else
rc = VINF_SUCCESS;
#endif
return rc;
}
/* PCI callback. */
#ifdef IN_RING3
/**
* @callback_method_impl{FNPCIIOREGIONMAP}
*/
static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
{
int rc;
/*
* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
*
* Let IOM talk DWORDs when reading, saves a lot of complications. On
* writing though, we have to do it all ourselves because of sideeffects.
*/
#ifdef NEW_READ_CODE
#else
#endif
if (RT_FAILURE(rc))
return rc;
if (pThis->fR0Enabled)
{
"hdaMMIOWrite", "hdaMMIORead");
if (RT_FAILURE(rc))
return rc;
}
if (pThis->fRCEnabled)
{
"hdaMMIOWrite", "hdaMMIORead");
if (RT_FAILURE(rc))
return rc;
}
return VINF_SUCCESS;
}
/* Saved state callbacks. */
/**
* @callback_method_impl{FNSSMDEVSAVEEXEC}
*/
{
/* Save Codec nodes states */
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
#else
#endif
/* Save MMIO registers */
/* Save HDA dma counters */
SSMR3PutStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
SSMR3PutStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
SSMR3PutStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
return VINF_SUCCESS;
}
/**
* @callback_method_impl{FNSSMDEVLOADEXEC}
*/
static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
{
/*
* Load Codec nodes states.
*/
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
#else
#endif
if (RT_FAILURE(rc))
return rc;
/*
* Load MMIO registers.
*/
switch (uVersion)
{
case HDA_SSM_VERSION_1:
/* Starting with r71199, we would save 112 instead of 113
registers due to some code cleanups. This only affected trunk
builds in the 4.1 development period. */
cRegs = 113;
{
&& VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
cRegs = 112;
}
break;
case HDA_SSM_VERSION_2:
case HDA_SSM_VERSION_3:
cRegs = 112;
break;
case HDA_SSM_VERSION:
break;
default:
}
{
}
else
/*
* Load HDA dma counters.
*/
PCSSMFIELD paFields = uVersion <= HDA_SSM_VERSION_2 ? g_aHdaBDLEDescFieldsOld : g_aHdaBDLEDescFields;
/*
* Update stuff after the state changes.
*/
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
{
pThis->pDrv[lun]->pfnEnableIn(pThis->pDrv[lun], pThis->pCodec[lun]->SwVoiceIn, SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
pThis->pDrv[lun]->pfnEnableOut(pThis->pDrv[lun], pThis->pCodec[lun]->SwVoiceOut, SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
}
#else
AUD_set_active_out(pThis->pCodec->SwVoiceOut, SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
#endif
return VINF_SUCCESS;
}
/* Debug and log type formatters. */
/**
* @callback_method_impl{FNRTSTRFORMATTYPE}
*/
static DECLCALLBACK(size_t)
void *pvUser)
{
"SDCTL(raw: %#x, strm:%#x, dir:%RTbool, tp:%RTbool strip:%x, deie:%RTbool, ioce:%RTbool, run:%RTbool, srst:%RTbool)",
}
/**
* @callback_method_impl{FNRTSTRFORMATTYPE}
*/
static DECLCALLBACK(size_t)
void *pvUser)
{
switch (uSdFifos)
{
default: cb = 0; break;
}
return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw: %#x, sdfifos:%u B)", uSdFifos, cb);
}
/**
* @callback_method_impl{FNRTSTRFORMATTYPE}
*/
static DECLCALLBACK(size_t)
void *pvUser)
{
switch (uSdFifos)
{
default: cb = 0; break;
}
return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSdFifos, cb);
}
/**
* @callback_method_impl{FNRTSTRFORMATTYPE}
*/
static DECLCALLBACK(size_t)
void *pvUser)
{
"SDSTS(raw: %#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
}
{
int iReg = 0;
return iReg;
return -1;
}
{
&& iHdaIndex >= 0
pHlp->pfnPrintf(pHlp, "hda: %s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
}
/**
* @callback_method_impl{FNDBGFHANDLERDEV}
*/
{
if (iHdaRegisterIndex != -1)
else
}
{
&& iHdaStrmIndex >= 0
&& iHdaStrmIndex < 7);
pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, CTL, iHdaStrmIndex));
pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, STS, iHdaStrmIndex));
pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOS, iHdaStrmIndex));
pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOW, iHdaStrmIndex));
}
{
/* todo: add args parsing */
return -1;
}
/**
* @callback_method_impl{FNDBGFHANDLERDEV}
*/
static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
{
if (iHdaStrmIndex != -1)
else
}
/**
* @callback_method_impl{FNDBGFHANDLERDEV}
*/
static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
{
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
else
#else
else
#endif
}
/**
* @callback_method_impl{FNDBGFHANDLERDEV}
*/
static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
{
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
else
#else
else
#endif
}
/* PDMIBASE */
/**
* @interface_method_impl{PDMIBASE,pfnQueryInterface}
*/
{
return NULL;
}
/* PDMDEVREG */
/**
* Reset notification.
*
* @returns VBox status.
* @param pDevIns The device instance data.
*
* @remark The original sources didn't install a reset handler, but it seems to
* make sense to me so we'll do it.
*/
{
Log(("hda: inter HDA reset.\n"));
if (pThis->pu32CorbBuf)
else
if (pThis->pu64RirbBuf)
else
{
if (u8Strm == 0)
else if(u8Strm == 4)
else
{
pBdle = &StEmptyBdle;
}
/* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
}
/* emulation of codec "wake up" (HDA spec 5.5.1 and 6.5)*/
Log(("hda: reset finished\n"));
}
/**
* @interface_method_impl{PDMDEVREG,pfnDestruct}
*/
{
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
{
{
}
}
#else
{
}
#endif
return VINF_SUCCESS;
}
/**
* @interface_method_impl{PDMDEVREG,pfnConstruct}
*/
{
int rc;
/*
* Validations.
*/
"RCEnabled\0"))
N_ ("Invalid configuration for the Intel HDA device"));
if (RT_FAILURE(rc))
N_("HDA configuration error: failed to read RCEnabled as boolean"));
if (RT_FAILURE(rc))
N_("HDA configuration error: failed to read R0Enabled as boolean"));
/*
* Initialize data (most of it anyway).
*/
/* IBase */
/* PCI Device */
false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
#if defined(HDA_AS_PCI_EXPRESS)
#elif defined(VBOX_WITH_MSI_DEVICES)
#else
#endif
/// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
/// of these values needs to be properly documented!
/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
/* Power Management */
#ifdef HDA_AS_PCI_EXPRESS
/* PCI Express */
/* Device flags */
/* version */ 0x1 |
/* MSI */ (100) << 9 );
/* Device capabilities */
/* Device control */
/* Device status */
/* Link caps */
/* Link control */
/* Link status */
/* Slot capabilities */
/* Slot control */
/* Slot status */
/* Root control */
/* Root capabilities */
/* Root status */
/* Device capabilities 2 */
/* Device control 2 */
/* Link control 2 */
/* Slot control 2 */
#endif
/*
* Register the PCI device.
*/
if (RT_FAILURE(rc))
return rc;
if (RT_FAILURE(rc))
return rc;
#ifdef VBOX_WITH_MSI_DEVICES
if (RT_FAILURE(rc))
{
}
#endif
if (RT_FAILURE(rc))
return rc;
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
//for (iter = 0; i < 3; i++)
{
/*
* Attach driver.
*/
if (RT_SUCCESS(rc))
{
("Configuration error: instance %d has no host audio interface!\n", iInstance),
}
else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
{
Log(("ac97: No attached driver!\n"));
}
else if (RT_FAILURE(rc))
{
return rc;
}
if (RT_SUCCESS(rc))
{
("Configuration error: instance %d has no host audio interface!\n", iInstance),
}
else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
{
Log(("ac97: No attached driver! LUN#1\n"));
}
else if (RT_FAILURE(rc))
{
return rc;
}
}
#else
/*
* Attach driver.
*/
if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
Log(("hda: No attached driver!\n"));
else if (RT_FAILURE(rc))
{
return rc;
}
#endif
/* Construct codec state. */
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
//pThis->pCodec[1]->pDrv = pThis->pDrv[1];
#endif
if (RT_FAILURE(rc))
if (RT_FAILURE(rc))
/* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
#else
if (RT_FAILURE(rc))
/* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
/*
* hdaReset shouldn't affects these registers.
*/
#endif
/*
* Debug and string formatter types.
*/
PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
#if 0
#endif
/*
* Some debug assertions.
*/
for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
{
struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
/* binary search order. */
("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
/* alignment. */
/* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
{
if (pPrevReg)
("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
}
#if 0
{
if (pNextReg)
("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
}
#endif
/* The final entry is a full dword, no gaps! Allows shortcuts. */
}
return VINF_SUCCESS;
}
/**
* The device registration structure.
*/
const PDMDEVREG g_DeviceICH6_HDA =
{
/* u32Version */
/* szName */
"hda",
/* szRCMod */
"VBoxDDGC.gc",
/* szR0Mod */
"VBoxDDR0.r0",
/* pszDescription */
"Intel HD Audio Controller",
/* fFlags */
/* fClass */
/* cMaxInstances */
1,
/* cbInstance */
sizeof(HDASTATE),
/* pfnConstruct */
/* pfnDestruct */
/* pfnRelocate */
NULL,
/* pfnMemSetup */
NULL,
/* pfnPowerOn */
NULL,
/* pfnReset */
/* pfnSuspend */
NULL,
/* pfnResume */
NULL,
/* pfnAttach */
NULL,
/* pfnDetach */
NULL,
/* pfnQueryInterface. */
NULL,
/* pfnInitComplete */
NULL,
/* pfnPowerOff */
NULL,
/* pfnSoftReset */
NULL,
/* u32VersionEnd */
};
#endif /* IN_RING3 */
#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */