cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#include <xf86RamDac.h>
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsyncextern _X_EXPORT unsigned long TIramdacCalculateMNPForClock(unsigned long RefClock,
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync unsigned long ReqClock, char IsPixClock, unsigned long MinClock,
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync unsigned long MaxClock, unsigned long *rM, unsigned long *rN,
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync unsigned long *rP);
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsyncextern _X_EXPORT RamDacHelperRecPtr TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs);
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsyncextern _X_EXPORT void TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec);
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsyncextern _X_EXPORT void TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec);
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsyncextern _X_EXPORT void TIramdac3026SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec);
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsyncextern _X_EXPORT void TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec);
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsyncextern _X_EXPORT void TIramdacHWCursorInit(xf86CursorInfoPtr infoPtr);
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsyncextern _X_EXPORT void TIramdacLoadPalette( ScrnInfoPtr pScrn, int numColors, int *indices,
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync LOCO *colors, VisualPtr pVisual);
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsynctypedef void TIramdacLoadPaletteProc(ScrnInfoPtr, int, int *, LOCO *,
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync VisualPtr);
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsyncextern _X_EXPORT TIramdacLoadPaletteProc *TIramdacLoadPaletteWeak(void);
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TI3030_RAMDAC (VENDOR_TI << 16) | 0x00
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TI3026_RAMDAC (VENDOR_TI << 16) | 0x01
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync/*
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync * TI Ramdac registers
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync */
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_rev 0x01
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_ind_curs_ctrl 0x06
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_byte_router_ctrl 0x07
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_latch_ctrl 0x0f
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_true_color_ctrl 0x18
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_multiplex_ctrl 0x19
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_clock_select 0x1a
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_palette_page 0x1c
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_general_ctrl 0x1d
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_misc_ctrl 0x1e
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_pll_addr 0x2c
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_pll_pixel_data 0x2d
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_pll_memory_data 0x2e
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_pll_loop_data 0x2f
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_key_over_low 0x30
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_key_over_high 0x31
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_key_red_low 0x32
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_key_red_high 0x33
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_key_green_low 0x34
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_key_green_high 0x35
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_key_blue_low 0x36
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_key_blue_high 0x37
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_key_ctrl 0x38
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_clock_ctrl 0x39
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_sense_test 0x3a
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_test_mode_data 0x3b
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_crc_remain_lsb 0x3c
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_crc_remain_msb 0x3d
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_crc_bit_select 0x3e
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_id 0x3f
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync/* These are pll values that are accessed via TIDAC_pll_pixel_data */
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_PIXEL_N 0x80
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_PIXEL_M 0x81
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_PIXEL_P 0x82
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_PIXEL_VALID 0x83
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync/* These are pll values that are accessed via TIDAC_pll_loop_data */
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_LOOP_N 0x90
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_LOOP_M 0x91
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_LOOP_P 0x92
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_LOOP_VALID 0x93
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync/* Direct mapping addresses */
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_INDEX 0xa0
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_PALETTE_DATA 0xa1
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_READ_MASK 0xa2
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_READ_ADDR 0xa3
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_CURS_WRITE_ADDR 0xa4
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_CURS_COLOR 0xa5
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_CURS_READ_ADDR 0xa7
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_CURS_CTL 0xa9
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_INDEXED_DATA 0xaa
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_CURS_RAM_DATA 0xab
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_CURS_XLOW 0xac
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_CURS_XHIGH 0xad
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_CURS_YLOW 0xae
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_CURS_YHIGH 0xaf
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_sw_reset 0xff
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync/* Constants */
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_TVP_3026_ID 0x26
cabde247f900dcf6e58d009bbdd15099c028c6fcvboxsync#define TIDAC_TVP_3030_ID 0x30