x11include/xorg-server-1.7.7/vgaHW.h

45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/*
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Copyright (c) 1997,1998 The XFree86 Project, Inc.
45e9809aff7304721fddb95654901b32195c9c7avboxsync *
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Loosely based on code bearing the following copyright:
45e9809aff7304721fddb95654901b32195c9c7avboxsync *
45e9809aff7304721fddb95654901b32195c9c7avboxsync *   Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany.
45e9809aff7304721fddb95654901b32195c9c7avboxsync *
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Author: Dirk Hohndel
45e9809aff7304721fddb95654901b32195c9c7avboxsync */
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#ifndef _VGAHW_H
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define _VGAHW_H
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#include <X11/X.h>
45e9809aff7304721fddb95654901b32195c9c7avboxsync#include "misc.h"
45e9809aff7304721fddb95654901b32195c9c7avboxsync#include "input.h"
45e9809aff7304721fddb95654901b32195c9c7avboxsync#include "scrnintstr.h"
45e9809aff7304721fddb95654901b32195c9c7avboxsync#include "colormapst.h"
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#include "xf86str.h"
45e9809aff7304721fddb95654901b32195c9c7avboxsync#include "xf86Pci.h"
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#include "xf86DDC.h"
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#include "globals.h"
45e9809aff7304721fddb95654901b32195c9c7avboxsync#include <X11/extensions/dpmsconst.h>
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT int vgaHWGetIndex(void);
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/*
45e9809aff7304721fddb95654901b32195c9c7avboxsync * access macro
45e9809aff7304721fddb95654901b32195c9c7avboxsync */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGAHWPTR(p) ((vgaHWPtr)((p)->privates[vgaHWGetIndex()].ptr))
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* Standard VGA registers */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_ATTR_INDEX      0x3C0
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_ATTR_DATA_W     0x3C0
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_ATTR_DATA_R     0x3C1
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_IN_STAT_0       0x3C2       /* read */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_MISC_OUT_W      0x3C2       /* write */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_ENABLE      0x3C3
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_SEQ_INDEX       0x3C4
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_SEQ_DATA        0x3C5
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_DAC_MASK        0x3C6
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_DAC_READ_ADDR   0x3C7
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_DAC_WRITE_ADDR  0x3C8
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_DAC_DATA        0x3C9
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_FEATURE_R       0x3CA       /* read */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_MISC_OUT_R      0x3CC       /* read */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_GRAPH_INDEX     0x3CE
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_GRAPH_DATA      0x3CF
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_IOBASE_MONO     0x3B0
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_IOBASE_COLOR    0x3D0
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_CRTC_INDEX_OFFSET   0x04
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_CRTC_DATA_OFFSET    0x05
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_IN_STAT_1_OFFSET    0x0A        /* read */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_FEATURE_W_OFFSET    0x0A        /* write */
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* default number of VGA registers stored internally */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_NUM_CRTC 25
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_NUM_SEQ 5
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_NUM_GFX 9
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_NUM_ATTR 21
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* Flags for vgaHWSave() and vgaHWRestore() */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_SR_MODE     0x01
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_SR_FONTS        0x02
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_SR_CMAP     0x04
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_SR_ALL      (VGA_SR_MODE | VGA_SR_FONTS | VGA_SR_CMAP)
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* Defaults for the VGA memory window */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_DEFAULT_PHYS_ADDR   0xA0000
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGA_DEFAULT_MEM_SIZE    (64 * 1024)
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/*
45e9809aff7304721fddb95654901b32195c9c7avboxsync * vgaRegRec contains settings of standard VGA registers.
45e9809aff7304721fddb95654901b32195c9c7avboxsync */
45e9809aff7304721fddb95654901b32195c9c7avboxsynctypedef struct {
45e9809aff7304721fddb95654901b32195c9c7avboxsync    unsigned char MiscOutReg;     /* */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    unsigned char *CRTC;       /* Crtc Controller */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    unsigned char *Sequencer;   /* Video Sequencer */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    unsigned char *Graphics;    /* Video Graphics */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    unsigned char *Attribute;  /* Video Atribute */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    unsigned char DAC[768];       /* Internal Colorlookuptable */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    unsigned char numCRTC;  /* number of CRTC registers, def=VGA_NUM_CRTC */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    unsigned char numSequencer; /* number of seq registers, def=VGA_NUM_SEQ */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    unsigned char numGraphics;  /* number of gfx registers, def=VGA_NUM_GFX */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    unsigned char numAttribute; /* number of attr registers, def=VGA_NUM_ATTR */
45e9809aff7304721fddb95654901b32195c9c7avboxsync} vgaRegRec, *vgaRegPtr;
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsynctypedef struct _vgaHWRec *vgaHWPtr;
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsynctypedef void (*vgaHWWriteIndexProcPtr)(vgaHWPtr hwp, CARD8 indx, CARD8 value);
45e9809aff7304721fddb95654901b32195c9c7avboxsynctypedef CARD8 (*vgaHWReadIndexProcPtr)(vgaHWPtr hwp, CARD8 indx);
45e9809aff7304721fddb95654901b32195c9c7avboxsynctypedef void (*vgaHWWriteProcPtr)(vgaHWPtr hwp, CARD8 value);
45e9809aff7304721fddb95654901b32195c9c7avboxsynctypedef CARD8 (*vgaHWReadProcPtr)(vgaHWPtr hwp);
45e9809aff7304721fddb95654901b32195c9c7avboxsynctypedef void (*vgaHWMiscProcPtr)(vgaHWPtr hwp);
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/*
45e9809aff7304721fddb95654901b32195c9c7avboxsync * vgaHWRec contains per-screen information required by the vgahw module.
45e9809aff7304721fddb95654901b32195c9c7avboxsync *
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Note, the palette referred to by the paletteEnabled, enablePalette and
45e9809aff7304721fddb95654901b32195c9c7avboxsync * disablePalette is the 16-entry (+overscan) EGA-compatible palette accessed
45e9809aff7304721fddb95654901b32195c9c7avboxsync * via the first 17 attribute registers and not the main 8-bit palette.
45e9809aff7304721fddb95654901b32195c9c7avboxsync */
45e9809aff7304721fddb95654901b32195c9c7avboxsynctypedef struct _vgaHWRec {
45e9809aff7304721fddb95654901b32195c9c7avboxsync    pointer         Base;       /* Address of "VGA" memory */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    int             MapSize;    /* Size of "VGA" memory */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    unsigned long       MapPhys;    /* phys location of VGA mem */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    int             IOBase;     /* I/O Base address */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    CARD8 *             MMIOBase;   /* Pointer to MMIO start */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    int             MMIOOffset; /* base + offset + vgareg
45e9809aff7304721fddb95654901b32195c9c7avboxsync                           = mmioreg */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    pointer         FontInfo1;  /* save area for fonts in
45e9809aff7304721fddb95654901b32195c9c7avboxsync                            plane 2 */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    pointer         FontInfo2;  /* save area for fonts in
45e9809aff7304721fddb95654901b32195c9c7avboxsync                            plane 3 */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    pointer         TextInfo;   /* save area for text */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaRegRec           SavedReg;   /* saved registers */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaRegRec           ModeReg;    /* register settings for
45e9809aff7304721fddb95654901b32195c9c7avboxsync                            current mode */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    Bool            ShowOverscan;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    Bool            paletteEnabled;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    Bool            cmapSaved;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    ScrnInfoPtr         pScrn;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWWriteIndexProcPtr  writeCrtc;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWReadIndexProcPtr   readCrtc;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWWriteIndexProcPtr  writeGr;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWReadIndexProcPtr   readGr;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWReadProcPtr            readST00;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWReadProcPtr            readST01;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWReadProcPtr            readFCR;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWWriteProcPtr           writeFCR;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWWriteIndexProcPtr  writeAttr;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWReadIndexProcPtr   readAttr;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWWriteIndexProcPtr  writeSeq;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWReadIndexProcPtr   readSeq;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWWriteProcPtr       writeMiscOut;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWReadProcPtr        readMiscOut;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWMiscProcPtr        enablePalette;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWMiscProcPtr        disablePalette;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWWriteProcPtr       writeDacMask;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWReadProcPtr        readDacMask;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWWriteProcPtr       writeDacWriteAddr;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWWriteProcPtr       writeDacReadAddr;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWWriteProcPtr       writeDacData;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWReadProcPtr        readDacData;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    pointer                     ddc;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    IOADDRESS           PIOOffset;  /* offset + vgareg
45e9809aff7304721fddb95654901b32195c9c7avboxsync                           = pioreg */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWReadProcPtr        readEnable;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    vgaHWWriteProcPtr       writeEnable;
45e9809aff7304721fddb95654901b32195c9c7avboxsync    struct pci_device          *dev;
45e9809aff7304721fddb95654901b32195c9c7avboxsync} vgaHWRec;
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* Some macros that VGA drivers can use in their ChipProbe() function */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define VGAHW_GET_IOBASE()  ((inb(VGA_MISC_OUT_R) & 0x01) ?           \
45e9809aff7304721fddb95654901b32195c9c7avboxsync                     VGA_IOBASE_COLOR : VGA_IOBASE_MONO)
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define OVERSCAN 0x11       /* Index of OverScan register */
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* Flags that define how overscan correction should take place */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define KGA_FIX_OVERSCAN  1   /* overcan correction required */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define KGA_ENABLE_ON_ZERO 2  /* if possible enable display at beginning */
45e9809aff7304721fddb95654901b32195c9c7avboxsync                              /* of next scanline/frame                  */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define KGA_BE_TOT_DEC 4      /* always fix problem by setting blank end */
45e9809aff7304721fddb95654901b32195c9c7avboxsync                  /* to total - 1                            */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BIT_PLANE 3     /* Which plane we write to in mono mode */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BITS_PER_GUN 6
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define COLORMAP_SIZE 256
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#if defined(__powerpc__) || defined(__arm__) || defined(__s390__)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define DACDelay(hw) /* No legacy VGA support */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#else
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define DACDelay(hw)                                  \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    do {                                      \
45e9809aff7304721fddb95654901b32195c9c7avboxsync        (void)inb((hw)->PIOOffset + (hw)->IOBase + VGA_IN_STAT_1_OFFSET); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync        (void)inb((hw)->PIOOffset + (hw)->IOBase + VGA_IN_STAT_1_OFFSET); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    } while (0)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* Function Prototypes */
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* vgaHW.c */
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsynctypedef void vgaHWProtectProc(ScrnInfoPtr, Bool);
45e9809aff7304721fddb95654901b32195c9c7avboxsynctypedef void vgaHWBlankScreenProc(ScrnInfoPtr, Bool);
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWSetStdFuncs(vgaHWPtr hwp);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWSetMmioFuncs(vgaHWPtr hwp, CARD8 *base, int offset);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWProtect(ScrnInfoPtr pScrn, Bool on);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT vgaHWProtectProc *vgaHWProtectWeak(void);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT Bool vgaHWSaveScreen(ScreenPtr pScreen, int mode);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWBlankScreen(ScrnInfoPtr pScrn, Bool on);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT vgaHWBlankScreenProc *vgaHWBlankScreenWeak(void);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWSeqReset(vgaHWPtr hwp, Bool start);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWRestoreFonts(ScrnInfoPtr scrninfp, vgaRegPtr restore);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWRestoreMode(ScrnInfoPtr scrninfp, vgaRegPtr restore);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWRestoreColormap(ScrnInfoPtr scrninfp, vgaRegPtr restore);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWRestore(ScrnInfoPtr scrninfp, vgaRegPtr restore, int flags);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWSaveFonts(ScrnInfoPtr scrninfp, vgaRegPtr save);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWSaveMode(ScrnInfoPtr scrninfp, vgaRegPtr save);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWSaveColormap(ScrnInfoPtr scrninfp, vgaRegPtr save);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWSave(ScrnInfoPtr scrninfp, vgaRegPtr save, int flags);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT Bool vgaHWInit(ScrnInfoPtr scrnp, DisplayModePtr mode);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT Bool vgaHWSetRegCounts(ScrnInfoPtr scrp, int numCRTC, int numSequencer,
45e9809aff7304721fddb95654901b32195c9c7avboxsync                    int numGraphics, int numAttribute);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT Bool vgaHWCopyReg(vgaRegPtr dst, vgaRegPtr src);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT Bool vgaHWGetHWRec(ScrnInfoPtr scrp);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWFreeHWRec(ScrnInfoPtr scrp);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT Bool vgaHWMapMem(ScrnInfoPtr scrp);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWUnmapMem(ScrnInfoPtr scrp);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWGetIOBase(vgaHWPtr hwp);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWLock(vgaHWPtr hwp);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWUnlock(vgaHWPtr hwp);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWEnable(vgaHWPtr hwp);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWDisable(vgaHWPtr hwp);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWDPMSSet(ScrnInfoPtr pScrn, int PowerManagementMode, int flags);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT Bool vgaHWHandleColormaps(ScreenPtr pScreen);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT void vgaHWddc1SetSpeed(ScrnInfoPtr pScrn, xf86ddcSpeed speed);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT CARD32 vgaHWHBlankKGA(DisplayModePtr mode, vgaRegPtr regp, int nBits,
45e9809aff7304721fddb95654901b32195c9c7avboxsync           unsigned int Flags);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT CARD32 vgaHWVBlankKGA(DisplayModePtr mode, vgaRegPtr regp, int nBits,
45e9809aff7304721fddb95654901b32195c9c7avboxsync           unsigned int Flags);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT Bool vgaHWAllocDefaultRegs(vgaRegPtr regp);
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT DDC1SetSpeedProc vgaHWddc1SetSpeedWeak(void);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern _X_EXPORT SaveScreenProcPtr vgaHWSaveScreenWeak(void);
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif /* _VGAHW_H */