040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync * Copyright IBM Corporation 1987,1988,1989
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync * All Rights Reserved
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync * Permission to use, copy, modify, and distribute this software and its
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync * documentation for any purpose and without fee is hereby granted,
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync * provided that the above copyright notice appear in all copies and that
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync * both that copyright notice and this permission notice appear in
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync * supporting documentation, and that the name of IBM not be
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync * used in advertising or publicity pertaining to distribution of the
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync * software without specific, written prior permission.
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync * IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync * IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync * SOFTWARE.
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define SET_BYTE_REGISTER( ioport, value ) outb( ioport, value )
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define SET_INDEX_REGISTER( ioport, value ) SET_BYTE_REGISTER( ioport, value )
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define SET_DATA_REGISTER( ioport, value ) SET_BYTE_REGISTER( ioport, value )
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync/* GJA -- deleted RTIO and ATRIO case here, so that a PCIO #define became
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync * superfluous.
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define SET_INDEXED_REGISTER(RegGroup, Index, Value) \
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync/* There is a jumper on the ega to change this to 0x200 instead !! */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#if 0 /* This is now a stack variable, as needed */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync SET_INDEX_REGISTER( AttributeIndexRegister, index )
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync SET_BYTE_REGISTER( AttributeDataWriteRegister, value )
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync /* Graphics Registers 03CE & 03CF */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync SET_INDEXED_REGISTER( GraphicsRegister, index, value )
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync/* Sequencer Registers 03C4 & 03C5 */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync SET_INDEX_REGISTER( SequencerIndexRegister, index )
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync SET_INDEXED_REGISTER( SequencerRegister, index, value )
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync/* BIT CONSTANTS FOR THE VGA/EGA HARDWARE */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync/* for the Graphics' Data_Rotate Register */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define VGA_COPY_MODE ( 0 << VGA_ROTATE_FUNC_SHIFT ) /* 0x00 */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define VGA_AND_MODE ( 1 << VGA_ROTATE_FUNC_SHIFT ) /* 0x08 */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define VGA_OR_MODE ( 2 << VGA_ROTATE_FUNC_SHIFT ) /* 0x10 */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define VGA_XOR_MODE ( 3 << VGA_ROTATE_FUNC_SHIFT ) /* 0x18 */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync/* for the Graphics' Graphics_Mode Register */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define VGA_READ_MODE_0 ( 0 << VGA_READ_MODE_SHIFT )
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define VGA_READ_MODE_1 ( 1 << VGA_READ_MODE_SHIFT )
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync/* I/O port address define for extended EGC */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define EGC_PLANE 0x4a0 /* EGC active plane select */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define EGC_MODE 0x4a4 /* EGC Mode register & ROP */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define EGC_AND_INV_MODE 0x2c2c /* (S&P&~D)|(~S&D) */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define EGC_OR_INV_MODE 0x2cbc /* S&(P|~D)|(~S&D) */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define EGC_XOR_MODE 0x2c6c /* (S&(P&~D|~P&D))|(~S&D) */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define EGC_XOR_INV_MODE 0x2c9c /* (S&(P&D)|(~P&~D))|(~S&D) */