040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#include <xf86RamDac.h>
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsyncunsigned long TIramdacCalculateMNPForClock(unsigned long RefClock,
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync unsigned long ReqClock, char IsPixClock, unsigned long MinClock,
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync unsigned long MaxClock, unsigned long *rM, unsigned long *rN,
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync unsigned long *rP);
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsyncRamDacHelperRecPtr TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs);
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsyncvoid TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec);
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsyncvoid TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec);
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsyncvoid TIramdac3026SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec);
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsyncvoid TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec);
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsyncunsigned long TIramdac3030CalculateMNPForClock(unsigned long RefClock,
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync unsigned long ReqClock, char IsPixClock, unsigned long MinClock,
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync unsigned long MaxClock, unsigned long *rM, unsigned long *rN,
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync unsigned long *rP);
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsyncvoid TIramdacHWCursorInit(xf86CursorInfoPtr infoPtr);
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsyncvoid TIramdacLoadPalette( ScrnInfoPtr pScrn, int numColors, int *indices,
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync LOCO *colors, VisualPtr pVisual);
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsynctypedef void TIramdacLoadPaletteProc(ScrnInfoPtr, int, int *, LOCO *,
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync VisualPtr);
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsyncTIramdacLoadPaletteProc *TIramdacLoadPaletteWeak(void);
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TI3030_RAMDAC (VENDOR_TI << 16) | 0x00
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TI3026_RAMDAC (VENDOR_TI << 16) | 0x01
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync/*
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync * TI Ramdac registers
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_rev 0x01
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_ind_curs_ctrl 0x06
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_byte_router_ctrl 0x07
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_latch_ctrl 0x0f
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_true_color_ctrl 0x18
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_multiplex_ctrl 0x19
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_clock_select 0x1a
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_palette_page 0x1c
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_general_ctrl 0x1d
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_misc_ctrl 0x1e
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_pll_addr 0x2c
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_pll_pixel_data 0x2d
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_pll_memory_data 0x2e
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_pll_loop_data 0x2f
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_key_over_low 0x30
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_key_over_high 0x31
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_key_red_low 0x32
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_key_red_high 0x33
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_key_green_low 0x34
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_key_green_high 0x35
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_key_blue_low 0x36
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_key_blue_high 0x37
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_key_ctrl 0x38
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_clock_ctrl 0x39
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_sense_test 0x3a
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_test_mode_data 0x3b
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_crc_remain_lsb 0x3c
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_crc_remain_msb 0x3d
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_crc_bit_select 0x3e
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_id 0x3f
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync/* These are pll values that are accessed via TIDAC_pll_pixel_data */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_PIXEL_N 0x80
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_PIXEL_M 0x81
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_PIXEL_P 0x82
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_PIXEL_VALID 0x83
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync/* These are pll values that are accessed via TIDAC_pll_loop_data */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_LOOP_N 0x90
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_LOOP_M 0x91
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_LOOP_P 0x92
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_LOOP_VALID 0x93
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync/* Direct mapping addresses */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_INDEX 0xa0
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_PALETTE_DATA 0xa1
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_READ_MASK 0xa2
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_READ_ADDR 0xa3
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_CURS_WRITE_ADDR 0xa4
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_CURS_COLOR 0xa5
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_CURS_READ_ADDR 0xa7
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_CURS_CTL 0xa9
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_INDEXED_DATA 0xaa
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_CURS_RAM_DATA 0xab
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_CURS_XLOW 0xac
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_CURS_XHIGH 0xad
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_CURS_YLOW 0xae
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_CURS_YHIGH 0xaf
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_sw_reset 0xff
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync/* Constants */
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_TVP_3026_ID 0x26
040abec2534dadc53ebc8fa378ef03f4feecb7dbvboxsync#define TIDAC_TVP_3030_ID 0x30