x11include/xorg-server-1.4.2/mergerop.h

45e9809aff7304721fddb95654901b32195c9c7avboxsync/*
45e9809aff7304721fddb95654901b32195c9c7avboxsync *
45e9809aff7304721fddb95654901b32195c9c7avboxsyncCopyright 1989, 1998  The Open Group
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45e9809aff7304721fddb95654901b32195c9c7avboxsyncPermission to use, copy, modify, distribute, and sell this software and its
45e9809aff7304721fddb95654901b32195c9c7avboxsyncdocumentation for any purpose is hereby granted without fee, provided that
45e9809aff7304721fddb95654901b32195c9c7avboxsyncthe above copyright notice appear in all copies and that both that
45e9809aff7304721fddb95654901b32195c9c7avboxsynccopyright notice and this permission notice appear in supporting
45e9809aff7304721fddb95654901b32195c9c7avboxsyncdocumentation.
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsyncThe above copyright notice and this permission notice shall be included in
45e9809aff7304721fddb95654901b32195c9c7avboxsyncall copies or substantial portions of the Software.
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsyncTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
45e9809aff7304721fddb95654901b32195c9c7avboxsyncIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
45e9809aff7304721fddb95654901b32195c9c7avboxsyncFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
45e9809aff7304721fddb95654901b32195c9c7avboxsyncOPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
45e9809aff7304721fddb95654901b32195c9c7avboxsyncAN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
45e9809aff7304721fddb95654901b32195c9c7avboxsyncCONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsyncExcept as contained in this notice, the name of The Open Group shall not be
45e9809aff7304721fddb95654901b32195c9c7avboxsyncused in advertising or otherwise to promote the sale, use or other dealings
45e9809aff7304721fddb95654901b32195c9c7avboxsyncin this Software without prior written authorization from The Open Group.
45e9809aff7304721fddb95654901b32195c9c7avboxsync *
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Author:  Keith Packard, MIT X Consortium
45e9809aff7304721fddb95654901b32195c9c7avboxsync */
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#ifdef HAVE_DIX_CONFIG_H
45e9809aff7304721fddb95654901b32195c9c7avboxsync#include <dix-config.h>
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#ifndef _MERGEROP_H_
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define _MERGEROP_H_
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#ifndef GXcopy
45e9809aff7304721fddb95654901b32195c9c7avboxsync#include <X11/X.h>
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsynctypedef struct _mergeRopBits {
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits   ca1, cx1, ca2, cx2;
45e9809aff7304721fddb95654901b32195c9c7avboxsync} mergeRopRec, *mergeRopPtr;
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern mergeRopRec  mergeRopBits[16];
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern mergeRopPtr  mergeGetRopBits(int i);
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#if defined(PPW) && defined(PGSZ) && (PPW != PGSZ)  /* cfb */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define DeclareMergeRop() MfbBits   _ca1 = 0, _cx1 = 0, _ca2 = 0, _cx2 = 0;
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define DeclarePrebuiltMergeRop()   MfbBits _cca, _ccx;
45e9809aff7304721fddb95654901b32195c9c7avboxsync#if PSZ == 24  /* both for PGSZ == 32 and 64 */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define DeclareMergeRop24() \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits   _ca1u[4], _cx1u[4], _ca2u[4], _cx2u[4];
45e9809aff7304721fddb95654901b32195c9c7avboxsync    /*    int _unrollidx[3]={0,0,1,2};*/
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define DeclarePrebuiltMergeRop24() MfbBits _ccau[4], _ccxu[4];
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif /* PSZ == 24 */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#else /* mfb */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define DeclareMergeRop() MfbBits   _ca1 = 0, _cx1 = 0, _ca2 = 0, _cx2 = 0;
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define DeclarePrebuiltMergeRop()   MfbBits _cca, _ccx;
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#if defined(PPW) && defined(PGSZ) && (PPW != PGSZ)  /* cfb */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define InitializeMergeRop(alu,pm) {\
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits   _pm; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    mergeRopPtr  _bits; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _pm = PFILL(pm); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _bits = mergeGetRopBits(alu); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _ca1 = _bits->ca1 &  _pm; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _cx1 = _bits->cx1 | ~_pm; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _ca2 = _bits->ca2 &  _pm; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _cx2 = _bits->cx2 &  _pm; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync}
45e9809aff7304721fddb95654901b32195c9c7avboxsync#if PSZ == 24
45e9809aff7304721fddb95654901b32195c9c7avboxsync#if (BITMAP_BIT_ORDER == MSBFirst)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define InitializeMergeRop24(alu,pm) {\
45e9809aff7304721fddb95654901b32195c9c7avboxsync    register int i; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    register MfbBits _pm = (pm) & 0xFFFFFF; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    mergeRopPtr  _bits = mergeGetRopBits(alu); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _bits_ca1 = _bits->ca1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _bits_cx1 = _bits->cx1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _bits_ca2 = _bits->ca2; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _bits_cx2 = _bits->cx2; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _pm = (_pm << 8) | (_pm >> 16); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    for(i = 0; i < 4; i++){ \
45e9809aff7304721fddb95654901b32195c9c7avboxsync      _ca1u[i] = _bits_ca1 &  _pm; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync      _cx1u[i] = _bits_cx1 | ~_pm; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync      _ca2u[i] = _bits_ca2 &  _pm; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync      _cx2u[i] = _bits_cx2 &  _pm; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync      _pm = (_pm << 16)|(_pm >> 8); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    } \
45e9809aff7304721fddb95654901b32195c9c7avboxsync}
45e9809aff7304721fddb95654901b32195c9c7avboxsync#else   /*(BITMAP_BIT_ORDER == LSBFirst)*/
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define InitializeMergeRop24(alu,pm) {\
45e9809aff7304721fddb95654901b32195c9c7avboxsync    register int i; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    register MfbBits _pm = (pm) & cfbmask[0]; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    mergeRopPtr  _bits = mergeGetRopBits(alu); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _bits_ca1 = _bits->ca1 & cfbmask[0]; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _bits_cx1 = _bits->cx1 & cfbmask[0]; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _bits_ca2 = _bits->ca2 & cfbmask[0]; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _bits_cx2 = _bits->cx2 & cfbmask[0]; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _pm |= (_pm << 24); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _bits_ca1 |= (_bits->ca1 << 24); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _bits_cx1 |= (_bits->cx1 << 24); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _bits_ca2 |= (_bits->ca2 << 24); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _bits_cx2 |= (_bits->cx2 << 24); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    for(i = 0; i < 4; i++){ \
45e9809aff7304721fddb95654901b32195c9c7avboxsync      _ca1u[i] = _bits_ca1 &  _pm; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync      _cx1u[i] = _bits_cx1 | ~_pm; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync      _ca2u[i] = _bits_ca2 &  _pm; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync      _cx2u[i] = _bits_cx2 &  _pm; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync      _pm = (_pm << 16)|(_pm >> 8); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    } \
45e9809aff7304721fddb95654901b32195c9c7avboxsync}
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif  /*(BITMAP_BIT_ORDER == MSBFirst)*/
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif /* PSZ == 24 */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#else /* mfb */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define InitializeMergeRop(alu,pm) {\
45e9809aff7304721fddb95654901b32195c9c7avboxsync    mergeRopPtr  _bits; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _bits = mergeGetRopBits(alu); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _ca1 = _bits->ca1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _cx1 = _bits->cx1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _ca2 = _bits->ca2; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _cx2 = _bits->cx2; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync}
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* AND has higher precedence than XOR */
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define DoMergeRop(src, dst) \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (((dst) & (((src) & _ca1) ^ _cx1)) ^ (((src) & _ca2) ^ _cx2))
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define DoMergeRop24u(src, dst, i)                  \
45e9809aff7304721fddb95654901b32195c9c7avboxsync(((dst) & (((src) & _ca1u[i]) ^ _cx1u[i])) ^ (((src) & _ca2u[i]) ^ _cx2u[i]))
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define DoMaskMergeRop24(src, dst, mask, index)  {\
45e9809aff7304721fddb95654901b32195c9c7avboxsync    register int idx = ((index) & 3)<< 1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _src0 = (src);\
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _src1 = (_src0 & _ca1) ^ _cx1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _src2 = (_src0 & _ca2) ^ _cx2; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) = (((*(dst)) & cfbrmask[idx]) | (((*(dst)) & cfbmask[idx]) & \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (((( _src1 |(~mask))<<cfb24Shift[idx])&cfbmask[idx]) ^ \
45e9809aff7304721fddb95654901b32195c9c7avboxsync     ((( _src2&(mask))<<cfb24Shift[idx])&cfbmask[idx])))); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    idx++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (dst)++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) = (((*(dst)) & cfbrmask[idx]) | (((*(dst)) & cfbmask[idx]) & \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    ((((_src1 |(~mask))>>cfb24Shift[idx])&cfbmask[idx]) ^ \
45e9809aff7304721fddb95654901b32195c9c7avboxsync     (((_src2 &(mask))>>cfb24Shift[idx])&cfbmask[idx])))); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (dst)--; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    }
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define DoMaskMergeRop(src, dst, mask) \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (((dst) & ((((src) & _ca1) ^ _cx1) | ~(mask))) ^ ((((src) & _ca2) ^ _cx2) & (mask)))
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define DoMaskMergeRop24u(src, dst, mask, i)                            \
45e9809aff7304721fddb95654901b32195c9c7avboxsync(((dst) & ((((src) & _ca1u[(i)]) ^ _cx1u[(i)]) | ~(mask))) ^ ((((src) & _ca2u[(i)]) ^ _cx2u[(i)]) & (mask)))
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define DoMergeRop24(src,dst,index) {\
45e9809aff7304721fddb95654901b32195c9c7avboxsync    register int idx = ((index) & 3)<< 1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _src0 = (src);\
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _src1 = (_src0 & _ca1) ^ _cx1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _src2 = (_src0 & _ca2) ^ _cx2; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) = (((*(dst)) & cfbrmask[idx]) | ((((*(dst)) & cfbmask[idx]) & \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    ((_src1 << cfb24Shift[idx])&cfbmask[idx])) ^ \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    ((_src2 << cfb24Shift[idx])&cfbmask[idx]))); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    idx++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (dst)++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) = (((*(dst)) & cfbrmask[idx]) | ((((*(dst)) & cfbmask[idx]) & \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    ((_src1 >> cfb24Shift[idx])&cfbmask[idx])) ^ \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    ((_src2 >> cfb24Shift[idx])&cfbmask[idx]))); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (dst)--; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    }
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define DoPrebuiltMergeRop(dst) (((dst) & _cca) ^ _ccx)
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define DoPrebuiltMergeRop24(dst,index) { \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    register int idx = ((index) & 3)<< 1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) = (((*(dst)) & cfbrmask[idx]) | ((((*(dst)) & cfbmask[idx]) &\
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (( _cca <<cfb24Shift[idx])&cfbmask[idx])) ^ \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (( _ccx <<cfb24Shift[idx])&cfbmask[idx]))); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    idx++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (dst)++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) = (((*(dst)) & cfbrmask[idx]) | ((((*(dst)) & cfbmask[idx]) &\
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (( _cca >>cfb24Shift[idx])&cfbmask[idx])) ^ \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (( _ccx >>cfb24Shift[idx])&cfbmask[idx]))); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (dst)--; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    }
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define DoMaskPrebuiltMergeRop(dst,mask) \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (((dst) & (_cca | ~(mask))) ^ (_ccx & (mask)))
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define PrebuildMergeRop(src) ((_cca = ((src) & _ca1) ^ _cx1), \
45e9809aff7304721fddb95654901b32195c9c7avboxsync                   (_ccx = ((src) & _ca2) ^ _cx2))
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#ifndef MROP
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP 0
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define Mclear      (1<<GXclear)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define Mand        (1<<GXand)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MandReverse (1<<GXandReverse)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define Mcopy       (1<<GXcopy)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MandInverted    (1<<GXandInverted)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define Mnoop       (1<<GXnoop)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define Mxor        (1<<GXxor)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define Mor     (1<<GXor)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define Mnor        (1<<GXnor)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define Mequiv      (1<<GXequiv)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define Minvert     (1<<GXinvert)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MorReverse  (1<<GXorReverse)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define McopyInverted   (1<<GXcopyInverted)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MorInverted (1<<GXorInverted)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define Mnand       (1<<GXnand)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define Mset        (1<<GXset)
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PIXEL24(pix, idx) \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (((*(pix) & cfbmask[(idx)<<1]) >> cfb24Shift[(idx)<<1])| \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    ((*((pix)+1) & cfbmask[((idx)<<1)+1]) << cfb24Shift[((idx)<<1)+1]))
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_SOLID24P(src,dst,sindex, index) \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MROP_SOLID24(MROP_PIXEL24(src,sindex),dst,index)
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_MASK24P(src,dst,mask,sindex,index) \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MROP_MASK24(MROP_PIXEL24(src,sindex),dst,mask,index)
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#if (MROP) == Mcopy
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_DECLARE()
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_DECLARE_REG()
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_INITIALIZE(alu,pm)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_SOLID(src,dst) (src)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_SOLID24(src,dst,index)     {\
45e9809aff7304721fddb95654901b32195c9c7avboxsync    register int idx = ((index) & 3)<< 1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _src = (src); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) = (*(dst) & cfbrmask[idx])|((_src<<cfb24Shift[idx])&cfbmask[idx]); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    idx++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *((dst)+1) = (*((dst)+1) & cfbrmask[idx])|((_src>>cfb24Shift[idx])&cfbmask[idx]); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    }
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_MASK(src,dst,mask) (((dst) & ~(mask)) | ((src) & (mask)))
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_MASK24(src,dst,mask,index) {\
45e9809aff7304721fddb95654901b32195c9c7avboxsync    register int idx = ((index) & 3)<< 1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _src = (src); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) = (*(dst) & cfbrmask[idx] &(~(((mask)<< cfb24Shift[idx])&cfbmask[idx])) | \
45e9809aff7304721fddb95654901b32195c9c7avboxsync        (((_src &(mask))<<cfb24Shift[idx])&cfbmask[idx])); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    idx++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *((dst)+1) = (*((dst)+1) & cfbrmask[idx] &(~(((mask)>>cfb24Shift[idx])&cfbmask[idx])) | \
45e9809aff7304721fddb95654901b32195c9c7avboxsync        (((_src&(mask))>>cfb24Shift[idx])&cfbmask[idx])); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    }
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_NAME(prefix)   MROP_NAME_CAT(prefix,Copy)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#if (MROP) == McopyInverted
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_DECLARE()
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_DECLARE_REG()
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_INITIALIZE(alu,pm)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_SOLID(src,dst) (~(src))
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_SOLID24(src,dst,index)     {\
45e9809aff7304721fddb95654901b32195c9c7avboxsync    register int idx = ((index) & 3)<< 1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _src = ~(src); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) = (*(dst) & cfbrmask[idx])|((_src << cfb24Shift[idx])&cfbmask[idx]); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    idx++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (dst)++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) = (*(dst) & cfbrmask[idx])|((_src >>cfb24Shift[idx])&cfbmask[idx]); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (dst)--; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    }
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_MASK(src,dst,mask) (((dst) & ~(mask)) | ((~(src)) & (mask)))
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_MASK24(src,dst,mask,index) {\
45e9809aff7304721fddb95654901b32195c9c7avboxsync    register int idx = ((index) & 3)<< 1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _src = ~(src); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) = (*(dst) & cfbrmask[idx] &(~(((mask)<< cfb24Shift[idx])&cfbmask[idx])) | \
45e9809aff7304721fddb95654901b32195c9c7avboxsync        (((_src &(mask))<<cfb24Shift[idx])&cfbmask[idx])); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    idx++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (dst)++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) = (*(dst) & cfbrmask[idx] &(~(((mask)>>cfb24Shift[idx])&cfbmask[idx])) | \
45e9809aff7304721fddb95654901b32195c9c7avboxsync        ((((_src & (mask))>>cfb24Shift[idx])&cfbmask[idx])); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (dst)--; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    }
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_NAME(prefix)   MROP_NAME_CAT(prefix,CopyInverted)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#if (MROP) == Mxor
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_DECLARE()
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_DECLARE_REG()
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_INITIALIZE(alu,pm)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_SOLID(src,dst) ((src) ^ (dst))
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_SOLID24(src,dst,index)     {\
45e9809aff7304721fddb95654901b32195c9c7avboxsync    register int idx = ((index) & 3)<< 1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _src = (src); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) ^= ((_src << cfb24Shift[idx])&cfbmask[idx]); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    idx++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (dst)++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) ^= ((_src >>cfb24Shift[idx])&cfbmask[idx]); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (dst)--; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    }
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_MASK(src,dst,mask) (((src) & (mask)) ^ (dst))
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_MASK24(src,dst,mask,index) {\
45e9809aff7304721fddb95654901b32195c9c7avboxsync    register int idx = ((index) & 3)<< 1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) ^= ((((src)&(mask))<<cfb24Shift[idx])&cfbmask[idx]); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    idx++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (dst)++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) ^= ((((src)&(mask))>>cfb24Shift[idx])&cfbmask[idx]); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (dst)--; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    }
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_NAME(prefix)   MROP_NAME_CAT(prefix,Xor)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#if (MROP) == Mor
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_DECLARE()
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_DECLARE_REG()
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_INITIALIZE(alu,pm)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_SOLID(src,dst) ((src) | (dst))
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_SOLID24(src,dst,index)     {\
45e9809aff7304721fddb95654901b32195c9c7avboxsync    register int idx = ((index) & 3)<< 1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) |= (((src)<<cfb24Shift[idx])&cfbmask[idx]); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    idx++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (dst)++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) |= (((src)>>cfb24Shift[idx])&cfbmask[idx]); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (dst)--; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    }
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_MASK(src,dst,mask) (((src) & (mask)) | (dst))
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_MASK24(src,dst,mask,index) {\
45e9809aff7304721fddb95654901b32195c9c7avboxsync    register int idx = ((index) & 3)<< 1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    MfbBits _src = (src); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) |= (((_src &(mask))<<cfb24Shift[idx])&cfbmask[idx]); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    idx++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (dst)++; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    *(dst) |= (((_src &(mask))>>cfb24Shift[idx])&cfbmask[idx]); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (dst)--; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    }
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_NAME(prefix)   MROP_NAME_CAT(prefix,Or)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#if (MROP) == (Mcopy|Mxor|MandReverse|Mor)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_DECLARE()  MfbBits _ca1 = 0, _cx1 = 0;
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_DECLARE_REG()  register MROP_DECLARE()
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_INITIALIZE(alu,pm) { \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    mergeRopPtr  _bits; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _bits = mergeGetRopBits(alu); \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _ca1 = _bits->ca1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    _cx1 = _bits->cx1; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync}
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_SOLID(src,dst) \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (((dst) & (((src) & _ca1) ^ _cx1)) ^ (src))
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_MASK(src,dst,mask) \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    (((dst) & ((((src) & _ca1) ^ _cx1)) | (~(mask)) ^ ((src) & (mask))))
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_NAME(prefix)   MROP_NAME_CAT(prefix,CopyXorAndReverseOr)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PREBUILD(src)  PrebuildMergeRop(src)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PREBUILT_DECLARE() DeclarePrebuiltMergeRop()
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PREBUILT_SOLID(src,dst)    DoPrebuiltMergeRop(dst)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PREBUILT_SOLID24(src,dst,index)    DoPrebuiltMergeRop24(dst,index)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PREBUILT_MASK(src,dst,mask)    DoMaskPrebuiltMergeRop(dst,mask)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PREBUILT_MASK24(src,dst,mask,index)    DoMaskPrebuiltMergeRop24(dst,mask,index)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#if (MROP) == 0
45e9809aff7304721fddb95654901b32195c9c7avboxsync#if !defined(PSZ) || (PSZ != 24)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_DECLARE()  DeclareMergeRop()
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_DECLARE_REG()  register DeclareMergeRop()
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_INITIALIZE(alu,pm) InitializeMergeRop(alu,pm)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_SOLID(src,dst) DoMergeRop(src,dst)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_MASK(src,dst,mask) DoMaskMergeRop(src, dst, mask)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#else
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_DECLARE() \
45e9809aff7304721fddb95654901b32195c9c7avboxsync        DeclareMergeRop() \
45e9809aff7304721fddb95654901b32195c9c7avboxsync        DeclareMergeRop24()
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_DECLARE_REG() \
45e9809aff7304721fddb95654901b32195c9c7avboxsync        register DeclareMergeRop()\
45e9809aff7304721fddb95654901b32195c9c7avboxsync        DeclareMergeRop24()
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_INITIALIZE(alu,pm) \
45e9809aff7304721fddb95654901b32195c9c7avboxsync        InitializeMergeRop(alu,pm)\
45e9809aff7304721fddb95654901b32195c9c7avboxsync        InitializeMergeRop24(alu,pm)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_SOLID(src,dst) DoMergeRop24u(src,dst,((int)(&(dst)-pdstBase) % 3))
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_MASK(src,dst,mask) DoMaskMergeRop24u(src, dst, mask,((int)(&(dst) - pdstBase)%3))
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_SOLID24(src,dst,index) DoMergeRop24(src,dst,index)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_MASK24(src,dst,mask,index) DoMaskMergeRop24(src, dst, mask,index)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_NAME(prefix)   MROP_NAME_CAT(prefix,General)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PREBUILD(src)  PrebuildMergeRop(src)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PREBUILT_DECLARE() DeclarePrebuiltMergeRop()
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PREBUILT_SOLID(src,dst)    DoPrebuiltMergeRop(dst)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PREBUILT_SOLID24(src,dst,index)    DoPrebuiltMergeRop24(dst,index)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PREBUILT_MASK(src,dst,mask)    DoMaskPrebuiltMergeRop(dst,mask)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PREBUILT_MASK24(src,dst,mask,index) \
45e9809aff7304721fddb95654901b32195c9c7avboxsync    DoMaskPrebuiltMergeRop24(dst,mask,index)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#ifndef MROP_PREBUILD
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PREBUILD(src)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PREBUILT_DECLARE()
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PREBUILT_SOLID(src,dst)    MROP_SOLID(src,dst)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PREBUILT_SOLID24(src,dst,index)    MROP_SOLID24(src,dst,index)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PREBUILT_MASK(src,dst,mask)    MROP_MASK(src,dst,mask)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_PREBUILT_MASK24(src,dst,mask,index) MROP_MASK24(src,dst,mask,index)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#if !defined(UNIXCPP) || defined(ANSICPP)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_NAME_CAT(prefix,suffix)    prefix##suffix
45e9809aff7304721fddb95654901b32195c9c7avboxsync#else
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define MROP_NAME_CAT(prefix,suffix)    prefix/**/suffix
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif