45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#include <xf86RamDac.h>
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsyncunsigned long TIramdacCalculateMNPForClock(unsigned long RefClock,
45e9809aff7304721fddb95654901b32195c9c7avboxsync unsigned long ReqClock, char IsPixClock, unsigned long MinClock,
45e9809aff7304721fddb95654901b32195c9c7avboxsync unsigned long MaxClock, unsigned long *rM, unsigned long *rN,
45e9809aff7304721fddb95654901b32195c9c7avboxsync unsigned long *rP);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncRamDacHelperRecPtr TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncvoid TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncvoid TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncvoid TIramdac3026SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncvoid TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncunsigned long TIramdac3030CalculateMNPForClock(unsigned long RefClock,
45e9809aff7304721fddb95654901b32195c9c7avboxsync unsigned long ReqClock, char IsPixClock, unsigned long MinClock,
45e9809aff7304721fddb95654901b32195c9c7avboxsync unsigned long MaxClock, unsigned long *rM, unsigned long *rN,
45e9809aff7304721fddb95654901b32195c9c7avboxsync unsigned long *rP);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncvoid TIramdacHWCursorInit(xf86CursorInfoPtr infoPtr);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncvoid TIramdacLoadPalette( ScrnInfoPtr pScrn, int numColors, int *indices,
45e9809aff7304721fddb95654901b32195c9c7avboxsync LOCO *colors, VisualPtr pVisual);
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsynctypedef void TIramdacLoadPaletteProc(ScrnInfoPtr, int, int *, LOCO *,
45e9809aff7304721fddb95654901b32195c9c7avboxsync VisualPtr);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncTIramdacLoadPaletteProc *TIramdacLoadPaletteWeak(void);
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TI3030_RAMDAC (VENDOR_TI << 16) | 0x00
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TI3026_RAMDAC (VENDOR_TI << 16) | 0x01
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/*
45e9809aff7304721fddb95654901b32195c9c7avboxsync * TI Ramdac registers
45e9809aff7304721fddb95654901b32195c9c7avboxsync */
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_rev 0x01
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_ind_curs_ctrl 0x06
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_byte_router_ctrl 0x07
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_latch_ctrl 0x0f
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_true_color_ctrl 0x18
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_multiplex_ctrl 0x19
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_clock_select 0x1a
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_palette_page 0x1c
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_general_ctrl 0x1d
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_misc_ctrl 0x1e
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_pll_addr 0x2c
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_pll_pixel_data 0x2d
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_pll_memory_data 0x2e
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_pll_loop_data 0x2f
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_key_over_low 0x30
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_key_over_high 0x31
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_key_red_low 0x32
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_key_red_high 0x33
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_key_green_low 0x34
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_key_green_high 0x35
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_key_blue_low 0x36
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_key_blue_high 0x37
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_key_ctrl 0x38
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_clock_ctrl 0x39
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_sense_test 0x3a
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_test_mode_data 0x3b
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_crc_remain_lsb 0x3c
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_crc_remain_msb 0x3d
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_crc_bit_select 0x3e
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_id 0x3f
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* These are pll values that are accessed via TIDAC_pll_pixel_data */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_PIXEL_N 0x80
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_PIXEL_M 0x81
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_PIXEL_P 0x82
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_PIXEL_VALID 0x83
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* These are pll values that are accessed via TIDAC_pll_loop_data */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_LOOP_N 0x90
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_LOOP_M 0x91
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_LOOP_P 0x92
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_LOOP_VALID 0x93
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* Direct mapping addresses */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_INDEX 0xa0
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_PALETTE_DATA 0xa1
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_READ_MASK 0xa2
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_READ_ADDR 0xa3
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_CURS_WRITE_ADDR 0xa4
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_CURS_COLOR 0xa5
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_CURS_READ_ADDR 0xa7
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_CURS_CTL 0xa9
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_INDEXED_DATA 0xaa
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_CURS_RAM_DATA 0xab
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_CURS_XLOW 0xac
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_CURS_XHIGH 0xad
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_CURS_YLOW 0xae
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_CURS_YHIGH 0xaf
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_sw_reset 0xff
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* Constants */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_TVP_3026_ID 0x26
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define TIDAC_TVP_3030_ID 0x30