deb4998ba50060c48cce222fd18a8eed053918d7vboxsync/*
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync * Copyright IBM Corporation 1987,1988,1989
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync *
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync * All Rights Reserved
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync *
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync * Permission to use, copy, modify, and distribute this software and its
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync * documentation for any purpose and without fee is hereby granted,
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync * provided that the above copyright notice appear in all copies and that
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync * both that copyright notice and this permission notice appear in
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync * supporting documentation, and that the name of IBM not be
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync * used in advertising or publicity pertaining to distribution of the
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync * software without specific, written prior permission.
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync *
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync * IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync * IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync * SOFTWARE.
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync *
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync*/
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync/* $XConsortium: vgaReg.h /main/4 1996/02/21 17:59:02 kaleb $ */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define SET_BYTE_REGISTER( ioport, value ) outb( ioport, value )
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define SET_INDEX_REGISTER( ioport, value ) SET_BYTE_REGISTER( ioport, value )
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define SET_DATA_REGISTER( ioport, value ) SET_BYTE_REGISTER( ioport, value )
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync/* GJA -- deleted RTIO and ATRIO case here, so that a PCIO #define became
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync * superfluous.
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define SET_INDEXED_REGISTER(RegGroup, Index, Value) \
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync (SET_BYTE_REGISTER(RegGroup, Index), \
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync SET_BYTE_REGISTER((RegGroup) + 1, Value))
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync/* There is a jumper on the ega to change this to 0x200 instead !! */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#ifdef HAVE_XORG_CONFIG_H
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#include <xorg-config.h>
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#endif
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#if 0 /* This is now a stack variable, as needed */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define REGBASE 0x300
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#endif
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define AttributeIndexRegister REGBASE + 0xC0
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define AttributeDataWriteRegister REGBASE + 0xC0
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define AttributeDataReadRegister REGBASE + 0xC1
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define AttributeRegister AttributeIndexRegister
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define AttributeModeIndex 0x30
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define OverScanColorIndex 0x31
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define ColorPlaneEnableIndex 0x32
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define HorizPelPanIndex 0x33
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define ColorSelectIndex 0x34
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#ifndef PC98_EGC
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define SetVideoAttributeIndex( index ) \
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync SET_INDEX_REGISTER( AttributeIndexRegister, index )
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define SetVideoAttribute( index, value ) \
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync SetVideoAttributeIndex( index ) ; \
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync SET_BYTE_REGISTER( AttributeDataWriteRegister, value )
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#endif
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync /* Graphics Registers 03CE & 03CF */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define GraphicsIndexRegister REGBASE + 0xCE
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define GraphicsDataRegister REGBASE + 0xCF
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define GraphicsRegister GraphicsIndexRegister
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define Set_ResetIndex 0x00
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define Enb_Set_ResetIndex 0x01
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define Color_CompareIndex 0x02
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define Data_RotateIndex 0x03
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define Read_Map_SelectIndex 0x04
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define Graphics_ModeIndex 0x05
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define MiscellaneousIndex 0x06
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define Color_Dont_CareIndex 0x07
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define Bit_MaskIndex 0x08
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#ifndef PC98_EGC
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define SetVideoGraphicsIndex( index ) \
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync SET_INDEX_REGISTER( GraphicsIndexRegister, index )
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define SetVideoGraphicsData( value ) \
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync SET_INDEX_REGISTER( GraphicsDataRegister, value )
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define SetVideoGraphics( index, value ) \
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync SET_INDEXED_REGISTER( GraphicsRegister, index, value )
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#endif
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync/* Sequencer Registers 03C4 & 03C5 */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define SequencerIndexRegister REGBASE + 0xC4
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define SequencerDataRegister REGBASE + 0xC5
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define SequencerRegister SequencerIndexRegister
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define Seq_ResetIndex 00
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define Clock_ModeIndex 01
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define Mask_MapIndex 02
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define Char_Map_SelectIndex 03
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define Memory_ModeIndex 04
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#ifndef PC98_EGC
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define SetVideoSequencerIndex( index ) \
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync SET_INDEX_REGISTER( SequencerIndexRegister, index )
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define SetVideoSequencer( index, value ) \
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync SET_INDEXED_REGISTER( SequencerRegister, index, value )
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#endif
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync/* BIT CONSTANTS FOR THE VGA/EGA HARDWARE */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync/* for the Graphics' Data_Rotate Register */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define VGA_ROTATE_FUNC_SHIFT 3
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define VGA_COPY_MODE ( 0 << VGA_ROTATE_FUNC_SHIFT ) /* 0x00 */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define VGA_AND_MODE ( 1 << VGA_ROTATE_FUNC_SHIFT ) /* 0x08 */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define VGA_OR_MODE ( 2 << VGA_ROTATE_FUNC_SHIFT ) /* 0x10 */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define VGA_XOR_MODE ( 3 << VGA_ROTATE_FUNC_SHIFT ) /* 0x18 */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync/* for the Graphics' Graphics_Mode Register */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define VGA_READ_MODE_SHIFT 3
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define VGA_WRITE_MODE_0 0
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define VGA_WRITE_MODE_1 1
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define VGA_WRITE_MODE_2 2
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define VGA_WRITE_MODE_3 3
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define VGA_READ_MODE_0 ( 0 << VGA_READ_MODE_SHIFT )
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define VGA_READ_MODE_1 ( 1 << VGA_READ_MODE_SHIFT )
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#ifdef PC98_EGC
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync/* I/O port address define for extended EGC */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define EGC_PLANE 0x4a0 /* EGC active plane select */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define EGC_READ 0x4a2 /* EGC FGC,EGC,Read Plane */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define EGC_MODE 0x4a4 /* EGC Mode register & ROP */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define EGC_FGC 0x4a6 /* EGC Forground color */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define EGC_MASK 0x4a8 /* EGC Mask register */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define EGC_BGC 0x4aa /* EGC Background color */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define EGC_ADD 0x4ac /* EGC Dest/Source address */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define EGC_LENGTH 0x4ae /* EGC Bit length */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define PALETTE_ADD 0xa8 /* Palette address */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define PALETTE_GRE 0xaa /* Palette Green */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define PALETTE_RED 0xac /* Palette Red */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define PALETTE_BLU 0xae /* Palette Blue */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define EGC_AND_MODE 0x2c8c /* (S&P&D)|(~S&D) */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define EGC_AND_INV_MODE 0x2c2c /* (S&P&~D)|(~S&D) */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define EGC_OR_MODE 0x2cec /* S&(P|D)|(~S&D) */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define EGC_OR_INV_MODE 0x2cbc /* S&(P|~D)|(~S&D) */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define EGC_XOR_MODE 0x2c6c /* (S&(P&~D|~P&D))|(~S&D) */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define EGC_XOR_INV_MODE 0x2c9c /* (S&(P&D)|(~P&~D))|(~S&D) */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define EGC_COPY_MODE 0x2cac /* (S&P)|(~S&D) */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#endif