deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#include <xf86RamDac.h>
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsyncunsigned long TIramdacCalculateMNPForClock(unsigned long RefClock,
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync unsigned long ReqClock, char IsPixClock, unsigned long MinClock,
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync unsigned long MaxClock, unsigned long *rM, unsigned long *rN,
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync unsigned long *rP);
deb4998ba50060c48cce222fd18a8eed053918d7vboxsyncRamDacHelperRecPtr TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs);
deb4998ba50060c48cce222fd18a8eed053918d7vboxsyncvoid TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec);
deb4998ba50060c48cce222fd18a8eed053918d7vboxsyncvoid TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec);
deb4998ba50060c48cce222fd18a8eed053918d7vboxsyncvoid TIramdac3026SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec);
deb4998ba50060c48cce222fd18a8eed053918d7vboxsyncvoid TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec);
deb4998ba50060c48cce222fd18a8eed053918d7vboxsyncunsigned long TIramdac3030CalculateMNPForClock(unsigned long RefClock,
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync unsigned long ReqClock, char IsPixClock, unsigned long MinClock,
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync unsigned long MaxClock, unsigned long *rM, unsigned long *rN,
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync unsigned long *rP);
deb4998ba50060c48cce222fd18a8eed053918d7vboxsyncvoid TIramdacHWCursorInit(xf86CursorInfoPtr infoPtr);
deb4998ba50060c48cce222fd18a8eed053918d7vboxsyncvoid TIramdacLoadPalette( ScrnInfoPtr pScrn, int numColors, int *indices,
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync LOCO *colors, VisualPtr pVisual);
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsynctypedef void TIramdacLoadPaletteProc(ScrnInfoPtr, int, int *, LOCO *,
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync VisualPtr);
deb4998ba50060c48cce222fd18a8eed053918d7vboxsyncTIramdacLoadPaletteProc *TIramdacLoadPaletteWeak(void);
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TI3030_RAMDAC (VENDOR_TI << 16) | 0x00
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TI3026_RAMDAC (VENDOR_TI << 16) | 0x01
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync/*
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync * TI Ramdac registers
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_rev 0x01
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_ind_curs_ctrl 0x06
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_byte_router_ctrl 0x07
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_latch_ctrl 0x0f
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_true_color_ctrl 0x18
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_multiplex_ctrl 0x19
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_clock_select 0x1a
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_palette_page 0x1c
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_general_ctrl 0x1d
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_misc_ctrl 0x1e
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_pll_addr 0x2c
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_pll_pixel_data 0x2d
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_pll_memory_data 0x2e
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_pll_loop_data 0x2f
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_key_over_low 0x30
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_key_over_high 0x31
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_key_red_low 0x32
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_key_red_high 0x33
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_key_green_low 0x34
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_key_green_high 0x35
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_key_blue_low 0x36
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_key_blue_high 0x37
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_key_ctrl 0x38
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_clock_ctrl 0x39
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_sense_test 0x3a
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_test_mode_data 0x3b
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_crc_remain_lsb 0x3c
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_crc_remain_msb 0x3d
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_crc_bit_select 0x3e
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_id 0x3f
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync/* These are pll values that are accessed via TIDAC_pll_pixel_data */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_PIXEL_N 0x80
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_PIXEL_M 0x81
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_PIXEL_P 0x82
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_PIXEL_VALID 0x83
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync/* These are pll values that are accessed via TIDAC_pll_loop_data */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_LOOP_N 0x90
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_LOOP_M 0x91
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_LOOP_P 0x92
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_LOOP_VALID 0x93
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync/* Direct mapping addresses */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_INDEX 0xa0
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_PALETTE_DATA 0xa1
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_READ_MASK 0xa2
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_READ_ADDR 0xa3
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_CURS_WRITE_ADDR 0xa4
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_CURS_COLOR 0xa5
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_CURS_READ_ADDR 0xa7
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_CURS_CTL 0xa9
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_INDEXED_DATA 0xaa
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_CURS_RAM_DATA 0xab
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_CURS_XLOW 0xac
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_CURS_XHIGH 0xad
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_CURS_YLOW 0xae
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_CURS_YHIGH 0xaf
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_sw_reset 0xff
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync/* Constants */
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_TVP_3026_ID 0x26
deb4998ba50060c48cce222fd18a8eed053918d7vboxsync#define TIDAC_TVP_3030_ID 0x30