a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync/* xf86DDC.h
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync *
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync * This file contains all information to interpret a standard EDIC block
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync * transmitted by a display device via DDC (Display Data Channel). So far
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync * there is no information to deal with optional EDID blocks.
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync * DDC is a Trademark of VESA (Video Electronics Standard Association).
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync *
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync * Copyright 1998 by Egbert Eich <Egbert.Eich@Physik.TU-Darmstadt.DE>
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync */
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync#ifndef XF86_DDC_H
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync#define XF86_DDC_H
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync#include "edid.h"
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync#include "xf86i2c.h"
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync#include "xf86str.h"
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync/* speed up / slow down */
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsynctypedef enum {
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync DDC_SLOW,
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync DDC_FAST
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync} xf86ddcSpeed;
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsynctypedef void (*DDC1SetSpeedProc) (ScrnInfoPtr, xf86ddcSpeed);
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsyncextern _X_EXPORT xf86MonPtr xf86DoEDID_DDC1(ScrnInfoPtr pScrn,
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync DDC1SetSpeedProc DDC1SetSpeed,
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync unsigned
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync int (*DDC1Read) (ScrnInfoPtr)
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync );
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsyncextern _X_EXPORT xf86MonPtr xf86DoEDID_DDC2(ScrnInfoPtr pScrn, I2CBusPtr pBus);
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsyncextern _X_EXPORT xf86MonPtr xf86DoEEDID(ScrnInfoPtr pScrn, I2CBusPtr pBus, Bool);
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsyncextern _X_EXPORT xf86MonPtr xf86PrintEDID(xf86MonPtr monPtr);
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsyncextern _X_EXPORT xf86MonPtr xf86InterpretEDID(int screenIndex, Uchar * block);
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsyncextern _X_EXPORT xf86MonPtr xf86InterpretEEDID(int screenIndex, Uchar * block);
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsyncextern _X_EXPORT void
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync xf86EdidMonitorSet(int scrnIndex, MonPtr Monitor, xf86MonPtr DDC);
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsyncextern _X_EXPORT Bool xf86SetDDCproperties(ScrnInfoPtr pScreen, xf86MonPtr DDC);
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsyncextern _X_EXPORT Bool
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync xf86MonitorIsHDMI(xf86MonPtr mon);
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsyncextern _X_EXPORT DisplayModePtr
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsyncFindDMTMode(int hsize, int vsize, int refresh, Bool rb);
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsyncextern _X_EXPORT const DisplayModeRec DMTModes[];
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync/*
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync * Quirks to work around broken EDID data from various monitors.
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync */
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsynctypedef enum {
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync DDC_QUIRK_NONE = 0,
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync /* First detailed mode is bogus, prefer largest mode at 60hz */
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync DDC_QUIRK_PREFER_LARGE_60 = 1 << 0,
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync /* 135MHz clock is too high, drop a bit */
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync DDC_QUIRK_135_CLOCK_TOO_HIGH = 1 << 1,
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync /* Prefer the largest mode at 75 Hz */
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync DDC_QUIRK_PREFER_LARGE_75 = 1 << 2,
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync /* Convert detailed timing's horizontal from units of cm to mm */
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync DDC_QUIRK_DETAILED_H_IN_CM = 1 << 3,
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync /* Convert detailed timing's vertical from units of cm to mm */
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync DDC_QUIRK_DETAILED_V_IN_CM = 1 << 4,
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync /* Detailed timing descriptors have bogus size values, so just take the
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync * maximum size and use that.
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync */
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync DDC_QUIRK_DETAILED_USE_MAXIMUM_SIZE = 1 << 5,
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync /* Monitor forgot to set the first detailed is preferred bit. */
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync DDC_QUIRK_FIRST_DETAILED_PREFERRED = 1 << 6,
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync /* use +hsync +vsync for detailed mode */
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync DDC_QUIRK_DETAILED_SYNC_PP = 1 << 7,
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync /* Force single-link DVI bandwidth limit */
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync DDC_QUIRK_DVI_SINGLE_LINK = 1 << 8,
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync} ddc_quirk_t;
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsynctypedef void (*handle_detailed_fn) (struct detailed_monitor_section *, void *);
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsyncvoid xf86ForEachDetailedBlock(xf86MonPtr mon, handle_detailed_fn, void *data);
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsyncddc_quirk_t xf86DDCDetectQuirks(int scrnIndex, xf86MonPtr DDC, Bool verbose);
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsyncvoid xf86DetTimingApplyQuirks(struct detailed_monitor_section *det_mon,
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync ddc_quirk_t quirks, int hsize, int vsize);
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsynctypedef void (*handle_video_fn) (struct cea_video_block *, void *);
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsyncvoid xf86ForEachVideoBlock(xf86MonPtr, handle_video_fn, void *);
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsyncstruct cea_data_block *xf86MonitorFindHDMIBlock(xf86MonPtr mon);
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync
a5e7ae69e440f6816420fc99599f044e79e716b6vboxsync#endif