03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync/*
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync * Copyright (c) 1997,1998 The XFree86 Project, Inc.
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync *
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync * Loosely based on code bearing the following copyright:
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync *
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany.
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync *
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync * Author: Dirk Hohndel
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#ifndef _VGAHW_H
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define _VGAHW_H
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#include <X11/X.h>
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#include "misc.h"
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#include "input.h"
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#include "scrnintstr.h"
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#include "colormapst.h"
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#include "xf86str.h"
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#include "xf86Pci.h"
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#include "xf86DDC.h"
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#include "globals.h"
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#include <X11/extensions/dpmsconst.h>
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT int vgaHWGetIndex(void);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync/*
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync * access macro
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGAHWPTR(p) ((vgaHWPtr)((p)->privates[vgaHWGetIndex()].ptr))
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync/* Standard VGA registers */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_ATTR_INDEX 0x3C0
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_ATTR_DATA_W 0x3C0
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_ATTR_DATA_R 0x3C1
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_IN_STAT_0 0x3C2 /* read */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_MISC_OUT_W 0x3C2 /* write */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_ENABLE 0x3C3
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_SEQ_INDEX 0x3C4
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_SEQ_DATA 0x3C5
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_DAC_MASK 0x3C6
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_DAC_READ_ADDR 0x3C7
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_DAC_WRITE_ADDR 0x3C8
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_DAC_DATA 0x3C9
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_FEATURE_R 0x3CA /* read */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_MISC_OUT_R 0x3CC /* read */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_GRAPH_INDEX 0x3CE
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_GRAPH_DATA 0x3CF
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_IOBASE_MONO 0x3B0
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_IOBASE_COLOR 0x3D0
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_CRTC_INDEX_OFFSET 0x04
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_CRTC_DATA_OFFSET 0x05
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_IN_STAT_1_OFFSET 0x0A /* read */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_FEATURE_W_OFFSET 0x0A /* write */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync/* default number of VGA registers stored internally */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_NUM_CRTC 25
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_NUM_SEQ 5
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_NUM_GFX 9
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_NUM_ATTR 21
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync/* Flags for vgaHWSave() and vgaHWRestore() */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_SR_MODE 0x01
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_SR_FONTS 0x02
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_SR_CMAP 0x04
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_SR_ALL (VGA_SR_MODE | VGA_SR_FONTS | VGA_SR_CMAP)
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync/* Defaults for the VGA memory window */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_DEFAULT_PHYS_ADDR 0xA0000
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define VGA_DEFAULT_MEM_SIZE (64 * 1024)
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync/*
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync * vgaRegRec contains settings of standard VGA registers.
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsynctypedef struct {
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync unsigned char MiscOutReg; /* */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync unsigned char *CRTC; /* Crtc Controller */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync unsigned char *Sequencer; /* Video Sequencer */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync unsigned char *Graphics; /* Video Graphics */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync unsigned char *Attribute; /* Video Atribute */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync unsigned char DAC[768]; /* Internal Colorlookuptable */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync unsigned char numCRTC; /* number of CRTC registers, def=VGA_NUM_CRTC */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync unsigned char numSequencer; /* number of seq registers, def=VGA_NUM_SEQ */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync unsigned char numGraphics; /* number of gfx registers, def=VGA_NUM_GFX */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync unsigned char numAttribute; /* number of attr registers, def=VGA_NUM_ATTR */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync} vgaRegRec, *vgaRegPtr;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsynctypedef struct _vgaHWRec *vgaHWPtr;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsynctypedef void (*vgaHWWriteIndexProcPtr) (vgaHWPtr hwp, CARD8 indx, CARD8 value);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsynctypedef CARD8 (*vgaHWReadIndexProcPtr) (vgaHWPtr hwp, CARD8 indx);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsynctypedef void (*vgaHWWriteProcPtr) (vgaHWPtr hwp, CARD8 value);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsynctypedef CARD8 (*vgaHWReadProcPtr) (vgaHWPtr hwp);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsynctypedef void (*vgaHWMiscProcPtr) (vgaHWPtr hwp);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync/*
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync * vgaHWRec contains per-screen information required by the vgahw module.
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync *
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync * Note, the palette referred to by the paletteEnabled, enablePalette and
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync * disablePalette is the 16-entry (+overscan) EGA-compatible palette accessed
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync * via the first 17 attribute registers and not the main 8-bit palette.
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsynctypedef struct _vgaHWRec {
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync pointer Base; /* Address of "VGA" memory */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync int MapSize; /* Size of "VGA" memory */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync unsigned long MapPhys; /* phys location of VGA mem */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync int IOBase; /* I/O Base address */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync CARD8 *MMIOBase; /* Pointer to MMIO start */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync int MMIOOffset; /* base + offset + vgareg
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync = mmioreg */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync pointer FontInfo1; /* save area for fonts in
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync plane 2 */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync pointer FontInfo2; /* save area for fonts in
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync plane 3 */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync pointer TextInfo; /* save area for text */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaRegRec SavedReg; /* saved registers */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaRegRec ModeReg; /* register settings for
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync current mode */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync Bool ShowOverscan;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync Bool paletteEnabled;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync Bool cmapSaved;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync ScrnInfoPtr pScrn;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWWriteIndexProcPtr writeCrtc;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWReadIndexProcPtr readCrtc;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWWriteIndexProcPtr writeGr;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWReadIndexProcPtr readGr;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWReadProcPtr readST00;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWReadProcPtr readST01;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWReadProcPtr readFCR;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWWriteProcPtr writeFCR;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWWriteIndexProcPtr writeAttr;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWReadIndexProcPtr readAttr;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWWriteIndexProcPtr writeSeq;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWReadIndexProcPtr readSeq;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWWriteProcPtr writeMiscOut;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWReadProcPtr readMiscOut;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWMiscProcPtr enablePalette;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWMiscProcPtr disablePalette;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWWriteProcPtr writeDacMask;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWReadProcPtr readDacMask;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWWriteProcPtr writeDacWriteAddr;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWWriteProcPtr writeDacReadAddr;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWWriteProcPtr writeDacData;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWReadProcPtr readDacData;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync pointer ddc;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync struct pci_io_handle *io;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWReadProcPtr readEnable;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaHWWriteProcPtr writeEnable;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync struct pci_device *dev;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync} vgaHWRec;
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync/* Some macros that VGA drivers can use in their ChipProbe() function */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define OVERSCAN 0x11 /* Index of OverScan register */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync/* Flags that define how overscan correction should take place */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define KGA_FIX_OVERSCAN 1 /* overcan correction required */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define KGA_ENABLE_ON_ZERO 2 /* if possible enable display at beginning */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync /* of next scanline/frame */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define KGA_BE_TOT_DEC 4 /* always fix problem by setting blank end */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync /* to total - 1 */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define BIT_PLANE 3 /* Which plane we write to in mono mode */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define BITS_PER_GUN 6
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define COLORMAP_SIZE 256
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#define DACDelay(hw) \
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync do { \
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync (hw)->readST01((hw)); \
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync (hw)->readST01((hw)); \
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync } while (0)
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync/* Function Prototypes */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync/* vgaHW.c */
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsynctypedef void vgaHWProtectProc(ScrnInfoPtr, Bool);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsynctypedef void vgaHWBlankScreenProc(ScrnInfoPtr, Bool);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWSetStdFuncs(vgaHWPtr hwp);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWSetMmioFuncs(vgaHWPtr hwp, CARD8 *base, int offset);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWProtect(ScrnInfoPtr pScrn, Bool on);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT vgaHWProtectProc *vgaHWProtectWeak(void);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT Bool vgaHWSaveScreen(ScreenPtr pScreen, int mode);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWBlankScreen(ScrnInfoPtr pScrn, Bool on);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT vgaHWBlankScreenProc *vgaHWBlankScreenWeak(void);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWSeqReset(vgaHWPtr hwp, Bool start);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWRestoreFonts(ScrnInfoPtr scrninfp,
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaRegPtr restore);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWRestoreMode(ScrnInfoPtr scrninfp, vgaRegPtr restore);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWRestoreColormap(ScrnInfoPtr scrninfp,
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync vgaRegPtr restore);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWRestore(ScrnInfoPtr scrninfp, vgaRegPtr restore,
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync int flags);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWSaveFonts(ScrnInfoPtr scrninfp, vgaRegPtr save);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWSaveMode(ScrnInfoPtr scrninfp, vgaRegPtr save);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWSaveColormap(ScrnInfoPtr scrninfp, vgaRegPtr save);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWSave(ScrnInfoPtr scrninfp, vgaRegPtr save,
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync int flags);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT Bool vgaHWInit(ScrnInfoPtr scrnp, DisplayModePtr mode);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT Bool vgaHWSetRegCounts(ScrnInfoPtr scrp, int numCRTC,
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync int numSequencer, int numGraphics,
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync int numAttribute);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT Bool vgaHWCopyReg(vgaRegPtr dst, vgaRegPtr src);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT Bool vgaHWGetHWRec(ScrnInfoPtr scrp);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWFreeHWRec(ScrnInfoPtr scrp);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT Bool vgaHWMapMem(ScrnInfoPtr scrp);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWUnmapMem(ScrnInfoPtr scrp);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWGetIOBase(vgaHWPtr hwp);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWLock(vgaHWPtr hwp);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWUnlock(vgaHWPtr hwp);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWEnable(vgaHWPtr hwp);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWDisable(vgaHWPtr hwp);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWDPMSSet(ScrnInfoPtr pScrn, int PowerManagementMode,
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync int flags);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT Bool vgaHWHandleColormaps(ScreenPtr pScreen);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void vgaHWddc1SetSpeed(ScrnInfoPtr pScrn, xf86ddcSpeed speed);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT CARD32 vgaHWHBlankKGA(DisplayModePtr mode, vgaRegPtr regp,
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync int nBits, unsigned int Flags);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT CARD32 vgaHWVBlankKGA(DisplayModePtr mode, vgaRegPtr regp,
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync int nBits, unsigned int Flags);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT Bool vgaHWAllocDefaultRegs(vgaRegPtr regp);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT DDC1SetSpeedProc vgaHWddc1SetSpeedWeak(void);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT SaveScreenProcPtr vgaHWSaveScreenWeak(void);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsyncextern _X_EXPORT void xf86GetClocks(ScrnInfoPtr pScrn, int num,
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync Bool (*ClockFunc) (ScrnInfoPtr, int),
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync void (*ProtectRegs) (ScrnInfoPtr, Bool),
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync void (*BlankScreen) (ScrnInfoPtr, Bool),
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync unsigned long vertsyncreg, int maskval,
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync int knownclkindex, int knownclkvalue);
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync
03532efdc331b598d3dedc8cc7477641c3b0dd12vboxsync#endif /* _VGAHW_H */