a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* xf86DDC.h
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * This file contains all information to interpret a standard EDIC block
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * transmitted by a display device via DDC (Display Data Channel). So far
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * there is no information to deal with optional EDID blocks.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * DDC is a Trademark of VESA (Video Electronics Standard Association).
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Copyright 1998 by Egbert Eich <Egbert.Eich@Physik.TU-Darmstadt.DE>
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#ifndef XF86_DDC_H
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define XF86_DDC_H
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#include "edid.h"
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#include "xf86i2c.h"
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#include "xf86str.h"
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* speed up / slow down */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef enum {
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync DDC_SLOW,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync DDC_FAST
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync} xf86ddcSpeed;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef void (*DDC1SetSpeedProc) (ScrnInfoPtr, xf86ddcSpeed);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT xf86MonPtr xf86DoEDID_DDC1(ScrnInfoPtr pScrn,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync DDC1SetSpeedProc DDC1SetSpeed,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync int (*DDC1Read) (ScrnInfoPtr)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync );
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT xf86MonPtr xf86DoEDID_DDC2(ScrnInfoPtr pScrn, I2CBusPtr pBus);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT xf86MonPtr xf86DoEEDID(ScrnInfoPtr pScrn, I2CBusPtr pBus, Bool);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT xf86MonPtr xf86PrintEDID(xf86MonPtr monPtr);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT xf86MonPtr xf86InterpretEDID(int screenIndex, Uchar * block);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT xf86MonPtr xf86InterpretEEDID(int screenIndex, Uchar * block);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync xf86EdidMonitorSet(int scrnIndex, MonPtr Monitor, xf86MonPtr DDC);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT Bool xf86SetDDCproperties(ScrnInfoPtr pScreen, xf86MonPtr DDC);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT DisplayModePtr xf86DDCGetModes(int scrnIndex, xf86MonPtr DDC);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT Bool
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync xf86MonitorIsHDMI(xf86MonPtr mon);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT xf86MonPtr xf86DoDisplayID(ScrnInfoPtr pScrn, I2CBusPtr pBus);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync xf86DisplayIDMonitorSet(int scrnIndex, MonPtr mon, xf86MonPtr DDC);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT DisplayModePtr
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncFindDMTMode(int hsize, int vsize, int refresh, Bool rb);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT const DisplayModeRec DMTModes[];
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/*
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Quirks to work around broken EDID data from various monitors.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef enum {
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync DDC_QUIRK_NONE = 0,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync /* First detailed mode is bogus, prefer largest mode at 60hz */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync DDC_QUIRK_PREFER_LARGE_60 = 1 << 0,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync /* 135MHz clock is too high, drop a bit */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync DDC_QUIRK_135_CLOCK_TOO_HIGH = 1 << 1,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync /* Prefer the largest mode at 75 Hz */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync DDC_QUIRK_PREFER_LARGE_75 = 1 << 2,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync /* Convert detailed timing's horizontal from units of cm to mm */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync DDC_QUIRK_DETAILED_H_IN_CM = 1 << 3,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync /* Convert detailed timing's vertical from units of cm to mm */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync DDC_QUIRK_DETAILED_V_IN_CM = 1 << 4,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync /* Detailed timing descriptors have bogus size values, so just take the
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * maximum size and use that.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync DDC_QUIRK_DETAILED_USE_MAXIMUM_SIZE = 1 << 5,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync /* Monitor forgot to set the first detailed is preferred bit. */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync DDC_QUIRK_FIRST_DETAILED_PREFERRED = 1 << 6,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync /* use +hsync +vsync for detailed mode */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync DDC_QUIRK_DETAILED_SYNC_PP = 1 << 7,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync /* Force single-link DVI bandwidth limit */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync DDC_QUIRK_DVI_SINGLE_LINK = 1 << 8,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync} ddc_quirk_t;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef void (*handle_detailed_fn) (struct detailed_monitor_section *, void *);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncvoid xf86ForEachDetailedBlock(xf86MonPtr mon, handle_detailed_fn, void *data);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncddc_quirk_t xf86DDCDetectQuirks(int scrnIndex, xf86MonPtr DDC, Bool verbose);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncvoid xf86DetTimingApplyQuirks(struct detailed_monitor_section *det_mon,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync ddc_quirk_t quirks, int hsize, int vsize);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef void (*handle_video_fn) (struct cea_video_block *, void *);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncvoid xf86ForEachVideoBlock(xf86MonPtr, handle_video_fn, void *);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif