a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/*
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Copyright (c) 1997,1998 The XFree86 Project, Inc.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Loosely based on code bearing the following copyright:
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Author: Dirk Hohndel
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#ifndef _VGAHW_H
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define _VGAHW_H
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#include <X11/X.h>
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#include "misc.h"
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#include "input.h"
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#include "scrnintstr.h"
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#include "colormapst.h"
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#include "xf86str.h"
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#include "xf86Pci.h"
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#include "xf86DDC.h"
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#include "globals.h"
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#include <X11/extensions/dpmsconst.h>
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT int vgaHWGetIndex(void);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/*
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * access macro
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGAHWPTR(p) ((vgaHWPtr)((p)->privates[vgaHWGetIndex()].ptr))
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Standard VGA registers */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_ATTR_INDEX 0x3C0
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_ATTR_DATA_W 0x3C0
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_ATTR_DATA_R 0x3C1
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_IN_STAT_0 0x3C2 /* read */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_MISC_OUT_W 0x3C2 /* write */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_ENABLE 0x3C3
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_SEQ_INDEX 0x3C4
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_SEQ_DATA 0x3C5
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_DAC_MASK 0x3C6
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_DAC_READ_ADDR 0x3C7
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_DAC_WRITE_ADDR 0x3C8
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_DAC_DATA 0x3C9
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_FEATURE_R 0x3CA /* read */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_MISC_OUT_R 0x3CC /* read */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_GRAPH_INDEX 0x3CE
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_GRAPH_DATA 0x3CF
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_IOBASE_MONO 0x3B0
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_IOBASE_COLOR 0x3D0
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_CRTC_INDEX_OFFSET 0x04
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_CRTC_DATA_OFFSET 0x05
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_IN_STAT_1_OFFSET 0x0A /* read */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_FEATURE_W_OFFSET 0x0A /* write */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* default number of VGA registers stored internally */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_NUM_CRTC 25
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_NUM_SEQ 5
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_NUM_GFX 9
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_NUM_ATTR 21
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Flags for vgaHWSave() and vgaHWRestore() */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_SR_MODE 0x01
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_SR_FONTS 0x02
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_SR_CMAP 0x04
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_SR_ALL (VGA_SR_MODE | VGA_SR_FONTS | VGA_SR_CMAP)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Defaults for the VGA memory window */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_DEFAULT_PHYS_ADDR 0xA0000
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define VGA_DEFAULT_MEM_SIZE (64 * 1024)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/*
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * vgaRegRec contains settings of standard VGA registers.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef struct {
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned char MiscOutReg; /* */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned char *CRTC; /* Crtc Controller */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned char *Sequencer; /* Video Sequencer */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned char *Graphics; /* Video Graphics */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned char *Attribute; /* Video Atribute */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned char DAC[768]; /* Internal Colorlookuptable */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned char numCRTC; /* number of CRTC registers, def=VGA_NUM_CRTC */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned char numSequencer; /* number of seq registers, def=VGA_NUM_SEQ */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned char numGraphics; /* number of gfx registers, def=VGA_NUM_GFX */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned char numAttribute; /* number of attr registers, def=VGA_NUM_ATTR */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync} vgaRegRec, *vgaRegPtr;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef struct _vgaHWRec *vgaHWPtr;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef void (*vgaHWWriteIndexProcPtr) (vgaHWPtr hwp, CARD8 indx, CARD8 value);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef CARD8 (*vgaHWReadIndexProcPtr) (vgaHWPtr hwp, CARD8 indx);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef void (*vgaHWWriteProcPtr) (vgaHWPtr hwp, CARD8 value);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef CARD8 (*vgaHWReadProcPtr) (vgaHWPtr hwp);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef void (*vgaHWMiscProcPtr) (vgaHWPtr hwp);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/*
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * vgaHWRec contains per-screen information required by the vgahw module.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Note, the palette referred to by the paletteEnabled, enablePalette and
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * disablePalette is the 16-entry (+overscan) EGA-compatible palette accessed
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * via the first 17 attribute registers and not the main 8-bit palette.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef struct _vgaHWRec {
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync pointer Base; /* Address of "VGA" memory */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync int MapSize; /* Size of "VGA" memory */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long MapPhys; /* phys location of VGA mem */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync int IOBase; /* I/O Base address */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync CARD8 *MMIOBase; /* Pointer to MMIO start */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync int MMIOOffset; /* base + offset + vgareg
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync = mmioreg */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync pointer FontInfo1; /* save area for fonts in
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync plane 2 */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync pointer FontInfo2; /* save area for fonts in
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync plane 3 */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync pointer TextInfo; /* save area for text */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaRegRec SavedReg; /* saved registers */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaRegRec ModeReg; /* register settings for
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync current mode */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync Bool ShowOverscan;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync Bool paletteEnabled;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync Bool cmapSaved;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync ScrnInfoPtr pScrn;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWWriteIndexProcPtr writeCrtc;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWReadIndexProcPtr readCrtc;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWWriteIndexProcPtr writeGr;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWReadIndexProcPtr readGr;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWReadProcPtr readST00;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWReadProcPtr readST01;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWReadProcPtr readFCR;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWWriteProcPtr writeFCR;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWWriteIndexProcPtr writeAttr;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWReadIndexProcPtr readAttr;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWWriteIndexProcPtr writeSeq;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWReadIndexProcPtr readSeq;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWWriteProcPtr writeMiscOut;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWReadProcPtr readMiscOut;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWMiscProcPtr enablePalette;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWMiscProcPtr disablePalette;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWWriteProcPtr writeDacMask;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWReadProcPtr readDacMask;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWWriteProcPtr writeDacWriteAddr;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWWriteProcPtr writeDacReadAddr;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWWriteProcPtr writeDacData;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWReadProcPtr readDacData;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync pointer ddc;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync struct pci_io_handle *io;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWReadProcPtr readEnable;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaHWWriteProcPtr writeEnable;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync struct pci_device *dev;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync} vgaHWRec;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Some macros that VGA drivers can use in their ChipProbe() function */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define OVERSCAN 0x11 /* Index of OverScan register */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Flags that define how overscan correction should take place */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define KGA_FIX_OVERSCAN 1 /* overcan correction required */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define KGA_ENABLE_ON_ZERO 2 /* if possible enable display at beginning */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync /* of next scanline/frame */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define KGA_BE_TOT_DEC 4 /* always fix problem by setting blank end */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync /* to total - 1 */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define BIT_PLANE 3 /* Which plane we write to in mono mode */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define BITS_PER_GUN 6
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define COLORMAP_SIZE 256
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define DACDelay(hw) \
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync do { \
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync (hw)->readST01((hw)); \
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync (hw)->readST01((hw)); \
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync } while (0)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Function Prototypes */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* vgaHW.c */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef void vgaHWProtectProc(ScrnInfoPtr, Bool);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef void vgaHWBlankScreenProc(ScrnInfoPtr, Bool);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWSetStdFuncs(vgaHWPtr hwp);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWSetMmioFuncs(vgaHWPtr hwp, CARD8 *base, int offset);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWProtect(ScrnInfoPtr pScrn, Bool on);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT vgaHWProtectProc *vgaHWProtectWeak(void);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT Bool vgaHWSaveScreen(ScreenPtr pScreen, int mode);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWBlankScreen(ScrnInfoPtr pScrn, Bool on);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT vgaHWBlankScreenProc *vgaHWBlankScreenWeak(void);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWSeqReset(vgaHWPtr hwp, Bool start);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWRestoreFonts(ScrnInfoPtr scrninfp,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaRegPtr restore);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWRestoreMode(ScrnInfoPtr scrninfp, vgaRegPtr restore);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWRestoreColormap(ScrnInfoPtr scrninfp,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync vgaRegPtr restore);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWRestore(ScrnInfoPtr scrninfp, vgaRegPtr restore,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync int flags);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWSaveFonts(ScrnInfoPtr scrninfp, vgaRegPtr save);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWSaveMode(ScrnInfoPtr scrninfp, vgaRegPtr save);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWSaveColormap(ScrnInfoPtr scrninfp, vgaRegPtr save);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWSave(ScrnInfoPtr scrninfp, vgaRegPtr save,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync int flags);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT Bool vgaHWInit(ScrnInfoPtr scrnp, DisplayModePtr mode);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT Bool vgaHWSetRegCounts(ScrnInfoPtr scrp, int numCRTC,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync int numSequencer, int numGraphics,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync int numAttribute);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT Bool vgaHWCopyReg(vgaRegPtr dst, vgaRegPtr src);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT Bool vgaHWGetHWRec(ScrnInfoPtr scrp);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWFreeHWRec(ScrnInfoPtr scrp);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT Bool vgaHWMapMem(ScrnInfoPtr scrp);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWUnmapMem(ScrnInfoPtr scrp);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWGetIOBase(vgaHWPtr hwp);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWLock(vgaHWPtr hwp);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWUnlock(vgaHWPtr hwp);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWEnable(vgaHWPtr hwp);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWDisable(vgaHWPtr hwp);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWDPMSSet(ScrnInfoPtr pScrn, int PowerManagementMode,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync int flags);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT Bool vgaHWHandleColormaps(ScreenPtr pScreen);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void vgaHWddc1SetSpeed(ScrnInfoPtr pScrn, xf86ddcSpeed speed);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT CARD32 vgaHWHBlankKGA(DisplayModePtr mode, vgaRegPtr regp,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync int nBits, unsigned int Flags);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT CARD32 vgaHWVBlankKGA(DisplayModePtr mode, vgaRegPtr regp,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync int nBits, unsigned int Flags);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT Bool vgaHWAllocDefaultRegs(vgaRegPtr regp);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT DDC1SetSpeedProc vgaHWddc1SetSpeedWeak(void);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT SaveScreenProcPtr vgaHWSaveScreenWeak(void);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void xf86GetClocks(ScrnInfoPtr pScrn, int num,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync Bool (*ClockFunc) (ScrnInfoPtr, int),
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync void (*ProtectRegs) (ScrnInfoPtr, Bool),
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync void (*BlankScreen) (ScrnInfoPtr, Bool),
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long vertsyncreg, int maskval,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync int knownclkindex, int knownclkvalue);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* _VGAHW_H */