a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/****************************************************************************
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* Realmode X86 Emulator Library
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* Copyright (C) 1996-1999 SciTech Software, Inc.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* Copyright (C) David Mosberger-Tang
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* Copyright (C) 1999 Egbert Eich
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* ========================================================================
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* Permission to use, copy, modify, distribute, and sell this software and
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* its documentation for any purpose is hereby granted without fee,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* provided that the above copyright notice appear in all copies and that
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* both that copyright notice and this permission notice appear in
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* supporting documentation, and that the name of the authors not be used
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* in advertising or publicity pertaining to distribution of the software
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* without specific, written prior permission. The authors makes no
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* representations about the suitability of this software for any purpose.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* It is provided "as is" without express or implied warranty.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* PERFORMANCE OF THIS SOFTWARE.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* ========================================================================
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* Language: ANSI C
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* Environment: Any
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* Developer: Kendall Bennett
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync* Description: Header file for x86 register definitions.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync****************************************************************************/
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/*---------------------- Macros and type definitions ----------------------*/
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * General EAX, EBX, ECX, EDX type registers. Note that for
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * portability, and speed, the issue of byte swapping is not addressed
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * in the registers. All registers are stored in the default format
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * available on the host machine. The only critical issue is that the
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * registers should line up EXACTLY in the same manner as they do in
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * the 386. That is:
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * EAX & 0xff === AL
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * EAX & 0xffff == AX
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * etc. The result is that alot of the calculations can then be
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * done using the native instruction set fully.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef struct {
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef struct {
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef struct {
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#else /* !__BIG_ENDIAN__ */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef struct {
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef struct {
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef struct {
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* BIG_ENDIAN */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef union {
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Segment registers here represent the 16 bit quantities
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * CS, DS, ES, SS.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* 8 bit registers */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* 16 bit registers */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* 32 bit extended registers */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* special registers */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* special registers */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* special registers */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* segment registers */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* flag conditions */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* 80286 and above always have bit#1 set */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define F_ALWAYS_ON (0x0002) /* flag bits always on */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Define a mask for only those flag bits we will ever pass back
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * (via PUSHF)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* following bits masked in to a 16bit quantity */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define F_PF_CALC 0x010000 /* PARITY flag has been calced */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define F_SF_CALC 0x040000 /* SIGN flag has been calced */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define F_ALL_CALC 0xff0000 /* All have been calced */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Emulator machine state.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Segment usage control.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef struct {
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * MODE contains information on:
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * REPE prefix 2 bits repe,repne
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * SEGMENT overrides 5 bits normal,DS,SS,CS,ES
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Delayed flag set 3 bits (zero, signed, parity)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * reserved 6 bits
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * interrupt # 8 bits instruction raised interrupt
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * BIOS video segregs 4 bits
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Interrupt Pending 1 bits
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Extern interrupt 1 bits
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Halted 1 bits
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync volatile int intr; /* mask of pending interrupts */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/****************************************************************************
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncStructure maintaining the emulator machine state.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncmem_base - Base real mode memory for the emulator
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncmem_size - Size of the real mode memory block for the emulator
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncprivate - private data pointer
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncx86 - X86 registers
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync****************************************************************************/
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef struct {
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/*----------------------------- Global Variables --------------------------*/
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Global emulator machine state.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * We keep it global to avoid pointer dereferences in the code for speed.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/*-------------------------- Function Prototypes --------------------------*/
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Function to log information at runtime */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync} /* End of "C" linkage for C++ */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* __X86EMU_REGS_H */