a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Permission to use, copy, modify, distribute, and sell this software and its
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * documentation for any purpose is hereby granted without fee, provided that
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * the above copyright notice appear in all copies and that both that
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * copyright notice and this permission notice appear in supporting
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * documentation, and that the name of Thomas Roell not be used in
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * advertising or publicity pertaining to distribution of the software without
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * specific, written prior permission. Thomas Roell makes no representations
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * about the suitability of this software for any purpose. It is provided
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * "as is" without express or implied warranty.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * THOMAS ROELL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * EVENT SHALL THOMAS ROELL BE LIABLE FOR ANY SPECIAL, INDIRECT OR
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * PERFORMANCE OF THIS SOFTWARE.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Copyright (c) 1994-2003 by The XFree86 Project, Inc.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Permission is hereby granted, free of charge, to any person obtaining a
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * copy of this software and associated documentation files (the "Software"),
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * to deal in the Software without restriction, including without limitation
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * the rights to use, copy, modify, merge, publish, distribute, sublicense,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * and/or sell copies of the Software, and to permit persons to whom the
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Software is furnished to do so, subject to the following conditions:
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * The above copyright notice and this permission notice shall be included in
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * all copies or substantial portions of the Software.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * OTHER DEALINGS IN THE SOFTWARE.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Except as contained in this notice, the name of the copyright holder(s)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * and author(s) shall not be used in advertising or otherwise to promote
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * the sale, use or other dealings in this Software without prior written
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * authorization from the copyright holder(s) and author(s).
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Map Sun compiler platform defines to gcc-style used in the code */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Allow drivers to use the GCC-supported __inline__ and/or __inline. */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync /* gcc has __inline__ */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* __inline__ */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync /* gcc has __inline */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* __inline */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Support gcc's __FUNCTION__ for people using other compilers */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#if !defined(__arm__)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#if !defined(__sparc__) && !defined(__sparc) && !defined(__arm32__) && !defined(__nds32__) \
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void outb(unsigned short, unsigned char);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void outw(unsigned short, unsigned short);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void outl(unsigned short, unsigned int);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#else /* __sparc__, __arm32__, __alpha__, __nds32__ */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void outb(unsigned long, unsigned char);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void outw(unsigned long, unsigned short);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void outl(unsigned long, unsigned int);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT unsigned char xf86ReadMmio8 (void *, unsigned long);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT unsigned short xf86ReadMmio16Be (void *, unsigned long);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT unsigned short xf86ReadMmio16Le (void *, unsigned long);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT unsigned int xf86ReadMmio32Be (void *, unsigned long);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT unsigned int xf86ReadMmio32Le (void *, unsigned long);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void xf86WriteMmio8 (void *, unsigned long, unsigned int);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void xf86WriteMmio16Be (void *, unsigned long, unsigned int);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void xf86WriteMmio16Le (void *, unsigned long, unsigned int);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void xf86WriteMmio32Be (void *, unsigned long, unsigned int);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void xf86WriteMmio32Le (void *, unsigned long, unsigned int);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void xf86WriteMmio8NB (void *, unsigned long, unsigned int);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void xf86WriteMmio16BeNB (void *, unsigned long, unsigned int);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void xf86WriteMmio16LeNB (void *, unsigned long, unsigned int);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void xf86WriteMmio32BeNB (void *, unsigned long, unsigned int);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void xf86WriteMmio32LeNB (void *, unsigned long, unsigned int);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* _SUNPRO_C */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* __sparc__, __arm32__, __alpha__, __nds32__ */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* __arm__ */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern unsigned long ldq_u(unsigned long *);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern unsigned long ldl_u(unsigned int *);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern unsigned long ldw_u(unsigned short *);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern void stq_u(unsigned long, unsigned long *);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern void stl_u(unsigned long, unsigned int *);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern void stw_u(unsigned long, unsigned short *);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern void mem_barrier(void);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern void write_mem_barrier(void);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern void stl_brx(unsigned long, volatile unsigned char *, int);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern void stw_brx(unsigned short, volatile unsigned char *, int);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern unsigned long ldl_brx(volatile unsigned char *, int);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern unsigned short ldw_brx(volatile unsigned char *, int);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* __powerpc__ && !__OpenBSD */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* NO_INLINE || DO_PROTOTYPES */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define write_mem_barrier() __asm__ __volatile__ ("sfence" : : : "memory")
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define write_mem_barrier() __asm__ __volatile__ ("lock; addl $0,0(%%esp)" : : : "memory")
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define mem_barrier() __asm__ __volatile__ ("mfence" : : : "memory")
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define mem_barrier() __asm__ __volatile__ ("lock; addl $0,0(%%esp)" : : : "memory")
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define mem_barrier() __asm__ __volatile__ ("mb" : : : "memory")
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define write_mem_barrier() __asm__ __volatile__ ("wmb" : : : "memory")
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define mem_barrier() __asm__ __volatile__ ("mfence" : : : "memory")
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define write_mem_barrier() __asm__ __volatile__ ("sfence" : : : "memory")
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define mem_barrier() __asm__ __volatile__ ("mf" : : : "memory")
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define write_mem_barrier() __asm__ __volatile__ ("mf" : : : "memory")
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync /* Note: sync instruction requires MIPS II instruction set */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync ".set push\n\t" \
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync ".set noreorder\n\t" \
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync ".set mips2\n\t" \
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync "sync\n\t" \
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync ".set pop" \
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync : /* no output */ \
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync : /* no input */ \
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync : "memory")
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* defined(linux) && defined(__powerpc64__) */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#ifndef eieio /* We deal with arch-specific eieio() routines above... */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define eieio() __asm__ __volatile__ ("eieio" ::: "memory")
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* eieio */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define barrier() __asm__ __volatile__ (".word 0x8143e00a" : : : "memory")
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* __GNUC__ */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* NO_INLINE */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Define some packed structures to use with unaligned accesses */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Elemental unaligned loads */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const struct __una_u64 *ptr = (const struct __una_u64 *) p;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const struct __una_u32 *ptr = (const struct __una_u32 *) p;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const struct __una_u16 *ptr = (const struct __una_u16 *) p;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Elemental unaligned stores */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#else /* !__GNUC__ */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* __GNUC__ */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* NO_INLINE */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#if (defined(linux) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)) && (defined(__alpha__))
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* for Linux on Alpha, we use the LIBC _inx/_outx routines */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* note that the appropriate setup via "ioperm" needs to be done */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* *before* any inx/outx is done. */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void _outb(unsigned char val, unsigned long port);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void _outw(unsigned short val, unsigned long port);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void _outl(unsigned int val, unsigned long port);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT unsigned int _inb(unsigned long port);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT unsigned int _inw(unsigned long port);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT unsigned int _inl(unsigned long port);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* linux */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#if (defined(__FreeBSD__) || defined(__OpenBSD__)) \
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* for FreeBSD and OpenBSD on Alpha, we use the libio (resp. libalpha) */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* inx/outx routines */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* note that the appropriate setup via "ioperm" needs to be done */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* *before* any inx/outx is done. */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void outb(unsigned int port, unsigned char val);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void outw(unsigned int port, unsigned short val);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void outl(unsigned int port, unsigned int val);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT unsigned char inb(unsigned int port);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT unsigned short inw(unsigned int port);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT unsigned int inl(unsigned int port);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* (__FreeBSD__ || __OpenBSD__ ) && !DO_PROTOTYPES */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* __NetBSD__ */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#elif (defined(linux) || defined(__FreeBSD__)) && defined(__amd64__)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("outb %0,%1"::"a"(val), "d"(port));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("outw %0,%1"::"a"(val), "d"(port));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("outl %0,%1"::"a"(val), "d"(port));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("inb %1,%0":"=a"(ret):"d"(port));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("inw %1,%0":"=a"(ret):"d"(port));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("inl %1,%0":"=a"(ret):"d"(port));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#elif (defined(linux) || defined(sun) || defined(__OpenBSD__) || defined(__FreeBSD__)) && defined(__sparc__)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("stba %0, [%1] %2": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("stha %0, [%1] %2": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("sta %0, [%1] %2": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned char
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86ReadMmio8(__volatile__ void *base, const unsigned long offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned short
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86ReadMmio16Be(__volatile__ void *base, const unsigned long offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned short
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86ReadMmio16Le(__volatile__ void *base, const unsigned long offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86ReadMmio32Be(__volatile__ void *base, const unsigned long offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86ReadMmio32Le(__volatile__ void *base, const unsigned long offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio8(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("stba %0, [%1] %2": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio16Be(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("sth %0, [%1]": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio16Le(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("stha %0, [%1] %2": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio32Be(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("st %0, [%1]": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio32Le(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("sta %0, [%1] %2": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio8NB(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("stba %0, [%1] %2": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio16BeNB(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("sth %0, [%1]": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio16LeNB(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("stha %0, [%1] %2": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio32BeNB(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("st %0, [%1]": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio32LeNB(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("sta %0, [%1] %2": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#elif defined(__mips__) || (defined(__arm32__) && !defined(__linux__))
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync_X_EXPORT unsigned int IOPortBase; /* Memory mapped I/O port area */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile unsigned char *) (((unsigned PORT_SIZE) (port)) + IOPortBase) =
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile unsigned short *) (((unsigned PORT_SIZE) (port)) + IOPortBase) =
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile unsigned int *) (((unsigned PORT_SIZE) (port)) + IOPortBase) =
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync return *(volatile unsigned char *) (((unsigned PORT_SIZE) (port)) +
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync return *(volatile unsigned short *) (((unsigned PORT_SIZE) (port)) +
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync return *(volatile unsigned int *) (((unsigned PORT_SIZE) (port)) +
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86ReadMmio32Be(__volatile__ void *base, const unsigned long offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio32Be(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("sw %0, 0(%1)": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* !linux */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* __mips__ */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#elif (defined(linux) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__FreeBSD__)) && defined(__powerpc__)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned char
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86ReadMmio8(__volatile__ void *base, const unsigned long offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("lbzx %0,%1,%2\n\t" "eieio":"=r"(val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned short
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86ReadMmio16Be(__volatile__ void *base, const unsigned long offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("lhzx %0,%1,%2\n\t" "eieio":"=r"(val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned short
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86ReadMmio16Le(__volatile__ void *base, const unsigned long offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("lhbrx %0,%1,%2\n\t" "eieio":"=r"(val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86ReadMmio32Be(__volatile__ void *base, const unsigned long offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("lwzx %0,%1,%2\n\t" "eieio":"=r"(val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86ReadMmio32Le(__volatile__ void *base, const unsigned long offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("lwbrx %0,%1,%2\n\t" "eieio":"=r"(val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmioNB8(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned char val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmioNB16Le(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned short val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmioNB16Be(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned short val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmioNB32Le(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmioNB32Be(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio8(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned char val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio16Le(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned short val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio16Be(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned short val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio32Le(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio32Be(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* for Linux on ARM, we use the LIBC inx/outx routines */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* note that the appropriate setup via "ioperm" needs to be done */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* *before* any inx/outx is done. */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Assume all port access are aligned. We need to revise this implementation
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * if there is unaligned port access. For ldq_u, ldl_u, ldw_u, stq_u, stl_u and
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * stw_u, they are assumed unaligned.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned char
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86ReadMmio8(__volatile__ void *base, const unsigned long offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync return *(volatile unsigned char *) ((unsigned char *) base + offset);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio8(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile unsigned char *) ((unsigned char *) base + offset) = val;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio8NB(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile unsigned char *) ((unsigned char *) base + offset) = val;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned short
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86ReadMmio16Swap(__volatile__ void *base, const unsigned long offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("lhi %0, [%1];\n\t" "wsbh %0, %0;\n\t":"=r"(ret)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned short
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86ReadMmio16(__volatile__ void *base, const unsigned long offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync return *(volatile unsigned short *) ((char *) base + offset);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio16Swap(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("wsbh %0, %0;\n\t" "shi %0, [%1];\n\t": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio16(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile unsigned short *) ((unsigned char *) base + offset) = val;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio16SwapNB(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("wsbh %0, %0;\n\t" "shi %0, [%1];\n\t": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio16NB(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile unsigned short *) ((unsigned char *) base + offset) = val;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86ReadMmio32Swap(__volatile__ void *base, const unsigned long offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync "wsbh %0, %0;\n\t" "rotri %0, %0, 16;\n\t":"=r"(ret)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86ReadMmio32(__volatile__ void *base, const unsigned long offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync return *(volatile unsigned int *) ((unsigned char *) base + offset);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio32Swap(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("wsbh %0, %0;\n\t" "rotri %0, %0, 16;\n\t" "swi %0, [%1];\n\t": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio32(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile unsigned int *) ((unsigned char *) base + offset) = val;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio32SwapNB(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long addr = ((unsigned long) base) + offset;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("wsbh %0, %0;\n\t" "rotri %0, %0, 16;\n\t" "swi %0, [%1];\n\t": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncxf86WriteMmio32NB(__volatile__ void *base, const unsigned long offset,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync const unsigned int val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile unsigned int *) ((unsigned char *) base + offset) = val;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned long
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync "wsbh %0, %0;\n\t" "rotri %0, %0, 16;\n\t":"=r"(ret)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned long
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync "wsbh %0, %0;\n\t" "rotri %0, %0, 16;\n\t":"=r"(ret)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("wsbh %0, %0;\n\t" "rotri %0, %0, 16;\n\t" "smw.bi %0, [%1], %0, 0;\n\t": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("wsbh %0, %0;\n\t" "rotri %0, %0, 16;\n\t" "smw.bi %0, [%1], %0, 0;\n\t": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#else /* !NDS32_MMIO_SWAP */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile unsigned char *) (((unsigned PORT_SIZE) (port))) = val;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile unsigned short *) (((unsigned PORT_SIZE) (port))) = val;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile unsigned int *) (((unsigned PORT_SIZE) (port))) = val;
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync return *(volatile unsigned char *) (((unsigned PORT_SIZE) (port)));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync return *(volatile unsigned short *) (((unsigned PORT_SIZE) (port)));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync return *(volatile unsigned int *) (((unsigned PORT_SIZE) (port)));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned long
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("lmw.bi %0, [%1], %0, 0;\n\t":"=r"(ret)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned long
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("lmw.bi %0, [%1], %0, 0;\n\t":"=r"(ret)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("smw.bi %0, [%1], %0, 0;\n\t": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("smw.bi %0, [%1], %0, 0;\n\t": /* No outputs */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* NDS32_MMIO_SWAP */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#if (((X_BYTE_ORDER == X_BIG_ENDIAN) && !defined(NDS32_MMIO_SWAP)) || ((X_BYTE_ORDER != X_BIG_ENDIAN) && defined(NDS32_MMIO_SWAP)))
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync (*((unsigned char *)(p)+1)))
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define stw_u(v,p) (*(unsigned char *)(p)) = ((v) >> 8); \
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync (*((unsigned char *)(p)+1)) = (v)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#else /* ix86 */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#if !defined(FAKEIT) && !defined(__mc68000__) && !defined(__arm__) && !defined(__sh__) && !defined(__hppa__) && !defined(__s390__) && !defined(__m32r__)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * If gcc uses gas rather than the native assembler, the syntax of these
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * inlines has to be different. DHD
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("outb %0,%1"::"a"(val), "d"(port));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("outw %0,%1"::"a"(val), "d"(port));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("outl %0,%1"::"a"(val), "d"(port));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("inb %1,%0":"=a"(ret):"d"(port));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("inw %1,%0":"=a"(ret):"d"(port));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("inl %1,%0":"=a"(ret):"d"(port));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#else /* GCCUSESGAS */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("out%B0 (%1)"::"a"(val), "d"(port));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("out%W0 (%1)"::"a"(val), "d"(port));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("out%L0 (%1)"::"a"(val), "d"(port));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("in%B0 (%1)":"=a"(ret):"d"(port));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("in%W0 (%1)":"=a"(ret):"d"(port));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ __volatile__("in%L0 (%1)":"=a"(ret):"d"(port));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* GCCUSESGAS */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#else /* !defined(FAKEIT) && !defined(__mc68000__) && !defined(__arm__) && !defined(__sh__) && !defined(__hppa__) && !defined(__m32r__) */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncstatic __inline__ unsigned int
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* FAKEIT */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* __SUNPRO_C */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* ix86 */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#else /* !GNUC */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#if !defined(__HIGHC__) && !defined(__SUNPRO_C) || \
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* __GNUC__ */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* NO_INLINE */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* entry points for Mmio memory access routines */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT int (*xf86ReadMmio8) (void *, unsigned long);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT int (*xf86ReadMmio16) (void *, unsigned long);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT int (*xf86ReadMmio32) (void *, unsigned long);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Some DRI 3D drivers need MMIO_IN32. */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync return *(volatile unsigned int *) ((unsigned long) Base + (Offset));
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void (*xf86WriteMmio8) (int, void *, unsigned long);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void (*xf86WriteMmio16) (int, void *, unsigned long);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void (*xf86WriteMmio32) (int, void *, unsigned long);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void (*xf86WriteMmioNB8) (int, void *, unsigned long);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void (*xf86WriteMmioNB16) (int, void *, unsigned long);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void (*xf86WriteMmioNB32) (int, void *, unsigned long);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void xf86SlowBCopyFromBus(unsigned char *, unsigned char *,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void xf86SlowBCopyToBus(unsigned char *, unsigned char *, int);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Some macros to hide the system dependencies for MMIO accesses */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Changed to kill noise generated by gcc's -Wcast-align */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN8(base, offset) (*xf86ReadMmio8)(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN16(base, offset) (*xf86ReadMmio16)(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN32(base, offset) (*xf86ReadMmio32)(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN32(base, offset) xf86ReadMmio32(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile CARD32 *)(void *)(((CARD8*)(base)) + (offset)) = (val); \
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync } while (0)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile CARD32 *)(void *)(((CARD8*)(base)) + (offset)) = (val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * we provide byteswapping and no byteswapping functions here
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * with byteswapping as default,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * drivers that don't need byteswapping should define PPC_MMIO_IS_BE
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN8(base, offset) xf86ReadMmio8(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN16(base, offset) xf86ReadMmio16Be(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN32(base, offset) xf86ReadMmio32Be(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#else /* byteswapping is the default */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN16(base, offset) xf86ReadMmio16Le(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN32(base, offset) xf86ReadMmio32Le(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#elif defined(__sparc__) || defined(sparc) || defined(__sparc)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * Like powerpc, we provide byteswapping and no byteswapping functions
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * here with byteswapping as default, drivers that don't need byteswapping
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * should define SPARC_MMIO_IS_BE (perhaps create a generic macro so that we
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * do not need to use PPC_MMIO_IS_BE and the sparc one in all the same places
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * of drivers?).
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN8(base, offset) xf86ReadMmio8(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN16(base, offset) xf86ReadMmio16Be(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN32(base, offset) xf86ReadMmio32Be(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#else /* byteswapping is the default */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN16(base, offset) xf86ReadMmio16Le(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN32(base, offset) xf86ReadMmio32Le(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * we provide byteswapping and no byteswapping functions here
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * with no byteswapping as default; when endianness of CPU core
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * and I/O devices don't match, byte swapping is necessary
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * drivers that need byteswapping should define NDS32_MMIO_SWAP
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN8(base, offset) xf86ReadMmio8(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN16(base, offset) xf86ReadMmio16Swap(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN32(base, offset) xf86ReadMmio32Swap(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#else /* no byteswapping is the default */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN16(base, offset) xf86ReadMmio16(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_IN32(base, offset) xf86ReadMmio32(base, offset)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync "cctl %0,L1I_VA_INVAL;" "isb;"::"r" (addr):"memory");
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync __asm__ volatile ("isync %0;" "isb;"::"r" (addr):"memory");
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#else /* !__alpha__ && !__powerpc__ && !__sparc__ */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile CARD16 *)(void *)(((CARD8*)(base)) + (offset))
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile CARD32 *)(void *)(((CARD8*)(base)) + (offset))
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile CARD8 *)(((CARD8*)(base)) + (offset)) = (val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile CARD16 *)(void *)(((CARD8*)(base)) + (offset)) = (val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync *(volatile CARD32 *)(void *)(((CARD8*)(base)) + (offset)) = (val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_ONB8(base, offset, val) MMIO_OUT8(base, offset, val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_ONB16(base, offset, val) MMIO_OUT16(base, offset, val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_ONB32(base, offset, val) MMIO_OUT32(base, offset, val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define MMIO_MOVE32(base, offset, val) MMIO_OUT32(base, offset, val)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* __alpha__ */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * With Intel, the version in os-support/misc/SlowBcopy.s is used.
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * This avoids port I/O during the copy (which causes problems with
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * some hardware).
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define slowbcopy_tobus(src,dst,count) xf86SlowBCopyToBus(src,dst,count)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define slowbcopy_frombus(src,dst,count) xf86SlowBCopyFromBus(src,dst,count)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#else /* __alpha__ */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define slowbcopy_tobus(src,dst,count) xf86SlowBcopy(src,dst,count)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define slowbcopy_frombus(src,dst,count) xf86SlowBcopy(src,dst,count)
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* __alpha__ */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#endif /* _COMPILER_H */