a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#include <xf86RamDac.h>
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT unsigned long TIramdacCalculateMNPForClock(unsigned long
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync RefClock,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync ReqClock,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync char IsPixClock,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync MinClock,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync MaxClock,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long *rM,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long *rN,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync unsigned long *rP);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT RamDacHelperRecPtr TIramdacProbe(ScrnInfoPtr pScrn,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync RamDacSupportedInfoRecPtr
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync ramdacs);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync RamDacRegRecPtr RamDacRegRec);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync RamDacRegRecPtr RamDacRegRec);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void TIramdac3026SetBpp(ScrnInfoPtr pScrn,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync RamDacRegRecPtr RamDacRegRec);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void TIramdac3030SetBpp(ScrnInfoPtr pScrn,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync RamDacRegRecPtr RamDacRegRec);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void TIramdacHWCursorInit(xf86CursorInfoPtr infoPtr);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT void TIramdacLoadPalette(ScrnInfoPtr pScrn, int numColors,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync int *indices, LOCO * colors,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync VisualPtr pVisual);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsynctypedef void TIramdacLoadPaletteProc(ScrnInfoPtr, int, int *, LOCO *,
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync VisualPtr);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsyncextern _X_EXPORT TIramdacLoadPaletteProc *TIramdacLoadPaletteWeak(void);
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TI3030_RAMDAC (VENDOR_TI << 16) | 0x00
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TI3026_RAMDAC (VENDOR_TI << 16) | 0x01
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/*
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync * TI Ramdac registers
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_rev 0x01
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_ind_curs_ctrl 0x06
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_byte_router_ctrl 0x07
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_latch_ctrl 0x0f
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_true_color_ctrl 0x18
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_multiplex_ctrl 0x19
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_clock_select 0x1a
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_palette_page 0x1c
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_general_ctrl 0x1d
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_misc_ctrl 0x1e
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_pll_addr 0x2c
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_pll_pixel_data 0x2d
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_pll_memory_data 0x2e
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_pll_loop_data 0x2f
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_key_over_low 0x30
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_key_over_high 0x31
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_key_red_low 0x32
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_key_red_high 0x33
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_key_green_low 0x34
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_key_green_high 0x35
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_key_blue_low 0x36
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_key_blue_high 0x37
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_key_ctrl 0x38
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_clock_ctrl 0x39
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_sense_test 0x3a
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_test_mode_data 0x3b
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_crc_remain_lsb 0x3c
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_crc_remain_msb 0x3d
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_crc_bit_select 0x3e
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_id 0x3f
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* These are pll values that are accessed via TIDAC_pll_pixel_data */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_PIXEL_N 0x80
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_PIXEL_M 0x81
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_PIXEL_P 0x82
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_PIXEL_VALID 0x83
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* These are pll values that are accessed via TIDAC_pll_loop_data */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_LOOP_N 0x90
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_LOOP_M 0x91
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_LOOP_P 0x92
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_LOOP_VALID 0x93
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Direct mapping addresses */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_INDEX 0xa0
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_PALETTE_DATA 0xa1
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_READ_MASK 0xa2
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_READ_ADDR 0xa3
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_CURS_WRITE_ADDR 0xa4
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_CURS_COLOR 0xa5
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_CURS_READ_ADDR 0xa7
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_CURS_CTL 0xa9
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_INDEXED_DATA 0xaa
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_CURS_RAM_DATA 0xab
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_CURS_XLOW 0xac
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_CURS_XHIGH 0xad
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_CURS_YLOW 0xae
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_CURS_YHIGH 0xaf
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_sw_reset 0xff
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync/* Constants */
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_TVP_3026_ID 0x26
a3f3701cea1ba388e7c877955252bb7375eedebdvboxsync#define TIDAC_TVP_3030_ID 0x30