4c221b0da1816acf2ca302b10092df059484468dvboxsync/****************************************************************************
4c221b0da1816acf2ca302b10092df059484468dvboxsync*
4c221b0da1816acf2ca302b10092df059484468dvboxsync* Realmode X86 Emulator Library
4c221b0da1816acf2ca302b10092df059484468dvboxsync*
4c221b0da1816acf2ca302b10092df059484468dvboxsync* Copyright (C) 1996-1999 SciTech Software, Inc.
4c221b0da1816acf2ca302b10092df059484468dvboxsync* Copyright (C) David Mosberger-Tang
4c221b0da1816acf2ca302b10092df059484468dvboxsync* Copyright (C) 1999 Egbert Eich
4c221b0da1816acf2ca302b10092df059484468dvboxsync*
4c221b0da1816acf2ca302b10092df059484468dvboxsync* ========================================================================
4c221b0da1816acf2ca302b10092df059484468dvboxsync*
4c221b0da1816acf2ca302b10092df059484468dvboxsync* Permission to use, copy, modify, distribute, and sell this software and
4c221b0da1816acf2ca302b10092df059484468dvboxsync* its documentation for any purpose is hereby granted without fee,
4c221b0da1816acf2ca302b10092df059484468dvboxsync* provided that the above copyright notice appear in all copies and that
4c221b0da1816acf2ca302b10092df059484468dvboxsync* both that copyright notice and this permission notice appear in
4c221b0da1816acf2ca302b10092df059484468dvboxsync* supporting documentation, and that the name of the authors not be used
4c221b0da1816acf2ca302b10092df059484468dvboxsync* in advertising or publicity pertaining to distribution of the software
4c221b0da1816acf2ca302b10092df059484468dvboxsync* without specific, written prior permission. The authors makes no
4c221b0da1816acf2ca302b10092df059484468dvboxsync* representations about the suitability of this software for any purpose.
4c221b0da1816acf2ca302b10092df059484468dvboxsync* It is provided "as is" without express or implied warranty.
4c221b0da1816acf2ca302b10092df059484468dvboxsync*
4c221b0da1816acf2ca302b10092df059484468dvboxsync* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
4c221b0da1816acf2ca302b10092df059484468dvboxsync* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
4c221b0da1816acf2ca302b10092df059484468dvboxsync* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
4c221b0da1816acf2ca302b10092df059484468dvboxsync* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
4c221b0da1816acf2ca302b10092df059484468dvboxsync* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
4c221b0da1816acf2ca302b10092df059484468dvboxsync* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
4c221b0da1816acf2ca302b10092df059484468dvboxsync* PERFORMANCE OF THIS SOFTWARE.
4c221b0da1816acf2ca302b10092df059484468dvboxsync*
4c221b0da1816acf2ca302b10092df059484468dvboxsync* ========================================================================
4c221b0da1816acf2ca302b10092df059484468dvboxsync*
4c221b0da1816acf2ca302b10092df059484468dvboxsync* Language: ANSI C
4c221b0da1816acf2ca302b10092df059484468dvboxsync* Environment: Any
4c221b0da1816acf2ca302b10092df059484468dvboxsync* Developer: Kendall Bennett
4c221b0da1816acf2ca302b10092df059484468dvboxsync*
4c221b0da1816acf2ca302b10092df059484468dvboxsync* Description: Header file for FPU register definitions.
4c221b0da1816acf2ca302b10092df059484468dvboxsync*
4c221b0da1816acf2ca302b10092df059484468dvboxsync****************************************************************************/
4c221b0da1816acf2ca302b10092df059484468dvboxsync
4c221b0da1816acf2ca302b10092df059484468dvboxsync#ifndef __X86EMU_FPU_REGS_H
4c221b0da1816acf2ca302b10092df059484468dvboxsync#define __X86EMU_FPU_REGS_H
4c221b0da1816acf2ca302b10092df059484468dvboxsync
4c221b0da1816acf2ca302b10092df059484468dvboxsync#ifdef X86_FPU_SUPPORT
4c221b0da1816acf2ca302b10092df059484468dvboxsync
4c221b0da1816acf2ca302b10092df059484468dvboxsync#ifdef PACK
4c221b0da1816acf2ca302b10092df059484468dvboxsync# pragma PACK
4c221b0da1816acf2ca302b10092df059484468dvboxsync#endif
4c221b0da1816acf2ca302b10092df059484468dvboxsync
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* Basic 8087 register can hold any of the following values: */
4c221b0da1816acf2ca302b10092df059484468dvboxsync
4c221b0da1816acf2ca302b10092df059484468dvboxsyncunion x86_fpu_reg_u {
4c221b0da1816acf2ca302b10092df059484468dvboxsync s8 tenbytes[10];
4c221b0da1816acf2ca302b10092df059484468dvboxsync double dval;
4c221b0da1816acf2ca302b10092df059484468dvboxsync float fval;
4c221b0da1816acf2ca302b10092df059484468dvboxsync s16 sval;
4c221b0da1816acf2ca302b10092df059484468dvboxsync s32 lval;
4c221b0da1816acf2ca302b10092df059484468dvboxsync };
4c221b0da1816acf2ca302b10092df059484468dvboxsync
4c221b0da1816acf2ca302b10092df059484468dvboxsyncstruct x86_fpu_reg {
4c221b0da1816acf2ca302b10092df059484468dvboxsync union x86_fpu_reg_u reg;
4c221b0da1816acf2ca302b10092df059484468dvboxsync char tag;
4c221b0da1816acf2ca302b10092df059484468dvboxsync };
4c221b0da1816acf2ca302b10092df059484468dvboxsync
4c221b0da1816acf2ca302b10092df059484468dvboxsync/*
4c221b0da1816acf2ca302b10092df059484468dvboxsync * Since we are not going to worry about the problems of aliasing
4c221b0da1816acf2ca302b10092df059484468dvboxsync * registers, every time a register is modified, its result type is
4c221b0da1816acf2ca302b10092df059484468dvboxsync * set in the tag fields for that register. If some operation
4c221b0da1816acf2ca302b10092df059484468dvboxsync * attempts to access the type in a way inconsistent with its current
4c221b0da1816acf2ca302b10092df059484468dvboxsync * storage format, then we flag the operation. If common, we'll
4c221b0da1816acf2ca302b10092df059484468dvboxsync * attempt the conversion.
4c221b0da1816acf2ca302b10092df059484468dvboxsync */
4c221b0da1816acf2ca302b10092df059484468dvboxsync
4c221b0da1816acf2ca302b10092df059484468dvboxsync#define X86_FPU_VALID 0x80
4c221b0da1816acf2ca302b10092df059484468dvboxsync#define X86_FPU_REGTYP(r) ((r) & 0x7F)
4c221b0da1816acf2ca302b10092df059484468dvboxsync
4c221b0da1816acf2ca302b10092df059484468dvboxsync#define X86_FPU_WORD 0x0
4c221b0da1816acf2ca302b10092df059484468dvboxsync#define X86_FPU_SHORT 0x1
4c221b0da1816acf2ca302b10092df059484468dvboxsync#define X86_FPU_LONG 0x2
4c221b0da1816acf2ca302b10092df059484468dvboxsync#define X86_FPU_FLOAT 0x3
4c221b0da1816acf2ca302b10092df059484468dvboxsync#define X86_FPU_DOUBLE 0x4
4c221b0da1816acf2ca302b10092df059484468dvboxsync#define X86_FPU_LDBL 0x5
4c221b0da1816acf2ca302b10092df059484468dvboxsync#define X86_FPU_BSD 0x6
4c221b0da1816acf2ca302b10092df059484468dvboxsync
4c221b0da1816acf2ca302b10092df059484468dvboxsync#define X86_FPU_STKTOP 0
4c221b0da1816acf2ca302b10092df059484468dvboxsync
4c221b0da1816acf2ca302b10092df059484468dvboxsyncstruct x86_fpu_registers {
4c221b0da1816acf2ca302b10092df059484468dvboxsync struct x86_fpu_reg x86_fpu_stack[8];
4c221b0da1816acf2ca302b10092df059484468dvboxsync int x86_fpu_flags;
4c221b0da1816acf2ca302b10092df059484468dvboxsync int x86_fpu_config; /* rounding modes, etc. */
4c221b0da1816acf2ca302b10092df059484468dvboxsync short x86_fpu_tos, x86_fpu_bos;
4c221b0da1816acf2ca302b10092df059484468dvboxsync };
4c221b0da1816acf2ca302b10092df059484468dvboxsync
4c221b0da1816acf2ca302b10092df059484468dvboxsync#ifdef END_PACK
4c221b0da1816acf2ca302b10092df059484468dvboxsync# pragma END_PACK
4c221b0da1816acf2ca302b10092df059484468dvboxsync#endif
4c221b0da1816acf2ca302b10092df059484468dvboxsync
4c221b0da1816acf2ca302b10092df059484468dvboxsync/*
4c221b0da1816acf2ca302b10092df059484468dvboxsync * There are two versions of the following macro.
4c221b0da1816acf2ca302b10092df059484468dvboxsync *
4c221b0da1816acf2ca302b10092df059484468dvboxsync * One version is for opcode D9, for which there are more than 32
4c221b0da1816acf2ca302b10092df059484468dvboxsync * instructions encoded in the second byte of the opcode.
4c221b0da1816acf2ca302b10092df059484468dvboxsync *
4c221b0da1816acf2ca302b10092df059484468dvboxsync * The other version, deals with all the other 7 i87 opcodes, for
4c221b0da1816acf2ca302b10092df059484468dvboxsync * which there are only 32 strings needed to describe the
4c221b0da1816acf2ca302b10092df059484468dvboxsync * instructions.
4c221b0da1816acf2ca302b10092df059484468dvboxsync */
4c221b0da1816acf2ca302b10092df059484468dvboxsync
4c221b0da1816acf2ca302b10092df059484468dvboxsync#endif /* X86_FPU_SUPPORT */
4c221b0da1816acf2ca302b10092df059484468dvboxsync
4c221b0da1816acf2ca302b10092df059484468dvboxsync#ifdef DEBUG
4c221b0da1816acf2ca302b10092df059484468dvboxsync# define DECODE_PRINTINSTR32(t,mod,rh,rl) \
4c221b0da1816acf2ca302b10092df059484468dvboxsync DECODE_PRINTF(t[(mod<<3)+(rh)]);
4c221b0da1816acf2ca302b10092df059484468dvboxsync# define DECODE_PRINTINSTR256(t,mod,rh,rl) \
4c221b0da1816acf2ca302b10092df059484468dvboxsync DECODE_PRINTF(t[(mod<<6)+(rh<<3)+(rl)]);
4c221b0da1816acf2ca302b10092df059484468dvboxsync#else
4c221b0da1816acf2ca302b10092df059484468dvboxsync# define DECODE_PRINTINSTR32(t,mod,rh,rl)
4c221b0da1816acf2ca302b10092df059484468dvboxsync# define DECODE_PRINTINSTR256(t,mod,rh,rl)
4c221b0da1816acf2ca302b10092df059484468dvboxsync#endif
4c221b0da1816acf2ca302b10092df059484468dvboxsync
4c221b0da1816acf2ca302b10092df059484468dvboxsync#endif /* __X86EMU_FPU_REGS_H */