4c221b0da1816acf2ca302b10092df059484468dvboxsyncextern _X_EXPORT RamDacHelperRecPtr IBMramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs);
4c221b0da1816acf2ca302b10092df059484468dvboxsyncextern _X_EXPORT void IBMramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec);
4c221b0da1816acf2ca302b10092df059484468dvboxsyncextern _X_EXPORT void IBMramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec);
4c221b0da1816acf2ca302b10092df059484468dvboxsyncextern _X_EXPORT void IBMramdac526SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec);
4c221b0da1816acf2ca302b10092df059484468dvboxsyncextern _X_EXPORT void IBMramdac640SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec);
4c221b0da1816acf2ca302b10092df059484468dvboxsyncextern _X_EXPORT unsigned long IBMramdac526CalculateMNPCForClock(unsigned long RefClock,
4c221b0da1816acf2ca302b10092df059484468dvboxsync unsigned long ReqClock, char IsPixClock, unsigned long MinClock,
4c221b0da1816acf2ca302b10092df059484468dvboxsync unsigned long MaxClock, unsigned long *rM, unsigned long *rN,
4c221b0da1816acf2ca302b10092df059484468dvboxsyncextern _X_EXPORT unsigned long IBMramdac640CalculateMNPCForClock(unsigned long RefClock,
4c221b0da1816acf2ca302b10092df059484468dvboxsync unsigned long ReqClock, char IsPixClock, unsigned long MinClock,
4c221b0da1816acf2ca302b10092df059484468dvboxsync unsigned long MaxClock, unsigned long *rM, unsigned long *rN,
4c221b0da1816acf2ca302b10092df059484468dvboxsyncextern _X_EXPORT void IBMramdac526HWCursorInit(xf86CursorInfoPtr infoPtr);
4c221b0da1816acf2ca302b10092df059484468dvboxsyncextern _X_EXPORT void IBMramdac640HWCursorInit(xf86CursorInfoPtr infoPtr);
4c221b0da1816acf2ca302b10092df059484468dvboxsynctypedef void IBMramdac526SetBppProc(ScrnInfoPtr, RamDacRegRecPtr);
4c221b0da1816acf2ca302b10092df059484468dvboxsyncextern _X_EXPORT IBMramdac526SetBppProc *IBMramdac526SetBppWeak(void);
4c221b0da1816acf2ca302b10092df059484468dvboxsync * IBM Ramdac registers
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* #define IBMRGB_f0 0x20 */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* Constants rgb525.h */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_REVISION_LEVEL */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_ID */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_MISC_CTRL_1 */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_MISC_CTRL_2 */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_MISC_CTRL_3 */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_MISC_CLK_CTRL */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_SYNC_CTRL */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_HSYNC_CTRL */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_POWER_MANAGEMENT */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_DAC_OPERATION */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_PALETTE_CTRL */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_PIXEL_FORMAT */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_8BPP_CTRL */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_16BPP_CTRL */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_24BPP_CTRL */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_32BPP_CTRL */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_PLL_CTRL_1 */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_PLL_CTRL_2 */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_PLL_REF_DIV_COUNT */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_F0 - RGB525_F15 */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_PLL_REFCLK values */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_CURSOR_CONTROL */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_REVISION_LEVEL */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* RGB525_ID */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* MISR status */
4c221b0da1816acf2ca302b10092df059484468dvboxsync/* the IBMRGB640 is rather different from the rest of the RAMDACs,
4c221b0da1816acf2ca302b10092df059484468dvboxsync so we define a completely new set of register names for it */