b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* $XFree86: xc/programs/Xserver/hw/xfree86/vgahw/vgaHW.h,v 1.31 2002/04/04 14:05:56 eich Exp $ */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/*
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Copyright (c) 1997,1998 The XFree86 Project, Inc.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Loosely based on code bearing the following copyright:
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Author: Dirk Hohndel
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#ifndef _VGAHW_H
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _VGAHW_H
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#include <X11/X.h>
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#include "misc.h"
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#include "input.h"
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#include "scrnintstr.h"
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#include "colormapst.h"
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#include "xf86str.h"
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#include "xf86Pci.h"
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#include "xf86DDC.h"
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#include "globals.h"
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DPMS_SERVER
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#include <X11/extensions/dpms.h>
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncextern int vgaHWGetIndex(void);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/*
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * access macro
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGAHWPTR(p) ((vgaHWPtr)((p)->privates[vgaHWGetIndex()].ptr))
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* Standard VGA registers */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_ATTR_INDEX 0x3C0
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_ATTR_DATA_W 0x3C0
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_ATTR_DATA_R 0x3C1
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_IN_STAT_0 0x3C2 /* read */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_MISC_OUT_W 0x3C2 /* write */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_ENABLE 0x3C3
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_SEQ_INDEX 0x3C4
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_SEQ_DATA 0x3C5
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_DAC_MASK 0x3C6
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_DAC_READ_ADDR 0x3C7
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_DAC_WRITE_ADDR 0x3C8
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_DAC_DATA 0x3C9
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_FEATURE_R 0x3CA /* read */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_MISC_OUT_R 0x3CC /* read */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_GRAPH_INDEX 0x3CE
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_GRAPH_DATA 0x3CF
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_IOBASE_MONO 0x3B0
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_IOBASE_COLOR 0x3D0
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_CRTC_INDEX_OFFSET 0x04
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_CRTC_DATA_OFFSET 0x05
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_IN_STAT_1_OFFSET 0x0A /* read */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_FEATURE_W_OFFSET 0x0A /* write */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* default number of VGA registers stored internally */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_NUM_CRTC 25
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_NUM_SEQ 5
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_NUM_GFX 9
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_NUM_ATTR 21
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* Flags for vgaHWSave() and vgaHWRestore() */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_SR_MODE 0x01
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_SR_FONTS 0x02
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_SR_CMAP 0x04
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_SR_ALL (VGA_SR_MODE | VGA_SR_FONTS | VGA_SR_CMAP)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* Defaults for the VGA memory window */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_DEFAULT_PHYS_ADDR 0xA0000
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_DEFAULT_MEM_SIZE (64 * 1024)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/*
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * vgaRegRec contains settings of standard VGA registers.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef struct {
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync unsigned char MiscOutReg; /* */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync unsigned char *CRTC; /* Crtc Controller */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync unsigned char *Sequencer; /* Video Sequencer */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync unsigned char *Graphics; /* Video Graphics */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync unsigned char *Attribute; /* Video Atribute */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync unsigned char DAC[768]; /* Internal Colorlookuptable */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync unsigned char numCRTC; /* number of CRTC registers, def=VGA_NUM_CRTC */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync unsigned char numSequencer; /* number of seq registers, def=VGA_NUM_SEQ */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync unsigned char numGraphics; /* number of gfx registers, def=VGA_NUM_GFX */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync unsigned char numAttribute; /* number of attr registers, def=VGA_NUM_ATTR */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync} vgaRegRec, *vgaRegPtr;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef struct _vgaHWRec *vgaHWPtr;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef void (*vgaHWWriteIndexProcPtr)(vgaHWPtr hwp, CARD8 indx, CARD8 value);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef CARD8 (*vgaHWReadIndexProcPtr)(vgaHWPtr hwp, CARD8 indx);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef void (*vgaHWWriteProcPtr)(vgaHWPtr hwp, CARD8 value);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef CARD8 (*vgaHWReadProcPtr)(vgaHWPtr hwp);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef void (*vgaHWMiscProcPtr)(vgaHWPtr hwp);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/*
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * vgaHWRec contains per-screen information required by the vgahw module.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Note, the palette referred to by the paletteEnabled, enablePalette and
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * disablePalette is the 16-entry (+overscan) EGA-compatible palette accessed
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * via the first 17 attribute registers and not the main 8-bit palette.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef struct _vgaHWRec {
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync pointer Base; /* Address of "VGA" memory */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync int MapSize; /* Size of "VGA" memory */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync unsigned long MapPhys; /* phys location of VGA mem */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync int IOBase; /* I/O Base address */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync CARD8 * MMIOBase; /* Pointer to MMIO start */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync int MMIOOffset; /* base + offset + vgareg
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync = mmioreg */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync pointer FontInfo1; /* save area for fonts in
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync plane 2 */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync pointer FontInfo2; /* save area for fonts in
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync plane 3 */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync pointer TextInfo; /* save area for text */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaRegRec SavedReg; /* saved registers */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaRegRec ModeReg; /* register settings for
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync current mode */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync Bool ShowOverscan;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync Bool paletteEnabled;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync Bool cmapSaved;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync ScrnInfoPtr pScrn;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWWriteIndexProcPtr writeCrtc;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWReadIndexProcPtr readCrtc;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWWriteIndexProcPtr writeGr;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWReadIndexProcPtr readGr;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWReadProcPtr readST00;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWReadProcPtr readST01;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWReadProcPtr readFCR;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWWriteProcPtr writeFCR;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWWriteIndexProcPtr writeAttr;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWReadIndexProcPtr readAttr;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWWriteIndexProcPtr writeSeq;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWReadIndexProcPtr readSeq;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWWriteProcPtr writeMiscOut;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWReadProcPtr readMiscOut;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWMiscProcPtr enablePalette;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWMiscProcPtr disablePalette;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWWriteProcPtr writeDacMask;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWReadProcPtr readDacMask;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWWriteProcPtr writeDacWriteAddr;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWWriteProcPtr writeDacReadAddr;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWWriteProcPtr writeDacData;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWReadProcPtr readDacData;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync pointer ddc;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync IOADDRESS PIOOffset; /* offset + vgareg
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync = pioreg */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWReadProcPtr readEnable;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync vgaHWWriteProcPtr writeEnable;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync PCITAG Tag;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync} vgaHWRec;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* Some macros that VGA drivers can use in their ChipProbe() function */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGAHW_GET_IOBASE() ((inb(VGA_MISC_OUT_R) & 0x01) ? \
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync VGA_IOBASE_COLOR : VGA_IOBASE_MONO)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define OVERSCAN 0x11 /* Index of OverScan register */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* Flags that define how overscan correction should take place */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define KGA_FIX_OVERSCAN 1 /* overcan correction required */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define KGA_ENABLE_ON_ZERO 2 /* if possible enable display at beginning */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync /* of next scanline/frame */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define KGA_BE_TOT_DEC 4 /* always fix problem by setting blank end */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync /* to total - 1 */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define BIT_PLANE 3 /* Which plane we write to in mono mode */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define BITS_PER_GUN 6
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define COLORMAP_SIZE 256
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#if defined(__powerpc__)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DACDelay(hw) /* No legacy VGA support */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#else
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DACDelay(hw) \
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync do { \
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync (void)inb((hw)->PIOOffset + (hw)->IOBase + VGA_IN_STAT_1_OFFSET); \
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync (void)inb((hw)->PIOOffset + (hw)->IOBase + VGA_IN_STAT_1_OFFSET); \
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync } while (0)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#endif
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* Function Prototypes */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* vgaHW.c */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef void vgaHWProtectProc(ScrnInfoPtr, Bool);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef void vgaHWBlankScreenProc(ScrnInfoPtr, Bool);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWSetStdFuncs(vgaHWPtr hwp);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWSetMmioFuncs(vgaHWPtr hwp, CARD8 *base, int offset);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWProtect(ScrnInfoPtr pScrn, Bool on);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvgaHWProtectProc *vgaHWProtectWeak(void);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncBool vgaHWSaveScreen(ScreenPtr pScreen, int mode);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWBlankScreen(ScrnInfoPtr pScrn, Bool on);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvgaHWBlankScreenProc *vgaHWBlankScreenWeak(void);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWSeqReset(vgaHWPtr hwp, Bool start);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWRestoreFonts(ScrnInfoPtr scrninfp, vgaRegPtr restore);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWRestoreMode(ScrnInfoPtr scrninfp, vgaRegPtr restore);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWRestoreColormap(ScrnInfoPtr scrninfp, vgaRegPtr restore);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWRestore(ScrnInfoPtr scrninfp, vgaRegPtr restore, int flags);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWSaveFonts(ScrnInfoPtr scrninfp, vgaRegPtr save);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWSaveMode(ScrnInfoPtr scrninfp, vgaRegPtr save);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWSaveColormap(ScrnInfoPtr scrninfp, vgaRegPtr save);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWSave(ScrnInfoPtr scrninfp, vgaRegPtr save, int flags);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncBool vgaHWInit(ScrnInfoPtr scrnp, DisplayModePtr mode);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncBool vgaHWSetRegCounts(ScrnInfoPtr scrp, int numCRTC, int numSequencer,
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync int numGraphics, int numAttribute);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncBool vgaHWCopyReg(vgaRegPtr dst, vgaRegPtr src);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncBool vgaHWGetHWRec(ScrnInfoPtr scrp);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWFreeHWRec(ScrnInfoPtr scrp);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncBool vgaHWMapMem(ScrnInfoPtr scrp);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWUnmapMem(ScrnInfoPtr scrp);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWGetIOBase(vgaHWPtr hwp);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWLock(vgaHWPtr hwp);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWUnlock(vgaHWPtr hwp);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWEnable(vgaHWPtr hwp);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWDisable(vgaHWPtr hwp);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWDPMSSet(ScrnInfoPtr pScrn, int PowerManagementMode, int flags);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncBool vgaHWHandleColormaps(ScreenPtr pScreen);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncvoid vgaHWddc1SetSpeed(ScrnInfoPtr pScrn, xf86ddcSpeed speed);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncCARD32 vgaHWHBlankKGA(DisplayModePtr mode, vgaRegPtr regp, int nBits,
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync unsigned int Flags);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncCARD32 vgaHWVBlankKGA(DisplayModePtr mode, vgaRegPtr regp, int nBits,
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync unsigned int Flags);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncBool vgaHWAllocDefaultRegs(vgaRegPtr regp);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncDDC1SetSpeedProc vgaHWddc1SetSpeedWeak(void);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsyncSaveScreenProcPtr vgaHWSaveScreenWeak(void);
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#endif /* _VGAHW_H */