b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* $XFree86: xc/programs/Xserver/hw/xfree86/xf4bpp/vgaReg.h,v 1.3 1999/06/06 08:49:07 dawes Exp $ */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Copyright IBM Corporation 1987,1988,1989
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * All Rights Reserved
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Permission to use, copy, modify, and distribute this software and its
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * documentation for any purpose and without fee is hereby granted,
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * provided that the above copyright notice appear in all copies and that
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * both that copyright notice and this permission notice appear in
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * supporting documentation, and that the name of IBM not be
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * used in advertising or publicity pertaining to distribution of the
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * software without specific, written prior permission.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * SOFTWARE.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* $XConsortium: vgaReg.h /main/4 1996/02/21 17:59:02 kaleb $ */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define SET_BYTE_REGISTER( ioport, value ) outb( ioport, value )
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define SET_INDEX_REGISTER( ioport, value ) SET_BYTE_REGISTER( ioport, value )
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define SET_DATA_REGISTER( ioport, value ) SET_BYTE_REGISTER( ioport, value )
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* GJA -- deleted RTIO and ATRIO case here, so that a PCIO #define became
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * superfluous.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define SET_INDEXED_REGISTER(RegGroup, Index, Value) \
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* There is a jumper on the ega to change this to 0x200 instead !! */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#if 0 /* This is now a stack variable, as needed */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync SET_INDEX_REGISTER( AttributeIndexRegister, index )
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync SET_BYTE_REGISTER( AttributeDataWriteRegister, value )
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync /* Graphics Registers 03CE & 03CF */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync SET_INDEXED_REGISTER( GraphicsRegister, index, value )
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* Sequencer Registers 03C4 & 03C5 */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync SET_INDEX_REGISTER( SequencerIndexRegister, index )
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync SET_INDEXED_REGISTER( SequencerRegister, index, value )
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* BIT CONSTANTS FOR THE VGA/EGA HARDWARE */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* for the Graphics' Data_Rotate Register */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_COPY_MODE ( 0 << VGA_ROTATE_FUNC_SHIFT ) /* 0x00 */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_AND_MODE ( 1 << VGA_ROTATE_FUNC_SHIFT ) /* 0x08 */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_OR_MODE ( 2 << VGA_ROTATE_FUNC_SHIFT ) /* 0x10 */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_XOR_MODE ( 3 << VGA_ROTATE_FUNC_SHIFT ) /* 0x18 */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* for the Graphics' Graphics_Mode Register */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_READ_MODE_0 ( 0 << VGA_READ_MODE_SHIFT )
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define VGA_READ_MODE_1 ( 1 << VGA_READ_MODE_SHIFT )
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* I/O port address define for extended EGC */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define EGC_PLANE 0x4a0 /* EGC active plane select */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define EGC_MODE 0x4a4 /* EGC Mode register & ROP */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define EGC_AND_INV_MODE 0x2c2c /* (S&P&~D)|(~S&D) */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define EGC_OR_INV_MODE 0x2cbc /* S&(P|~D)|(~S&D) */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define EGC_XOR_MODE 0x2c6c /* (S&(P&~D|~P&D))|(~S&D) */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define EGC_XOR_INV_MODE 0x2c9c /* (S&(P&D)|(~P&~D))|(~S&D) */