7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/**************************************************************************
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsyncCopyright (C) 2004-2005 Nicolai Haehnle et al.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsyncPermission is hereby granted, free of charge, to any person obtaining a
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7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsyncto deal in the Software without restriction, including without limitation
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsyncon the rights to use, copy, modify, merge, publish, distribute, sub
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsynclicense, and/or sell copies of the Software, and to permit persons to whom
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsyncthe Software is furnished to do so, subject to the following conditions:
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsyncThe above copyright notice and this permission notice (including the next
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsyncparagraph) shall be included in all copies or substantial portions of the
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsyncTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsyncIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsyncDAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync**************************************************************************/
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* *INDENT-OFF* */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * This file contains registers and constants for the R300. They have been
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * found mostly by examining command buffers captured using glxtest, as well
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * as by extrapolating some known registers and constants from the R200.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * I am fairly certain that they are correct unless stated otherwise
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * in comments.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Vertex Array Processing (VAP) Control
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Stolen from r200 code from Christoph Brill (It's a guess!)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* This register is written directly and also starts data section
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * in many 3d CP_PACKET3's
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* State based - direct writes to registers trigger vertex
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync generation */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* I don't think I saw these three used.. */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* index size - when not set the indices are assumed to be 16 bit */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* number of vertices */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* BEGIN: Wild guesses */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* each of the following is 3 bits wide, specifies number
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync of components */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* END: Wild guesses */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* BEGIN: Vertex data assembly - lots of uncertainties */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Where do we get our vertex data?
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Vertex data either comes either from immediate mode registers or from
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * vertex arrays.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * There appears to be no mixed mode (though we can force the pitch of
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * vertex arrays to 0, effectively reusing the same element over and over
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Immediate mode is controlled by the INPUT_CNTL registers. I am not sure
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * if these registers influence vertex array processing.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * In both cases, vertex attributes are then passed through INPUT_ROUTE.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * into the vertex processor's input registers.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The first word routes the first input, the second word the second, etc.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The corresponding input is routed into the register with the given index.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The list is ended by a word with INPUT_ROUTE_END set.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Always set COMPONENTS_4 in immediate mode.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - always set up to produce at least two attributes:
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * if vertex program uses only position, fglrx will set normal, too
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * are set to a swizzling bit pattern, other words are 0.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * In immediate mode, the pattern is always set to xyzw. In vertex array
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * mode, the swizzling pattern is e.g. used to set zw components in texture
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * coordinates with only tweo components.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* END: Vertex data assembly */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* BEGIN: Upload vertex program and data */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The programmable vertex shader unit has a memory bank of unknown size
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * that can be written to in 16 byte units by writing the address into
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs).
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Pointers into the memory bank are always in multiples of 16 bytes.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The memory bank is divided into areas with fixed meaning.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Starting at address UPLOAD_PROGRAM: Vertex program instructions.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB),
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * whereas the difference between known addresses suggests size 512.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Starting at address UPLOAD_PARAMETERS: Vertex program parameters.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Native reported limits and the VPI layout suggest size 256, whereas
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * difference between known addresses suggests size 512.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * floating point pointsize. The exact purpose of this state is uncertain,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * as there is also the R300_RE_POINTSIZE register.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Multiple vertex programs and parameter sets can be loaded at once,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * which could explain the size discrepancy.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* END: Upload vertex program and data */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* I do not know the purpose of this register. However, I do know that
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * it is set to 221C_CLEAR for clear operations and to 221C_NORMAL
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * for normal rendering.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * plane is per-pixel and the second plane is per-vertex.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * This was determined by experimentation alone but I believe it is correct.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * rendering commands and overwriting vertex program parameters.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * avoids bugs caused by still running shaders reading bad data from memory.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Absolutely no clue what this register is about. */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Addresses are relative to the vertex program instruction area of the
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * memory bank. PROGRAM_END points to the last instruction of the active
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The meaning of the two UNKNOWN fields is obviously not known. However,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * experiments so far have shown that both *must* point to an instruction
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * inside the vertex program, otherwise the GPU locks up.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * position takes place.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Most likely this is used to ignore rest of the program in cases
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * where group of verts arent visible. For some reason this "section"
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * is sometimes accepted other instruction that have no relationship with
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * position calculations.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Addresses are relative the the vertex program parameters area. */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* The entire range from 0x2300 to 0x2AC inclusive seems to be used for
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * immediate vertices
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* write 0 to indicate end of packet? */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* These are values from r300_reg/r300_reg.h - they are known to be correct
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * and are here so we can use one register file instead of several
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - Vladimir
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* each of the following is 3 bits wide, specifies number
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync of components */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* UNK30 seems to enables point to quad transformation on textures
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * (or something closely related to that).
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * This bit is rather fatal at the time being due to lackings at pixel
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * shader side
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* each of the following is 2 bits wide */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* MSPOS - positions for multisample antialiasing (?) */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* shifts - each of the fields is 4 bits */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* each of the following is 2 bits wide */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* the following use the same constants as above, but meaning is
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync is times 2 (i.e. instead of 32 words it means 64 */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* watermarks, 3 bits wide */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Zero to flush caches. */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* The upper enable bits are guessed, based on fglrx reported limits. */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* The pointsize is given in multiples of 6. The pointsize can be
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * enormous: Clear() renders a single point that fills the entire
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * framebuffer.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* The line width is given in multiples of 6.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * In default mode lines are classified as vertical lines.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * HO: horizontal
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * VE: vertical or horizontal
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * HO & VE: no classification
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Some sort of scale or clamp value for texcoordless textures. */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Something shade related */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Dangerous */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Fog parameters */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Not sure why there are duplicate of factor and constant values.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * My best guess so far is that there are seperate zbiases for test and write.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Ordering might be wrong.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Some of the tests indicate that fgl has a fallback implementation of zbias
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * via pixel shaders.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* This register needs to be set to (1<<1) for RV350 to correctly
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * perform depth test (see --vb-triangles in r300_demo)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Don't know about other chips. - Vladimir
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * This is set to 3 when GL_POLYGON_OFFSET_FILL is on.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * My guess is that there are two bits for each zbias primitive
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * (FILL, LINE, POINT).
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * One to enable depth test and one for depth write.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Yet this doesnt explain why depth writes work ...
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* BEGIN: Rasterization / Interpolators - many guesses */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* 0_UNKNOWN_18 has always been set except for clear operations.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * on the vertex program, *not* the fragment program)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* number of color interpolators used */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync register. */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Only used for texture coordinates.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Use the source field to route texture coordinate input from the
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * vertex program to the desired interpolator. Note that the source
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * field is relative to the outputs the vertex program *actually*
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * writes. If a vertex program only writes texcoord[1], this will
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * be source index 0.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Set INTERP_USED on all interpolators that produce data used by
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * the fragment program. INTERP_USED looks like a swizzling mask,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * but I haven't seen it used that way.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Note: The _UNKNOWN constants are always set in their respective
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * register. I don't know if this is necessary.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* These DWORDs control how vertex data is routed into fragment program
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * registers, after interpolators.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Special handling for color: When the fragment program uses color,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * color register index.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Apperently you may set the R300_RS_ROUTE_0_COLOR bit, but not provide any
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * R300_RS_ROUTE_0_COLOR_DEST value; this setup is used for clearing the state.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * See r300_ioctl.c:r300EmitClearState. I'm not sure if this setup is strictly
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * correct or not. - Oliver.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* As above, but for secondary color */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_RS_ROUTE_1_COLOR1_DEST_MASK (31 << 17)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* END: Rasterization / Interpolators - many guesses */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Hierarchical Z Enable */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* BEGIN: Scissors and cliprects */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* There are four clipping rectangles. Their corner coordinates are inclusive.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * on whether the pixel is inside cliprects 0-3, respectively. For example,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * the number 3 (binary 0011).
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * the pixel is rasterized.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * In addition to this, there is a scissors rectangle. Only pixels inside the
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * scissors rectangle are drawn. (coordinates are inclusive)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * For some reason, the top-left corner of the framebuffer is at (1440, 1440)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * for the purpose of clipping and scissors.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* END: Scissors and cliprects */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* BEGIN: Texture specification */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The texture specification dwords are grouped by meaning and not by texture
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * unit. This means that e.g. the offset for texture image unit N is found in
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * register TX_OFFSET_0 + (4*N)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_TX_MIN_FILTER_NEAREST_MIP_NEAREST (5 << 11)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_TX_MIN_FILTER_NEAREST_MIP_LINEAR (9 << 11)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 11)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* NOTE: NEAREST doesnt seem to exist.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Im not seting MAG_FILTER_MASK and (3 << 11) on for all
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * anisotropy modes because that would void selected mag filter
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (1 << 13)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (2 << 13)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_TX_MIN_FILTER_MASK ( (15 << 11) | (3 << 13) )
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* The interpretation of the format word by Wladimir van der Laan */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* The X, Y, Z and W refer to the layout of the components.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync They are given meanings as R, G, B and Alpha by the swizzle
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync specification */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* 0x16 - some 16 bit green format.. ?? */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* Floating point formats */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* Note - hardware supports both 16 and 32 bit floating point */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* alpha modes, convenience mostly */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* if you have alpha, pick constant appropriate to the
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* Swizzling */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* constants */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* 2.0*Z, everything above 1.0 is set to 0.0 */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* 2.0*W, everything above 1.0 is set to 0.0 */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* Convenience macro to take care of layout and swizzling */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* These can be ORed with result of R300_EASY_TX_FORMAT()
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync We don't really know what they do. Take values from a
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync constant color ? */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define R300_TX_PITCH_0 0x4500 /* obvious missing in gap */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* BEGIN: Guess from R200 */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* END: Guess from R200 */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* 32 bit chroma key */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* ff00ff00 == { 0, 1.0, 0, 1.0 } */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* END: Texture specification */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* BEGIN: Fragment program instruction set */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Fragment programs are written directly into register space.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * There are separate instruction streams for texture instructions and ALU
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * instructions.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * In order to synchronize these streams, the program is divided into up
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * to 4 nodes. Each node begins with a number of TEX operations, followed
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * by a number of ALU operations.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The first node can have zero TEX ops, all subsequent nodes must have at
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * one TEX ops.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * All nodes must have at least one ALU op.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The index of the last node is stored in PFS_CNTL_0: A value of 0 means
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * 1 node, a value of 3 means 4 nodes.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The total amount of instructions is defined in PFS_CNTL_2. The offsets are
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * offsets into the respective instruction streams, while *_END points to the
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * last instruction relative to this offset.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* There is an unshifted value here which has so far always been equal to the
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * index of the highest used temporary register.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Nodes are stored backwards. The last active node is always stored in
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * PFS_NODE_3.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * first node is stored in NODE_2, the second node is stored in NODE_3.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Offsets are relative to the master offset from PFS_CNTL_2.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * As far as I can tell, texture instructions cannot write into output
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * registers directly. A subsequent ALU instruction is always necessary,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * even if it's just MAD o0, r0, 1, 0
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* GUESS based on layout and native limits */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Unsure if these are opcodes, or some kind of bitfield, but this is how
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * they were set when I checked
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The ALU instructions register blocks are enumerated according to the order
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * in which fglrx. I assume there is space for 64 instructions, since
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * each block has space for a maximum of 64 DWORDs, and this matches reported
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * native limits.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The basic functional block seems to be one MAD for each color and alpha,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * and an adder that adds all components after the MUL.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - DP4: Use OUTC_DP4, OUTA_DP4
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - CMPH: If ARG2 > 0.5, return ARG0, else return ARG1
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - CMP: If ARG2 < 0, return ARG1, else return ARG0
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - FLR: use FRC+MAD
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - XPD: use MAD+MAD
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - SGE, SLT: use MAD+CMP
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - RSQ: use ABS modifier for argument
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - Use OUTC_REPL_ALPHA to write results of an alpha-only operation
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * (e.g. RCP) into color register
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - apparently, there's no quick DST operation
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2"
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0"
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1"
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Operand selection
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * First stage selects three sources from the available registers and
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha).
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * fglrx sorts the three source fields: Registers before constants,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * lower indices before higher indices; I do not know whether this is
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * necessary.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * fglrx fills unused sources with "read constant 0"
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * According to specs, you cannot select more than two different constants.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Second stage selects the operands from the sources. This is defined in
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * INSTR0 (color) and INSTR2 (alpha). You can also select the special constants
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * zero and one.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Swizzling and negation happens in this stage, as well.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Important: Color and alpha seem to be mostly separate, i.e. their sources
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * selection appears to be fully independent (the register storage is probably
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * physically split into a color and an alpha section).
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * However (because of the apparent physical split), there is some interaction
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * WRT swizzling. If, for example, you want to load an R component into an
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Alpha operand, this R component is taken from a *color* source, not from
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * an alpha source. The corresponding register doesn't even have to appear in
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * the alpha sources list. (I hope this all makes sense to you)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Destination selection
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The destination register index is in FPI1 (color) and FPI3 (alpha)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * together with enable bits.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * There are separate enable bits for writing into temporary registers
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_*
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * /DSTA_OUTPUT). You can write to both at once, or not write at all (the
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * same index must be used for both).
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Note: There is a special form for LRP
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - Argument order is the same as in ARB_fragment_program.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - Operation is MAD
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* END: Fragment program instruction set */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Fog state and color */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Fragment program parameters in 7.16 floating point */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* GUESS: PARAM_31 is last, based on native limits reported by fglrx */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * the application
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * are set to the same
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * function (both registers are always set up completely in any case)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - Most blend flags are simply copied from R200 and not tested yet
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* the following only appear in CBLEND */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* the following are shared between CBLEND and ABLEND */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Bit 16: Larger tiles
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Bit 17: 4x2 tiles
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Bit 18: Extremely weird tile like, but some pixels duplicated?
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Guess by Vladimir.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Set to 0A before 3D operations, set to 02 afterwards.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/*#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C*/
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* There seems to be no "write only" setting, so use Z-test = ALWAYS
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * for this.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Bit (1<<8) is the "test" bit. so plain write is 6 - vd
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* functions */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* operations */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* front and back refer to operations done for front
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync and back faces, i.e. separate stencil function support */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* reserved up to (15 << 0) */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Z Buffer Address Offset.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Z Buffer Pitch and Endian Control */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Z Buffer Clear Value */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Hierarchical Z Memory Offset */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Hierarchical Z Write Index */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Hierarchical Z Data */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Hierarchical Z Read Index */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Hierarchical Z Pitch */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Z Buffer Z Pass Counter Data */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Z Buffer Z Pass Counter Address */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Depth buffer X and Y coordinate offset */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Sets the fifo sizes */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Stencil Reference Value and Mask for backfacing quads */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* R300_ZB_STENCILREFMASK handles front face */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* BEGIN: Vertex program instruction set */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Every instruction is four dwords long:
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * DWORD 0: output and opcode
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * DWORD 1: first argument
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * DWORD 2: second argument
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * DWORD 3: third argument
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - ABS r, a is implemented as MAX r, a, -a
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - MOV is implemented as ADD to zero
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - XPD is implemented as MUL + MAD
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - FLR is implemented as FRC + ADD
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - apparently, fglrx tries to schedule instructions so that there is at
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * least one instruction between the write to a temporary and the first
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * read from said temporary; however, violations of this scheduling are
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - register indices seem to be unrelated with OpenGL aliasing to
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * conventional state
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - only one attribute and one parameter can be loaded at a time; however,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * the same attribute/parameter can be used for more than one argument
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - the second software argument for POW is the third hardware argument
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * (no idea why)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * There is some magic surrounding LIT:
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The single argument is replicated across all three inputs, but swizzled:
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * First argument: xyzy
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Second argument: xyzx
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Third argument: xyzw
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Whenever the result is used later in the fragment program, fglrx forces
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * x and w to be 1.0 in the input selection; I don't know whether this is
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * strictly necessary
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* Used in fog computations, scalar(scalar) */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* all temps, vector(scalar, vector, vector) */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* GUESS based on fglrx native limits */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* GUESS based on fglrx native limits */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* The R300 can select components from the input register arbitrarily.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Use the following constants, shifted by the component shift you
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * want to select
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* END: Vertex program instruction set */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* BEGIN: Packet 3 commands */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* A primitive emission dword. */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* GUESS (based on r200) */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* GUESS (based on r200) */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Two parameter dwords:
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * 0. The first parameter appears to be always 0
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * 1. The second parameter is a standard primitive emission dword.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Specify the full set of vertex arrays as (address, stride).
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The first parameter is the number of vertex arrays specified.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The rest of the command is a variable length list of blocks, where
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * each block is three dwords long and specifies two arrays.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The first dword of a block is split into two words, the lower significant
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * word refers to the first array, the more significant word to the second
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * array in the block.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The low byte of each word contains the size of an array entry in dwords,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * the high byte contains the stride of the array.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The second dword of a block contains the pointer to the first array,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * the third dword of a block contains the pointer to the second array.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Note that if the total number of arrays is odd, the third dword of
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * the last block is omitted.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* END: Packet 3 commands */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Color formats for 2d packets
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * CP type-3 packets
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#endif /* _R300_REG_H */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* *INDENT-ON* */