7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* mach64_drm.h -- Public header for the mach64 driver -*- linux-c -*-
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Created: Thu Nov 30 20:04:32 2000 by gareth@valinux.com
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/*
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Copyright 2000 Gareth Hughes
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Copyright 2002 Frank C. Earl
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Copyright 2002-2003 Leif Delgass
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * All Rights Reserved.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync *
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Permission is hereby granted, free of charge, to any person obtaining a
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * copy of this software and associated documentation files (the "Software"),
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * to deal in the Software without restriction, including without limitation
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * and/or sell copies of the Software, and to permit persons to whom the
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Software is furnished to do so, subject to the following conditions:
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync *
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The above copyright notice and this permission notice (including the next
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * paragraph) shall be included in all copies or substantial portions of the
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Software.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync *
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync *
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Authors:
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Gareth Hughes <gareth@valinux.com>
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Frank C. Earl <fearl@airmail.net>
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * Leif Delgass <ldelgass@retinalburn.net>
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#ifndef __MACH64_DRM_H__
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define __MACH64_DRM_H__
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* WARNING: If you change any of these defines, make sure to change the
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * defines in the Xserver file (mach64_sarea.h)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#ifndef __MACH64_SAREA_DEFINES__
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define __MACH64_SAREA_DEFINES__
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* What needs to be changed for the current vertex buffer?
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * GH: We're going to be pedantic about this. We want the card to do as
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * little as possible, so let's avoid having it fetch a whole bunch of
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * register values that don't change all that often, if at all.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_UPLOAD_DST_OFF_PITCH 0x0001
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_UPLOAD_Z_OFF_PITCH 0x0002
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_UPLOAD_Z_ALPHA_CNTL 0x0004
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_UPLOAD_SCALE_3D_CNTL 0x0008
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_UPLOAD_DP_FOG_CLR 0x0010
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_UPLOAD_DP_WRITE_MASK 0x0020
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_UPLOAD_DP_PIX_WIDTH 0x0040
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_UPLOAD_SETUP_CNTL 0x0080
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_UPLOAD_MISC 0x0100
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_UPLOAD_TEXTURE 0x0200
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_UPLOAD_TEX0IMAGE 0x0400
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_UPLOAD_TEX1IMAGE 0x0800
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_UPLOAD_CLIPRECTS 0x1000 /* handled client-side */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_UPLOAD_CONTEXT 0x00ff
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_UPLOAD_ALL 0x1fff
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* DMA buffer size
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_BUFFER_SIZE 16384
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Max number of swaps allowed on the ring
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * before the client must wait
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_MAX_QUEUED_FRAMES 3U
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Byte offsets for host blit buffer data
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_HOSTDATA_BLIT_OFFSET 104
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Keep these small for testing.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_NR_SAREA_CLIPRECTS 8
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_CARD_HEAP 0
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_AGP_HEAP 1
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_NR_TEX_HEAPS 2
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_NR_TEX_REGIONS 64
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_LOG_TEX_GRANULARITY 16
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_TEX_MAXLEVELS 1
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_NR_CONTEXT_REGS 15
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_NR_TEXTURE_REGS 4
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#endif /* __MACH64_SAREA_DEFINES__ */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsynctypedef struct {
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int dst_off_pitch;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int z_off_pitch;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int z_cntl;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int alpha_tst_cntl;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int scale_3d_cntl;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int sc_left_right;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int sc_top_bottom;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int dp_fog_clr;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int dp_write_mask;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int dp_pix_width;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int dp_mix;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int dp_src;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int clr_cmp_cntl;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int gui_traj_cntl;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int setup_cntl;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int tex_size_pitch;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int tex_cntl;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int secondary_tex_off;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int tex_offset;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync} drm_mach64_context_regs_t;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsynctypedef struct drm_mach64_sarea {
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* The channel for communication of state information to the kernel
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * on firing a vertex dma buffer.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync drm_mach64_context_regs_t context_state;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int dirty;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int vertsize;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* The current cliprects, or a subset thereof.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync struct drm_clip_rect boxes[MACH64_NR_SAREA_CLIPRECTS];
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int nbox;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* Counters for client-side throttling of rendering clients.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int frames_queued;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync /* Texture memory LRU.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync struct drm_tex_region tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS +
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync 1];
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int tex_age[MACH64_NR_TEX_HEAPS];
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync int ctx_owner;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync} drm_mach64_sarea_t;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* WARNING: If you change any of these defines, make sure to change the
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * defines in the Xserver file (mach64_common.h)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Mach64 specific ioctls
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync * The device specific ioctl range is 0x40 to 0x79.
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define DRM_MACH64_INIT 0x00
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define DRM_MACH64_IDLE 0x01
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define DRM_MACH64_RESET 0x02
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define DRM_MACH64_SWAP 0x03
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define DRM_MACH64_CLEAR 0x04
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define DRM_MACH64_VERTEX 0x05
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define DRM_MACH64_BLIT 0x06
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define DRM_MACH64_FLUSH 0x07
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define DRM_MACH64_GETPARAM 0x08
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define DRM_IOCTL_MACH64_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_INIT, drm_mach64_init_t)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define DRM_IOCTL_MACH64_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_IDLE )
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define DRM_IOCTL_MACH64_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_RESET )
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define DRM_IOCTL_MACH64_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_SWAP )
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define DRM_IOCTL_MACH64_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_CLEAR, drm_mach64_clear_t)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define DRM_IOCTL_MACH64_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_VERTEX, drm_mach64_vertex_t)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define DRM_IOCTL_MACH64_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_BLIT, drm_mach64_blit_t)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define DRM_IOCTL_MACH64_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_FLUSH )
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define DRM_IOCTL_MACH64_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_MACH64_GETPARAM, drm_mach64_getparam_t)
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Buffer flags for clears
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_FRONT 0x1
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_BACK 0x2
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_DEPTH 0x4
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync/* Primitive types for vertex buffers
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_PRIM_POINTS 0x00000000
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_PRIM_LINES 0x00000001
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_PRIM_LINE_LOOP 0x00000002
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_PRIM_LINE_STRIP 0x00000003
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_PRIM_TRIANGLES 0x00000004
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_PRIM_TRIANGLE_STRIP 0x00000005
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_PRIM_TRIANGLE_FAN 0x00000006
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_PRIM_QUADS 0x00000007
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_PRIM_QUAD_STRIP 0x00000008
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#define MACH64_PRIM_POLYGON 0x00000009
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsynctypedef enum _drm_mach64_dma_mode_t {
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync MACH64_MODE_DMA_ASYNC,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync MACH64_MODE_DMA_SYNC,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync MACH64_MODE_MMIO
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync} drm_mach64_dma_mode_t;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsynctypedef struct drm_mach64_init {
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync enum {
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync DRM_MACH64_INIT_DMA = 0x01,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync DRM_MACH64_CLEANUP_DMA = 0x02
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync } func;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned long sarea_priv_offset;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync int is_pci;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync drm_mach64_dma_mode_t dma_mode;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int fb_bpp;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int front_offset, front_pitch;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int back_offset, back_pitch;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int depth_bpp;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int depth_offset, depth_pitch;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned long fb_offset;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned long mmio_offset;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned long ring_offset;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned long buffers_offset;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned long agp_textures_offset;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync} drm_mach64_init_t;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsynctypedef struct drm_mach64_clear {
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int flags;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync int x, y, w, h;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int clear_color;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned int clear_depth;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync} drm_mach64_clear_t;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsynctypedef struct drm_mach64_vertex {
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync int prim;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync void *buf; /* Address of vertex buffer */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned long used; /* Number of bytes in buffer */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync int discard; /* Client finished with buffer? */
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync} drm_mach64_vertex_t;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsynctypedef struct drm_mach64_blit {
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync void *buf;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync int pitch;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync int offset;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync int format;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned short x, y;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync unsigned short width, height;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync} drm_mach64_blit_t;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsynctypedef struct drm_mach64_getparam {
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync enum {
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync MACH64_PARAM_FRAMES_QUEUED = 0x01,
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync MACH64_PARAM_IRQ_NR = 0x02
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync } param;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync void *value;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync} drm_mach64_getparam_t;
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync
7a0d67332f33bc21290d63bc7c8150b0cf0a4b21vboxsync#endif