DRM/include/drm.h

b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* BEGIN CSTYLED */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/**
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * \file drm.h
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Header for the Direct Rendering Manager
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * \author Rickard E. (Rik) Faith <faith@valinux.com>
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * \par Acknowledgments:
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/*
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * All rights reserved.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Permission is hereby granted, free of charge, to any person obtaining a
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * copy of this software and associated documentation files (the "Software"),
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * to deal in the Software without restriction, including without limitation
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * the rights to use, copy, modify, merge, publish, distribute, sublicense,
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * and/or sell copies of the Software, and to permit persons to whom the
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Software is furnished to do so, subject to the following conditions:
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * The above copyright notice and this permission notice (including the next
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * paragraph) shall be included in all copies or substantial portions of the
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Software.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * OTHER DEALINGS IN THE SOFTWARE.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/**
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * \mainpage
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * The Direct Rendering Manager (DRM) is a device-independent kernel-level
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * device driver that provides support for the XFree86 Direct Rendering
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Infrastructure (DRI).
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * The DRM supports the Direct Rendering Infrastructure (DRI) in four major
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * ways:
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *     -# The DRM provides synchronized access to the graphics hardware via
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *        the use of an optimized two-tiered lock.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *     -# The DRM enforces the DRI security policy for access to the graphics
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *        hardware by only allowing authenticated X11 clients access to
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *        restricted regions of memory.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *     -# The DRM provides a generic DMA engine, complete with multiple
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *        queues and the ability to detect the need for an OpenGL context
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *        switch.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *     -# The DRM is extensible via the use of small device-specific modules
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *        that rely extensively on the API exported by the DRM module.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/*
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Copyright 2009-2010 Oracle Corporation
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * All rights reserved.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Use is subject to license terms.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#ifndef _DRM_H_
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _DRM_H_
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#include <sys/types32.h>
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#ifndef __user
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define __user
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#endif
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#ifdef __GNUC__
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync# define DEPRECATED  __attribute__ ((deprecated))
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#else
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync# define DEPRECATED
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync# define __volatile__ volatile
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#endif
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#if defined(__linux__)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#include <asm/ioctl.h>      /* For _IO* macros */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_IOCTL_NR(n)     _IOC_NR(n)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_IOC_VOID        _IOC_NONE
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_IOC_READ        _IOC_READ
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_IOC_WRITE       _IOC_WRITE
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_IOC_READWRITE   _IOC_READ|_IOC_WRITE
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#if (defined(__FreeBSD__) || defined(__FreeBSD_kernel__)) && defined(IN_MODULE)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* Prevent name collision when including sys/ioccom.h */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#undef ioctl
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#include <sys/ioccom.h>
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define ioctl(a,b,c)        xf86ioctl(a,b,c)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#else
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#include <sys/ioccom.h>
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#endif              /* __FreeBSD__ && xf86ioctl */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_IOCTL_NR(n)     ((n) & 0xff)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_IOC_VOID        IOC_VOID
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_IOC_READ        IOC_OUT
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_IOC_WRITE       IOC_IN
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_IOC_READWRITE   IOC_INOUT
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#endif
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* Solaris-specific. */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#if defined(__SOLARIS__) || defined(sun)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_NRBITS 8
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_TYPEBITS   8
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_SIZEBITS   14
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_DIRBITS    2
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_TYPEMASK   ((1 << _IOC_TYPEBITS)-1)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_SIZEMASK   ((1 << _IOC_SIZEBITS)-1)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_DIRMASK    ((1 << _IOC_DIRBITS)-1)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_NRSHIFT    0
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_TYPESHIFT  (_IOC_NRSHIFT+_IOC_NRBITS)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_SIZESHIFT  (_IOC_TYPESHIFT+_IOC_TYPEBITS)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_DIRSHIFT   (_IOC_SIZESHIFT+_IOC_SIZEBITS)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_NONE   0U
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_WRITE  1U
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_READ   2U
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC(dir, type, nr, size) \
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    (((dir)  << _IOC_DIRSHIFT) | \
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    ((type) << _IOC_TYPESHIFT) | \
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    ((nr)   << _IOC_NRSHIFT) | \
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    ((size) << _IOC_SIZESHIFT))
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* used for X server compile */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#if !defined(_KERNEL)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IO(type, nr)       _IOC(_IOC_NONE, (type), (nr), 0)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOR(type, nr, size)    _IOC(_IOC_READ, (type), (nr), sizeof (size))
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOW(type, nr, size)    _IOC(_IOC_WRITE, (type), (nr), sizeof (size))
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOWR(type, nr, size)   _IOC(_IOC_READ|_IOC_WRITE, \
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync                (type), (nr), sizeof (size))
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_DIR(nr)        (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_TYPE(nr)       (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_NR(nr)     (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _IOC_SIZE(nr)       (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define IOC_IN          (_IOC_WRITE << _IOC_DIRSHIFT)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define IOC_OUT         (_IOC_READ << _IOC_DIRSHIFT)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define IOC_INOUT       ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define IOCSIZE_MASK        (_IOC_SIZEMASK << _IOC_SIZESHIFT)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define IOCSIZE_SHIFT       (_IOC_SIZESHIFT)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#endif /* _KERNEL */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_IOCTL_NR(n)     _IOC_NR(n)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_IOC_VOID        IOC_VOID
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_IOC_READ        IOC_OUT
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_IOC_WRITE       IOC_IN
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_IOC_READWRITE   IOC_INOUT
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#endif /* __Solaris__ or sun */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define XFREE86_VERSION(major,minor,patch,snap) \
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync        ((major << 16) | (minor << 8) | patch)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#ifndef CONFIG_XFREE86_VERSION
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#endif
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_PROC_DEVICES "/proc/devices"
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_PROC_MISC    "/proc/misc"
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_PROC_DRM     "/proc/drm"
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_DEV_DRM  "/dev/drm"
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_DEV_MODE     (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_DEV_UID  0
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_DEV_GID  0
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#endif
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#ifdef __OpenBSD__
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_MAJOR       81
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#endif
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#if defined(__linux__) || defined(__NetBSD__)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_MAJOR       226
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#endif
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_MAX_MINOR   15
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#endif
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_NAME    "drm"     /**< Name in kernel, /dev, and /proc */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_MIN_ORDER   5     /**< At least 2^5 bytes = 32 bytes */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_MAX_ORDER   22    /**< Up to 2^22 bytes = 4MB */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define DRM_RAM_PERCENT 10    /**< How much system ram can we lock? */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _DRM_LOCK_HELD  0x80000000U /**< Hardware lock is held */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _DRM_LOCK_CONT  0x40000000U /**< Hardware lock is contended */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _DRM_LOCK_IS_HELD(lock)    ((lock) & _DRM_LOCK_HELD)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _DRM_LOCK_IS_CONT(lock)    ((lock) & _DRM_LOCK_CONT)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#if defined(__linux__)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#if defined(__KERNEL__)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef __u64 drm_u64_t;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#else
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef unsigned long long drm_u64_t;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#endif
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef unsigned int drm_handle_t;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#else
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#include <sys/types.h>
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef uint64_t drm_u64_t;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef unsigned long long drm_handle_t;    /**< To mapped regions */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#endif
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef unsigned int drm_context_t; /**< GLXContext handle */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef unsigned int drm_drawable_t;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef unsigned int drm_magic_t;   /**< Magic for authentication */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/**
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Cliprect.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * \warning If you change this structure, make sure you change
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * XF86DRIClipRectRec in the server as well
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * \note KW: Actually it's illegal to change either for
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * backwards-compatibility reasons.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef struct drm_clip_rect {
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    unsigned short x1;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    unsigned short y1;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    unsigned short x2;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    unsigned short y2;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync} drm_clip_rect_t;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/**
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Drawable information.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef struct drm_drawable_info {
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    unsigned int num_rects;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    drm_clip_rect_t *rects;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync} drm_drawable_info_t;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/**
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Texture region,
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef struct drm_tex_region {
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    unsigned char next;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    unsigned char prev;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    unsigned char in_use;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    unsigned char padding;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    unsigned int age;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync} drm_tex_region_t;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/**
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Hardware lock.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * The lock structure is a simple cache-line aligned integer.  To avoid
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * processor bus contention on a multiprocessor system, there should not be any
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * other data stored in the same cache line.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef struct drm_hw_lock {
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    __volatile__ unsigned int lock;     /**< lock variable */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    char padding[60];           /**< Pad to cache line */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync} drm_hw_lock_t;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/* This is beyond ugly, and only works on GCC.  However, it allows me to use
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * drm.h in places (i.e., in the X-server) where I can't use size_t.  The real
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * fix is to use uint32_t instead of size_t, but that fix will break existing
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems.  That *will*
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * eventually happen, though.  I chose 'unsigned long' to be the fallback type
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * because that works on all the platforms I know about.  Hopefully, the
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * real fix will happen before that bites us.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#ifdef __SIZE_TYPE__
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync# define DRM_SIZE_T __SIZE_TYPE__
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#else
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#if !defined(__SOLARIS__) && !defined(sun)
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync# warning "__SIZE_TYPE__ not defined.  Assuming sizeof(size_t) == sizeof(unsigned long)!"
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#endif
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync# define DRM_SIZE_T unsigned long
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#endif
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/**
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * DRM_IOCTL_VERSION ioctl argument type.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * \sa drmGetVersion().
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef struct drm_version {
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    int version_major;    /**< Major version */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    int version_minor;    /**< Minor version */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    int version_patchlevel;   /**< Patch level */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    DRM_SIZE_T name_len;      /**< Length of name buffer */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    char __user *name;        /**< Name of driver */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    DRM_SIZE_T date_len;      /**< Length of date buffer */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    char __user *date;        /**< User-space buffer to hold date */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    DRM_SIZE_T desc_len;      /**< Length of desc buffer */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    char __user *desc;        /**< User-space buffer to hold desc */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync} drm_version_t;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/**
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * DRM_IOCTL_GET_UNIQUE ioctl argument type.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * \sa drmGetBusid() and drmSetBusId().
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef struct drm_unique {
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    DRM_SIZE_T unique_len;    /**< Length of unique */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    char __user *unique;      /**< Unique name for driver instantiation */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync} drm_unique_t;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync#undef DRM_SIZE_T
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef struct drm_list {
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    int count;        /**< Length of user-space structures */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    drm_version_t __user *version;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync} drm_list_t;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef struct drm_block {
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    int unused;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync} drm_block_t;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/**
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * DRM_IOCTL_CONTROL ioctl argument type.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync *
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * \sa drmCtlInstHandler() and drmCtlUninstHandler().
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef struct drm_control {
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    enum {
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync        DRM_ADD_COMMAND,
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync        DRM_RM_COMMAND,
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync        DRM_INST_HANDLER,
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync        DRM_UNINST_HANDLER
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    } func;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    int irq;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync} drm_control_t;
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync/**
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync * Type of memory to map.
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsynctypedef enum drm_map_type {
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    _DRM_FRAME_BUFFER = 0,    /**< WC (no caching), no core dump */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    _DRM_REGISTERS = 1,   /**< no caching, no core dump */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    _DRM_SHM = 2,         /**< shared, cached */
b8e299dddd091ae24e0c08c45d91b8f937bd14d2vboxsync    _DRM_AGP = 3,         /**< AGP/GART */
    _DRM_SCATTER_GATHER = 4,  /**< Scatter/gather memory for PCI DMA */
    _DRM_CONSISTENT = 5,      /**< Consistent memory for PCI DMA */
    _DRM_TTM    = 6
} drm_map_type_t;

/**
 * Memory mapping flags.
 */
typedef enum drm_map_flags {
    _DRM_RESTRICTED = 0x01,      /**< Cannot be mapped to user-virtual */
    _DRM_READ_ONLY = 0x02,
    _DRM_LOCKED = 0x04,      /**< shared, cached, locked */
    _DRM_KERNEL = 0x08,      /**< kernel requires access */
    _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
    _DRM_CONTAINS_LOCK = 0x20,   /**< SHM page that contains lock */
    _DRM_REMOVABLE = 0x40,       /**< Removable mapping */
    _DRM_DRIVER = 0x80       /**< Managed by driver */
} drm_map_flags_t;

typedef struct drm_ctx_priv_map {
    unsigned int ctx_id;     /**< Context requesting private mapping */
    void *handle;        /**< Handle of map */
} drm_ctx_priv_map_t;

/**
 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
 * argument type.
 *
 * \sa drmAddMap().
 */
typedef struct drm_map {
    unsigned long long offset;   /**< Requested physical address (0 for SAREA)*/
    unsigned long long handle;
                /**< User-space: "Handle" to pass to mmap() */
                /**< Kernel-space: kernel-virtual address */
    unsigned long size;  /**< Requested physical size (bytes) */
    drm_map_type_t type;     /**< Type of memory to map */
    drm_map_flags_t flags;   /**< Flags */
    int mtrr;        /**< MTRR slot used */
    /*   Private data */
} drm_map_t;

/**
 * DRM_IOCTL_GET_CLIENT ioctl argument type.
 */
typedef struct drm_client {
    int idx;        /**< Which client desired? */
    int auth;       /**< Is client authenticated? */
    unsigned long pid;  /**< Process ID */
    unsigned long uid;  /**< User ID */
    unsigned long magic;    /**< Magic */
    unsigned long iocs; /**< Ioctl count */
} drm_client_t;

typedef enum {
    _DRM_STAT_LOCK,
    _DRM_STAT_OPENS,
    _DRM_STAT_CLOSES,
    _DRM_STAT_IOCTLS,
    _DRM_STAT_LOCKS,
    _DRM_STAT_UNLOCKS,
    _DRM_STAT_VALUE,    /**< Generic value */
    _DRM_STAT_BYTE,     /**< Generic byte counter (1024bytes/K) */
    _DRM_STAT_COUNT,    /**< Generic non-byte counter (1000/k) */

    _DRM_STAT_IRQ,      /**< IRQ */
    _DRM_STAT_PRIMARY,  /**< Primary DMA bytes */
    _DRM_STAT_SECONDARY,    /**< Secondary DMA bytes */
    _DRM_STAT_DMA,      /**< DMA */
    _DRM_STAT_SPECIAL,  /**< Special DMA (e.g., priority or polled) */
    _DRM_STAT_MISSED    /**< Missed DMA opportunity */
        /* Add to the *END* of the list */
} drm_stat_type_t;

/**
 * DRM_IOCTL_GET_STATS ioctl argument type.
 */
typedef struct drm_stats {
    unsigned long count;
    struct {
        unsigned long value;
        drm_stat_type_t type;
    } data[15];
} drm_stats_t;

/**
 * Hardware locking flags.
 */
typedef enum drm_lock_flags {
    _DRM_LOCK_READY = 0x01,      /**< Wait until hardware is ready for DMA */
    _DRM_LOCK_QUIESCENT = 0x02,  /**< Wait until hardware quiescent */
    _DRM_LOCK_FLUSH = 0x04,      /**< Flush this context's DMA queue first */
    _DRM_LOCK_FLUSH_ALL = 0x08,  /**< Flush all DMA queues first */
    /* These *HALT* flags aren't supported yet
       -- they will be used to support the
       full-screen DGA-like mode. */
    _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
    _DRM_HALT_CUR_QUEUES = 0x20  /**< Halt all current queues */
} drm_lock_flags_t;

/**
 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
 *
 * \sa drmGetLock() and drmUnlock().
 */
typedef struct drm_lock {
    int context;
    drm_lock_flags_t flags;
} drm_lock_t;

/**
 * DMA flags
 *
 * \warning
 * These values \e must match xf86drm.h.
 *
 * \sa drm_dma.
 */
typedef enum drm_dma_flags {
    /* Flags for DMA buffer dispatch */
    _DRM_DMA_BLOCK = 0x01,        /**<
                       * Block until buffer dispatched.
                       *
                       * \note The buffer may not yet have
                       * been processed by the hardware --
                       * getting a hardware lock with the
                       * hardware quiescent will ensure
                       * that the buffer has been
                       * processed.
                       */
    _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
    _DRM_DMA_PRIORITY = 0x04,     /**< High priority dispatch */

    /* Flags for DMA buffer request */
    _DRM_DMA_WAIT = 0x10,         /**< Wait for free buffers */
    _DRM_DMA_SMALLER_OK = 0x20,   /**< Smaller-than-requested buffers OK */
    _DRM_DMA_LARGER_OK = 0x40     /**< Larger-than-requested buffers OK */
} drm_dma_flags_t;

/**
 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
 *
 * \sa drmAddBufs().
 */
typedef enum {
    _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
    _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
    _DRM_SG_BUFFER  = 0x04, /**< Scatter/gather memory buffer */
    _DRM_FB_BUFFER  = 0x08,  /**< Buffer is in frame buffer */
    _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
} drm_buf_flag;
typedef struct drm_buf_desc {
    int count;       /**< Number of buffers of this size */
    int size;        /**< Size in bytes */
    int low_mark;        /**< Low water mark */
    int high_mark;       /**< High water mark */
    drm_buf_flag flags;
    unsigned long agp_start; /**<
                  * Start address of where the AGP buffers are
                  * in the AGP aperture
                  */
} drm_buf_desc_t;

/**
 * DRM_IOCTL_INFO_BUFS ioctl argument type.
 */
typedef struct drm_buf_info {
    int count;        /**< Number of buffers described in list */
    drm_buf_desc_t __user *list;      /**< List of buffer descriptions */
} drm_buf_info_t;

/**
 * DRM_IOCTL_FREE_BUFS ioctl argument type.
 */
typedef struct drm_buf_free {
    int count;
    int __user *list;
} drm_buf_free_t;

/**
 * Buffer information
 *
 * \sa drm_buf_map.
 */
typedef struct drm_buf_pub {
    int idx;               /**< Index into the master buffer list */
    int total;             /**< Buffer size */
    int used;              /**< Amount of buffer in use (for DMA) */
    void __user *address;          /**< Address of buffer */
} drm_buf_pub_t;

/**
 * DRM_IOCTL_MAP_BUFS ioctl argument type.
 */
typedef struct drm_buf_map {
    int count;      /**< Length of the buffer list */
#if defined(__cplusplus)
    void __user *c_virtual;
#else
    void __user *virtual;       /**< Mmap'd area in user-virtual */
#endif
    drm_buf_pub_t __user *list; /**< Buffer information */
    int fd;
} drm_buf_map_t;

/**
 * DRM_IOCTL_DMA ioctl argument type.
 *
 * Indices here refer to the offset into the buffer list in drm_buf_get.
 *
 * \sa drmDMA().
 */
typedef struct drm_dma {
    int context;              /**< Context handle */
    int send_count;           /**< Number of buffers to send */
    int __user *send_indices;     /**< List of handles to buffers */
    int __user *send_sizes;       /**< Lengths of data to send */
    drm_dma_flags_t flags;        /**< Flags */
    int request_count;        /**< Number of buffers requested */
    int request_size;         /**< Desired size for buffers */
    int __user *request_indices;     /**< Buffer information */
    int __user *request_sizes;
    int granted_count;        /**< Number of buffers granted */
} drm_dma_t;

typedef enum {
    _DRM_CONTEXT_PRESERVED = 0x01,
    _DRM_CONTEXT_2DONLY = 0x02
} drm_ctx_flags_t;

/**
 * DRM_IOCTL_ADD_CTX ioctl argument type.
 *
 * \sa drmCreateContext() and drmDestroyContext().
 */
typedef struct drm_ctx {
    drm_context_t handle;
    drm_ctx_flags_t flags;
} drm_ctx_t;

/**
 * DRM_IOCTL_RES_CTX ioctl argument type.
 */
typedef struct drm_ctx_res {
    int count;
    drm_ctx_t __user *contexts;
} drm_ctx_res_t;


/**
 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
 */
typedef struct drm_draw {
    drm_drawable_t handle;
} drm_draw_t;

/**
 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
 */
typedef enum {
         DRM_DRAWABLE_CLIPRECTS,
} drm_drawable_info_type_t;

typedef struct drm_update_draw {
    drm_drawable_t handle;
    unsigned int type;
    unsigned int num;
    unsigned long long data;
} drm_update_draw_t;

/**
 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
 */
typedef struct drm_auth {
    drm_magic_t magic;
} drm_auth_t;

/**
 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
 *
 * \sa drmGetInterruptFromBusID().
 */
typedef struct drm_irq_busid {
    int irq;    /**< IRQ number */
    int busnum; /**< bus number */
    int devnum; /**< device number */
    int funcnum;    /**< function number */
} drm_irq_busid_t;

typedef enum {
    _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
    _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
    _DRM_VBLANK_FLIP = 0x8000000,   /**< Scheduled buffer swap should flip */
    _DRM_VBLANK_NEXTONMISS = 0x10000000,    /**< If missed, wait for next vblank */
    _DRM_VBLANK_SECONDARY = 0x20000000,     /**< Secondary display controller */
    _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
} drm_vblank_seq_type_t;

#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \
    _DRM_VBLANK_NEXTONMISS)

struct drm_wait_vblank_request {
    drm_vblank_seq_type_t type;
    unsigned int sequence;
    unsigned long signal;
};

struct drm_wait_vblank_reply {
    drm_vblank_seq_type_t type;
    unsigned int sequence;
    long tval_sec;
    long tval_usec;
};

/**
 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
 *
 * \sa drmWaitVBlank().
 */
typedef union drm_wait_vblank {
    struct drm_wait_vblank_request request;
    struct drm_wait_vblank_reply reply;
} drm_wait_vblank_t;

/**
 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
 *
 * \sa drmAgpEnable().
 */
typedef struct drm_agp_mode {
    unsigned long mode; /**< AGP mode */
} drm_agp_mode_t;

/**
 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
 *
 * \sa drmAgpAlloc() and drmAgpFree().
 */
typedef struct drm_agp_buffer {
    unsigned long size; /**< In bytes -- will round to page boundary */
    unsigned long handle;   /**< Used for binding / unbinding */
    unsigned long type; /**< Type of memory to allocate */
    unsigned long physical; /**< Physical used by i810 */
} drm_agp_buffer_t;

/**
 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
 *
 * \sa drmAgpBind() and drmAgpUnbind().
 */
typedef struct drm_agp_binding {
    unsigned long handle;   /**< From drm_agp_buffer */
    unsigned long offset;   /**< In bytes -- will round to page boundary */
} drm_agp_binding_t;

/**
 * DRM_IOCTL_AGP_INFO ioctl argument type.
 *
 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
 * drmAgpVendorId() and drmAgpDeviceId().
 */
typedef struct drm_agp_info {
    int agp_version_major;
    int agp_version_minor;
    unsigned long mode;
    unsigned long aperture_base;   /**< physical address */
    unsigned long aperture_size;   /**< bytes */
    unsigned long memory_allowed;  /**< bytes */
    unsigned long memory_used;

    /** \name PCI information */
    /*@{ */
    unsigned short id_vendor;
    unsigned short id_device;
    /*@} */
} drm_agp_info_t;

/**
 * DRM_IOCTL_SG_ALLOC ioctl argument type.
 */
typedef struct drm_scatter_gather {
    unsigned long size; /**< In bytes -- will round to page boundary */
    unsigned long handle;   /**< Used for mapping / unmapping */
} drm_scatter_gather_t;

/**
 * DRM_IOCTL_SET_VERSION ioctl argument type.
 */
typedef struct drm_set_version {
    int drm_di_major;
    int drm_di_minor;
    int drm_dd_major;
    int drm_dd_minor;
} drm_set_version_t;

/**
 * \name Ioctls Definitions
 */
/*@{*/

#define DRM_IOCTL_BASE          'd'
#define DRM_IO(nr)          _IO(DRM_IOCTL_BASE,nr)
#define DRM_IOR(nr,type)        _IOR(DRM_IOCTL_BASE,nr,type)
#define DRM_IOW(nr,type)        _IOW(DRM_IOCTL_BASE,nr,type)
#define DRM_IOWR(nr,type)       _IOWR(DRM_IOCTL_BASE,nr,type)

#define DRM_IOCTL_VERSION       DRM_IOWR(0x00, drm_version_t)
#define DRM_IOCTL_GET_UNIQUE        DRM_IOWR(0x01, drm_unique_t)
#define DRM_IOCTL_GET_MAGIC     DRM_IOR( 0x02, drm_auth_t)
#define DRM_IOCTL_IRQ_BUSID     DRM_IOWR(0x03, drm_irq_busid_t)
#define DRM_IOCTL_GET_MAP               DRM_IOWR(0x04, drm_map_t)
#define DRM_IOCTL_GET_CLIENT            DRM_IOWR(0x05, drm_client_t)
#define DRM_IOCTL_GET_STATS             DRM_IOR( 0x06, drm_stats_t)
#define DRM_IOCTL_SET_VERSION       DRM_IOWR(0x07, drm_set_version_t)

#define DRM_IOCTL_SET_UNIQUE        DRM_IOW( 0x10, drm_unique_t)
#define DRM_IOCTL_AUTH_MAGIC        DRM_IOW( 0x11, drm_auth_t)
#define DRM_IOCTL_BLOCK         DRM_IOWR(0x12, drm_block_t)
#define DRM_IOCTL_UNBLOCK       DRM_IOWR(0x13, drm_block_t)
#define DRM_IOCTL_CONTROL       DRM_IOW( 0x14, drm_control_t)
#define DRM_IOCTL_ADD_MAP       DRM_IOWR(0x15, drm_map_t)
#define DRM_IOCTL_ADD_BUFS      DRM_IOWR(0x16, drm_buf_desc_t)
#define DRM_IOCTL_MARK_BUFS     DRM_IOW( 0x17, drm_buf_desc_t)
#define DRM_IOCTL_INFO_BUFS     DRM_IOWR(0x18, drm_buf_info_t)
#define DRM_IOCTL_MAP_BUFS      DRM_IOWR(0x19, drm_buf_map_t)
#define DRM_IOCTL_FREE_BUFS     DRM_IOW( 0x1a, drm_buf_free_t)

#define DRM_IOCTL_RM_MAP        DRM_IOW( 0x1b, drm_map_t)

#define DRM_IOCTL_SET_SAREA_CTX     DRM_IOW( 0x1c, drm_ctx_priv_map_t)
#define DRM_IOCTL_GET_SAREA_CTX     DRM_IOWR(0x1d, drm_ctx_priv_map_t)

#define DRM_IOCTL_ADD_CTX       DRM_IOWR(0x20, drm_ctx_t)
#define DRM_IOCTL_RM_CTX        DRM_IOWR(0x21, drm_ctx_t)
#define DRM_IOCTL_MOD_CTX       DRM_IOW( 0x22, drm_ctx_t)
#define DRM_IOCTL_GET_CTX       DRM_IOWR(0x23, drm_ctx_t)
#define DRM_IOCTL_SWITCH_CTX        DRM_IOW( 0x24, drm_ctx_t)
#define DRM_IOCTL_NEW_CTX       DRM_IOW( 0x25, drm_ctx_t)
#define DRM_IOCTL_RES_CTX       DRM_IOWR(0x26, drm_ctx_res_t)
#define DRM_IOCTL_ADD_DRAW      DRM_IOWR(0x27, drm_draw_t)
#define DRM_IOCTL_RM_DRAW       DRM_IOWR(0x28, drm_draw_t)
#define DRM_IOCTL_DMA           DRM_IOWR(0x29, drm_dma_t)
#define DRM_IOCTL_LOCK          DRM_IOW( 0x2a, drm_lock_t)
#define DRM_IOCTL_UNLOCK        DRM_IOW( 0x2b, drm_lock_t)
#define DRM_IOCTL_FINISH        DRM_IOW( 0x2c, drm_lock_t)

#define DRM_IOCTL_AGP_ACQUIRE       DRM_IO(  0x30)
#define DRM_IOCTL_AGP_RELEASE       DRM_IO(  0x31)
#define DRM_IOCTL_AGP_ENABLE        DRM_IOW( 0x32, drm_agp_mode_t)
#define DRM_IOCTL_AGP_INFO      DRM_IOR( 0x33, drm_agp_info_t)
#define DRM_IOCTL_AGP_ALLOC     DRM_IOWR(0x34, drm_agp_buffer_t)
#define DRM_IOCTL_AGP_FREE      DRM_IOW( 0x35, drm_agp_buffer_t)
#define DRM_IOCTL_AGP_BIND      DRM_IOW( 0x36, drm_agp_binding_t)
#define DRM_IOCTL_AGP_UNBIND        DRM_IOW( 0x37, drm_agp_binding_t)

#define DRM_IOCTL_SG_ALLOC      DRM_IOW( 0x38, drm_scatter_gather_t)
#define DRM_IOCTL_SG_FREE       DRM_IOW( 0x39, drm_scatter_gather_t)

#define DRM_IOCTL_WAIT_VBLANK       DRM_IOWR(0x3a, drm_wait_vblank_t)

#define DRM_IOCTL_UPDATE_DRAW           DRM_IOW(0x3f, drm_update_draw_t)
/*@}*/

/**
 * Device specific ioctls should only be in their respective headers
 * The device specific ioctl range is from 0x40 to 0x99.
 * Generic IOCTLS restart at 0xA0.
 *
 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
 * drmCommandReadWrite().
 */
#define DRM_COMMAND_BASE                0x40
#define DRM_COMMAND_END                 0xA0

#endif /* _DRM_H_ */