cvconst.h revision af062818b47340eef15700d2f0211576ba3506ee
af062818b47340eef15700d2f0211576ba3506eevboxsync * File cvconst.h - MS debug information
af062818b47340eef15700d2f0211576ba3506eevboxsync * Copyright (C) 2004, Eric Pouech
af062818b47340eef15700d2f0211576ba3506eevboxsync * This library is free software; you can redistribute it and/or
af062818b47340eef15700d2f0211576ba3506eevboxsync * modify it under the terms of the GNU Lesser General Public
af062818b47340eef15700d2f0211576ba3506eevboxsync * License as published by the Free Software Foundation; either
af062818b47340eef15700d2f0211576ba3506eevboxsync * version 2.1 of the License, or (at your option) any later version.
af062818b47340eef15700d2f0211576ba3506eevboxsync * This library is distributed in the hope that it will be useful,
af062818b47340eef15700d2f0211576ba3506eevboxsync * but WITHOUT ANY WARRANTY; without even the implied warranty of
af062818b47340eef15700d2f0211576ba3506eevboxsync * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
af062818b47340eef15700d2f0211576ba3506eevboxsync * Lesser General Public License for more details.
af062818b47340eef15700d2f0211576ba3506eevboxsync * You should have received a copy of the GNU Lesser General Public
af062818b47340eef15700d2f0211576ba3506eevboxsync * License along with this library; if not, write to the Free Software
af062818b47340eef15700d2f0211576ba3506eevboxsync * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
af062818b47340eef15700d2f0211576ba3506eevboxsync/* information in this file is highly derived from MSDN DIA information pages */
af062818b47340eef15700d2f0211576ba3506eevboxsync/* symbols & types enumeration */
af062818b47340eef15700d2f0211576ba3506eevboxsync/* kind of UDT */
af062818b47340eef15700d2f0211576ba3506eevboxsync/* where a SymTagData is */
af062818b47340eef15700d2f0211576ba3506eevboxsync/* kind of SymTagData */
af062818b47340eef15700d2f0211576ba3506eevboxsync/* values for registers (on different CPUs) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* those values are common to all supported CPUs (and CPU independent) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* Intel x86 CPU */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* <pcode> */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_REG_PCDR3 = 43, /* this includes PCDR4 to PCDR7 */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* </pcode> */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_REG_PSEUDO1 = 116, /* this includes Pseudo02 to Pseudo09 */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_REG_XMM0 = 154, /* this includes XMM1 to XMM7 */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_REG_XMM0L = 194, /* this includes XMM1L to XMM7L */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_REG_XMM0H = 202, /* this includes XMM1H to XMM7H */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* Motorola 68K CPU */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* MIPS 4000 CPU */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_M4_IntA0 = 14, /* this includes IntA1 to IntA3 */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_M4_IntT0 = 18, /* this includes IntT1 to IntT7 */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_M4_IntS0 = 26, /* this includes IntS1 to IntS7 */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_M4_FltF0 = 60, /* this includes FltF1 to Flt31 */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* Alpha AXP CPU */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_ALPHA_FltF0 = 10, /* this includes FltF1 to FltF31 */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* Motorola & IBM PowerPC CPU */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_PPC_FPR0 = 42, /* this includes FPR1 to FPR31 */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* some PPC registers missing */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* Hitachi SH3 CPU */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_SH_XFpR0 = 96, /* this includes XFpR1 to XXFpR15 */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* ARM CPU */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* Intel IA64 CPU */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_IA64_IntR0 = 1024, /* this includes R1 to R127 */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_IA64_FltF0 = 2048, /* this includes FltF1 to FltF127 */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* some IA64 registers missing */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* TriCore CPU */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* some TriCode registers missing */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* AM33 (and the likes) CPU */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* Mitsubishi M32R CPU */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* AMD/Intel x86_64 CPU */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* <pcode> */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_AMD64_PCDR3 = CV_REG_PCDR3, /* this includes PCDR4 to PCDR7 */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_AMD64_CR0 = CV_REG_CR0, /* this includes CR1 to CR4 */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_AMD64_DR0 = CV_REG_DR0, /* this includes DR1 to DR7 */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* </pcode> */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_AMD64_PSEUDO1 = CV_REG_PSEUDO1, /* this includes Pseudo02 to Pseudo09 */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_AMD64_ST0 = CV_REG_ST0, /* this includes ST1 to ST7 */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_AMD64_MM0 = CV_REG_MM0, /* this includes MM1 to MM7 */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_AMD64_XMM0 = CV_REG_XMM0, /* this includes XMM1 to XMM7 */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_AMD64_XMM0L = CV_REG_XMM0L, /* this includes XMM1L to XMM7L */
af062818b47340eef15700d2f0211576ba3506eevboxsync CV_AMD64_XMM0H = CV_REG_XMM0H, /* this includes XMM1H to XMM7H */
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef enum