x86.h revision ed882ec1ed01b0a5469d2acd28d0bf52e38c2103
/** Bit 16 - RF - Resume flag - System flag. */ /** Bit 17 - VM - Virtual 8086 mode - System flag. */ /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */ /** Bit 19 - VIF - Virtual interrupt flag - System flag. */ /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */ /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */ /** Bit 22-31 - 0 - Reserved flag. */ /** Pointer to EFLAGS bits. */ /** Pointer to const EFLAGS bits. */ #
endif /* !VBOX_FOR_DTRACE_LIB */ /** The plain unsigned view. */ /** The bitfield view. */ /** Pointer to EFLAGS. */ /** Pointer to const EFLAGS. */ * RFLAGS (32 upper bits are reserved). /** The plain unsigned view. */ /** The bitfield view. */ /** Pointer to RFLAGS. */ /** Pointer to const RFLAGS. */ /** Bit 0 - CF - Carry flag - Status flag. */ /** Bit 1 - Reserved, reads as 1. */ /** Bit 2 - PF - Parity flag - Status flag. */ /** Bit 4 - AF - Auxiliary carry flag - Status flag. */ /** Bit 6 - ZF - Zero flag - Status flag. */ /** Bit 7 - SF - Signed flag - Status flag. */ /** Bit 8 - TF - Trap flag - System flag. */ /** Bit 9 - IF - Interrupt flag - System flag. */ /** Bit 10 - DF - Direction flag - Control flag. */ /** Bit 11 - OF - Overflow flag - Status flag. */ /** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */ /** Bit 14 - NT - Nested task flag - System flag. */ /** Bit 16 - RF - Resume flag - System flag. */ /** Bit 17 - VM - Virtual 8086 mode - System flag. */ /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */ /** Bit 19 - VIF - Virtual interrupt flag - System flag. */ /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */ /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */ /** The the IOPL level from the flags. */ /** Bits restored by popf */ /** The status bits commonly updated by arithmetic instructions. */ /** CPUID Feature information - ECX. * CPUID query with EAX=1. /** Bit 0 - SSE3 - Supports SSE3 or not. */ /** Bit 1 - PCLMULQDQ. */ /** Bit 2 - DS Area 64-bit layout. */ /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */ /** Bit 5 - VMX - Virtual Machine Technology. */ /** Bit 6 - SMX: Safer Mode Extensions. */ /** Bit 7 - EST - Enh. SpeedStep Tech. */ /** Bit 8 - TM2 - Terminal Monitor 2. */ /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */ /** Bit 10 - CNTX-ID - L1 Context ID. */ /** Bit 11 - Reserved. */ /** Bit 13 - CX16 - CMPXCHG16B. */ /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */ /** Bit 15 - PDCM - Perf/Debug Capability MSR. */ /** Bit 16 - Reserved. */ /** Bit 17 - PCID - Process-context identifiers. */ /** Bit 18 - Direct Cache Access. */ /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */ /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */ /** Bit 22 - MOVBE - Supports MOVBE. */ /** Bit 23 - POPCNT - Supports POPCNT. */ /** Bit 24 - TSC-Deadline. */ /** Bit 26 - XSAVE - Supports XSAVE. */ /** Bit 27 - OSXSAVE - Supports OSXSAVE. */ /** Bit 28 - AVX - Supports AVX instruction extensions. */ /** Bit 29 - 30 - Reserved */ /** Bit 31 - Hypervisor present (we're a guest). */ #
else /* VBOX_FOR_DTRACE_LIB */#
endif /* VBOX_FOR_DTRACE_LIB *//** Pointer to CPUID Feature Information - ECX. */ /** Pointer to const CPUID Feature Information - ECX. */ /** CPUID Feature Information - EDX. * CPUID query with EAX=1. #
ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */ /** Bit 0 - FPU - x87 FPU on Chip. */ /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */ /** Bit 2 - DE - Debugging extensions. */ /** Bit 3 - PSE - Page Size Extension. */ /** Bit 4 - TSC - Time Stamp Counter. */ /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */ /** Bit 6 - PAE - Physical Address Extension. */ /** Bit 7 - MCE - Machine Check Exception. */ /** Bit 8 - CX8 - CMPXCHG8B instruction. */ /** Bit 9 - APIC - APIC On-Chip. */ /** Bit 10 - Reserved. */ /** Bit 11 - SEP - SYSENTER and SYSEXIT. */ /** Bit 12 - MTRR - Memory Type Range Registers. */ /** Bit 13 - PGE - PTE Global Bit. */ /** Bit 14 - MCA - Machine Check Architecture. */ /** Bit 15 - CMOV - Conditional Move Instructions. */ /** Bit 16 - PAT - Page Attribute Table. */ /** Bit 17 - PSE-36 - 36-bit Page Size Extention. */ /** Bit 18 - PSN - Processor Serial Number. */ /** Bit 19 - CLFSH - CLFLUSH Instruction. */ /** Bit 20 - Reserved. */ /** Bit 21 - DS - Debug Store. */ /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */ /** Bit 23 - MMX - Intel MMX 'Technology'. */ /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */ /** Bit 25 - SSE - SSE Support. */ /** Bit 26 - SSE2 - SSE2 Support. */ /** Bit 27 - SS - Self Snoop. */ /** Bit 28 - HTT - Hyper-Threading Technology. */ /** Bit 29 - TM - Thermal Monitor. */ /** Bit 30 - Reserved - . */ /** Bit 31 - PBE - Pending Break Enabled. */ #
else /* VBOX_FOR_DTRACE_LIB */#
endif /* VBOX_FOR_DTRACE_LIB *//** Pointer to CPUID Feature Information - EDX. */ /** Pointer to const CPUID Feature Information - EDX. */ /** @name CPUID Vendor information. * CPUID query with EAX=0. /** @name CPUID Feature information. * CPUID query with EAX=1. /** ECX Bit 0 - SSE3 - Supports SSE3 or not. */ /** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */ /** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */ /** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */ /** ECX Bit 5 - VMX - Virtual Machine Technology. */ /** ECX Bit 6 - SMX - Safer Mode Extensions. */ /** ECX Bit 7 - EST - Enh. SpeedStep Tech. */ /** ECX Bit 8 - TM2 - Terminal Monitor 2. */ /** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */ /** ECX Bit 10 - CNTX-ID - L1 Context ID. */ /** ECX Bit 13 - CX16 - CMPXCHG16B. */ /** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */ /** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */ /** ECX Bit 17 - PCID - Process-context identifiers. */ /** ECX Bit 18 - DCA - Direct Cache Access. */ /** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */ /** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */ /** ECX Bit 21 - x2APIC support. */ /** ECX Bit 22 - MOVBE instruction. */ /** ECX Bit 23 - POPCNT instruction. */ /** ECX Bir 24 - TSC-Deadline. */ /** ECX Bit 25 - AES instructions. */ /** ECX Bit 26 - XSAVE instruction. */ /** ECX Bit 27 - OSXSAVE instruction. */ /** ECX Bit 29 - F16C - Half-precision convert instruction support. */ /** ECX Bit 31 - Hypervisor Present (software only). */ /** Bit 0 - FPU - x87 FPU on Chip. */ /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */ /** Bit 2 - DE - Debugging extensions. */ /** Bit 3 - PSE - Page Size Extension. */ /** Bit 4 - TSC - Time Stamp Counter. */ /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */ /** Bit 6 - PAE - Physical Address Extension. */ /** Bit 7 - MCE - Machine Check Exception. */ /** Bit 8 - CX8 - CMPXCHG8B instruction. */ /** Bit 9 - APIC - APIC On-Chip. */ /** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */ /** Bit 12 - MTRR - Memory Type Range Registers. */ /** Bit 13 - PGE - PTE Global Bit. */ /** Bit 14 - MCA - Machine Check Architecture. */ /** Bit 15 - CMOV - Conditional Move Instructions. */ /** Bit 16 - PAT - Page Attribute Table. */ /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */ /** Bit 18 - PSN - Processor Serial Number. */ /** Bit 19 - CLFSH - CLFLUSH Instruction. */ /** Bit 21 - DS - Debug Store. */ /** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */ /** Bit 23 - MMX - Intel MMX Technology. */ /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */ /** Bit 25 - SSE - SSE Support. */ /** Bit 26 - SSE2 - SSE2 Support. */ /** Bit 27 - SS - Self Snoop. */ /** Bit 28 - HTT - Hyper-Threading Technology. */ /** Bit 29 - TM - Therm. Monitor. */ /** Bit 31 - PBE - Pending Break Enabled. */ * CPUID query with EAX=5. /** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */ /** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */ /** @name CPUID Extended Feature information. * CPUID query with EAX=0x80000001. /** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */ /** EDX Bit 26 - 1 GB large page. */ /** EDX Bit 27 - RDTSCP. */ /** @name CPUID AMD Feature information. * CPUID query with EAX=0x80000001. /** Bit 0 - FPU - x87 FPU on Chip. */ /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */ /** Bit 2 - DE - Debugging extensions. */ /** Bit 3 - PSE - Page Size Extension. */ /** Bit 4 - TSC - Time Stamp Counter. */ /** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */ /** Bit 6 - PAE - Physical Address Extension. */ /** Bit 7 - MCE - Machine Check Exception. */ /** Bit 8 - CX8 - CMPXCHG8B instruction. */ /** Bit 9 - APIC - APIC On-Chip. */ /** Bit 12 - MTRR - Memory Type Range Registers. */ /** Bit 13 - PGE - PTE Global Bit. */ /** Bit 14 - MCA - Machine Check Architecture. */ /** Bit 15 - CMOV - Conditional Move Instructions. */ /** Bit 16 - PAT - Page Attribute Table. */ /** Bit 17 - PSE-36 - 36-bit Page Size Extention. */ /** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */ /** Bit 23 - MMX - Intel MMX Technology. */ /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */ /** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */ /** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */ /** Bit 31 - 3DNOW - AMD 3DNow. */ /** Bit 1 - CMPL - Core multi-processing legacy mode. */ /** Bit 2 - SVM - AMD VM extensions. */ /** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */ /** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */ /** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */ /** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */ /** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */ /** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */ /** Bit 9 - OSVW - AMD OS visible workaround. */ /** Bit 10 - IBS - Instruct based sampling. */ /** Bit 11 - SSE5 - SSE5 instruction support. */ /** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */ /** Bit 13 - WDT - AMD Watchdog timer support. */ /** @name CPUID AMD Feature information. * CPUID query with EAX=0x80000007. /** Bit 0 - TS - Temperature Sensor. */ /** Bit 1 - FID - Frequency ID Control. */ /** Bit 2 - VID - Voltage ID Control. */ /** Bit 3 - TTP - THERMTRIP. */ /** Bit 4 - TM - Hardware Thermal Control. */ /** Bit 5 - STC - Software Thermal Control. */ /** Bit 6 - MC - 100 Mhz Multiplier Control. */ /** Bit 7 - HWPSTATE - Hardware P-State Control. */ /** Bit 8 - TSCINVAR - TSC Invariant. */ /** Bit 0 - PE - Protection Enabled */ /** Bit 1 - MP - Monitor Coprocessor */ /** Bit 2 - EM - Emulation. */ /** Bit 3 - TS - Task Switch. */ /** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */ /** Bit 5 - NE - Numeric error. */ /** Bit 16 - WP - Write Protect. */ /** Bit 18 - AM - Alignment Mask. */ /** Bit 29 - NW - Not Write-though. */ /** Bit 30 - WP - Cache Disable. */ /** Bit 31 - PG - Paging. */ /** Bit 3 - PWT - Page-level Writes Transparent. */ /** Bit 4 - PCD - Page-level Cache Disable. */ /** Bits 12-31 - - Page directory page number. */ /** Bits 5-31 - - PAE Page directory page number. */ /** Bits 12-51 - - AMD64 Page directory page number. */ /** Bit 0 - VME - Virtual-8086 Mode Extensions. */ /** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */ /** Bit 2 - TSD - Time Stamp Disable. */ /** Bit 3 - DE - Debugging Extensions. */ /** Bit 4 - PSE - Page Size Extension. */ /** Bit 5 - PAE - Physical Address Extension. */ /** Bit 6 - MCE - Machine-Check Enable. */ /** Bit 7 - PGE - Page Global Enable. */ /** Bit 8 - PCE - Performance-Monitoring Counter Enable. */ /** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */ /** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */ /** Bit 13 - VMXE - VMX mode is enabled. */ /** Bit 14 - SMXE - Safer Mode Extensions Enabled. */ /** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */ /** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor /** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */ /** Bit 0 - B0 - Breakpoint 0 condition detected. */ /** Bit 1 - B1 - Breakpoint 1 condition detected. */ /** Bit 2 - B2 - Breakpoint 2 condition detected. */ /** Bit 3 - B3 - Breakpoint 3 condition detected. */ /** Mask of all the Bx bits. */ /** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */ /** Bit 14 - BS - Single step */ /** Bit 15 - BT - Task switch. (TSS T bit.) */ /** Bits which must be 1s in DR6. */ /** Bits which must be 0s in DR6. */ /** Bits which must be 0s on writes to DR6. */ /** Get the DR6.Bx bit for a the given breakpoint. */ /** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */ /** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */ /** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */ /** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */ /** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */ /** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */ /** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */ /** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */ /** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */ /** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */ /** L0, L1, L2, and L3. */ /** L0, L1, L2, and L3. */ /** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when * any DR register is accessed. */ /** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */ /** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */ /** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */ /** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */ /** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */ /** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */ /** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */ /** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */ /** Bits which reads as 1s. */ /** Bits which reads as zeros. */ /** Bits which must be 0s when writing to DR7. */ /** Calcs the L bit of Nth breakpoint. * @param iBp The breakpoint number [0..3]. /** Calcs the G bit of Nth breakpoint. * @param iBp The breakpoint number [0..3]. /** Calcs the L and G bits of Nth breakpoint. * @param iBp The breakpoint number [0..3]. /** Break on instruction fetch only. */ /** Break on write only. */ /** Break on I/O read/write. This is only defined if CR4.DE is set. */ /** Break on read or write (but not instruction fetches). */ /** Shifts a X86_DR7_RW_* value to its right place. * @param iBp The breakpoint number [0..3]. * @param fRw One of the X86_DR7_RW_* value. /** Fetch the the R/Wx bits for a given breakpoint (so it can be compared with * one of the X86_DR7_RW_XXX constants). * @returns X86_DR7_RW_XXX * @param iBp The breakpoint number [0..3]. /** Checks if there are any I/O breakpoint types configured in the RW * registers. Does NOT check if these are enabled, sorry. */ /** Shifts a X86_DR7_LEN_* value to its right place. * @param iBp The breakpoint number [0..3]. * @param cb One of the X86_DR7_LEN_* values. /** Fetch the breakpoint length bits from the DR7 value. * @param iBp The breakpoint number [0..3]. /** Mask used to check if any breakpoints are enabled. */ /** LEN0, LEN1, LEN2, and LEN3. */ /** @name Machine Specific Registers /** Machine check address register (P5). */ /** Machine check type register (P5). */ /** Time Stamp Counter. */ /** Local APIC enabled. */ /** X2APIC enabled (requires the EN bit to be set). */ /** The processor is the boot strap processor (BSP). */ /** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual /** Undocumented intel MSR for reporting thread and core counts. * Judging from the XNU sources, it seems to be introduced in Nehalem. The * first 16 bits is the thread count. The next 16 bits the core count, except * on Westmere where it seems it's only the next 4 bits for some reason. */ /** CPU Feature control. */ /** BIOS update trigger (microcode update). */ /** BIOS update signature (microcode). */ /** General performance counter no. 0. */ /** General performance counter no. 1. */ /** General performance counter no. 2. */ /** General performance counter no. 3. */ /** Nehalem power control. */ /** Get FSB clock status (Intel-specific). */ /** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */ /** C0 Maximum Frequency Clock Count */ /** C0 Actual Frequency Clock Count */ /** MTRR Capabilities. */ /** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS. /** SYSENTER_ESP - the R0 ESP. */ /** SYSENTER_EIP - the R0 EIP. */ /** Machine Check Global Capabilities Register. */ /** Machine Check Global Status Register. */ /** Machine Check Global Control Register. */ /** Page Attribute Table. */ /** Performance counter MSRs. (Intel only) */ /** Flexible ratio, seems to be undocumented, used by XNU (tsc.c). * The 16th bit whether flex ratio is being used, in which case bits 15:8 * holds a ratio that Apple takes for TSC granularity. * @note This MSR conflics the P4 MSR_MCG_R12 register. */ /** Performance state value and starting with Intel core more. * Apple uses the >=core features to determine TSC granularity on older CPUs. */ /** Enable misc. processor features (R/W). */ /** Enable fast-strings feature (for REP MOVS and REP STORS). */ /** Automatic Thermal Control Circuit Enable (R/W). */ /** Performance Monitoring Available (R). */ /** Branch Trace Storage Unavailable (R/O). */ /** Precise Event Based Sampling (PEBS) Unavailable (R/O). */ /** Enhanced Intel SpeedStep Technology Enable (R/W). */ /** Limit CPUID Maxval to 3 leafs (R/W). */ /** When set to 1, xTPR messages are disabled (R/W). */ /** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */ /** The number (0..3 or 0..15) of the last branch record register on P4 and /** @name Last branch registers for P4 and Xeon, models 0 thru 2. /** MTRR Default Range. */ /** Basic VMX information. */ /** Allowed settings for pin-based VM execution controls */ /** Allowed settings for proc-based VM execution controls */ /** Allowed settings for the VMX exit controls. */ /** Allowed settings for the VMX entry controls. */ /** Fixed cleared bits in CR0. */ /** Fixed set bits in CR0. */ /** Fixed cleared bits in CR4. */ /** Fixed set bits in CR4. */ /** Information for enumerating fields in the VMCS. */ /** Allowed settings for the VM-functions controls. */ /** Allowed settings for secondary proc-based VM execution controls */ /** DS Save Area (R/W). */ /** Running Average Power Limit (RAPL) power units. */ /** X2APIC MSR ranges. */ /** K6 EFER - Extended Feature Enable Register. */ /** @todo document EFER */ /** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */ /** Bit 8 - LME - Long mode enabled. (R/W) */ /** Bit 10 - LMA - Long mode active. (R) */ /** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */ /** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */ /** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */ /** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */ /** Shift value for getting the SYSRET CS and SS value. */ /** Shift value for getting the SYSCALL CS and SS value. */ /** Selector mask for use after shifting. */ /** The mask which give the SYSCALL EIP. */ /** K6 WHCR - Write Handling Control Register. */ /** K6 UWCCR - UC/WC Cacheability Control Register. */ /** K6 PSOR - Processor State Observability Register. */ /** Performance counter MSRs. (AMD only) */ /** K8 LSTAR - Long mode SYSCALL target (RIP). */ /** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */ /** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */ /** K8 FS.base - The 64-bit base FS register. */ /** K8 GS.base - The 64-bit base GS register. */ /** K8 KernelGSbase - Used with SWAPGS. */ /** K8 TSC_AUX - Used with RDTSCP. */ /** North bridge config? See BIOS & Kernel dev guides for /** Hypertransport interrupt pending register. * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */ /** SVM - VM_HSAVE_PA - Physical address for saving and restoring * host state during world switch. */ /** @name Page Table / Directory / Directory Pointers / L4. /** Pointer to a page table/directory table entry as an unsigned integer. */ /** Pointer to an const page table/directory table entry as an unsigned integer. */ /** Number of entries in a 32-bit PT/PD. */ /** Number of entries in a PAE PT/PD. */ /** Number of entries in a PAE PDPT. */ /** Number of entries in an AMD64 PDPT. * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */ /** The size of a 4KB page. */ /** The page shift of a 4KB page. */ /** The 4KB page offset mask. */ /** The 4KB page base mask for virtual addresses. */ /** The 4KB page base mask for virtual addresses - 32bit version. */ /** The size of a 2MB page. */ /** The page shift of a 2MB page. */ /** The 2MB page offset mask. */ /** The 2MB page base mask for virtual addresses. */ /** The 2MB page base mask for virtual addresses - 32bit version. */ /** The size of a 4MB page. */ /** The page shift of a 4MB page. */ /** The 4MB page offset mask. */ /** The 4MB page base mask for virtual addresses. */ /** The 4MB page base mask for virtual addresses - 32bit version. */ * Check if the given address is canonical. /** @name Page Table Entry /** Bit 0 - P - Present bit. */ /** Bit 1 - R/W - Read (clear) / Write (set) bit. */ /** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */ /** Bit 3 - PWT - Page level write thru bit. */ /** Bit 4 - PCD - Page level cache disable bit. */ /** Bit 5 - A - Access bit. */ /** Bit 6 - D - Dirty bit. */ /** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */ /** Bit 8 - G - Global flag. */ /** Bit 0 - P - Present bit mask. */ /** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */ /** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */ /** Bit 3 - PWT - Page level write thru bit mask. */ /** Bit 4 - PCD - Page level cache disable bit mask. */ /** Bit 5 - A - Access bit mask. */ /** Bit 6 - D - Dirty bit mask. */ /** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */ /** Bit 8 - G - Global bit mask. */ /** Bits 9-11 - - Available for use to system software. */ /** Bits 12-31 - - Physical Page number of the next level. */ /** Bits 12-51 - - PAE - Physical Page number of the next level. */ /** Bits 63 - NX - PAE/LM - No execution flag. */ /** Bits 62-52 - - PAE - MBZ bits when NX is active. */ /** Bits 63-52 - - PAE - MBZ bits when no NX. */ /** No bits - - LM - MBZ bits when NX is active. */ /** Bits 63 - - LM - MBZ bits when no NX. */ /** Flags whether(=1) or not the page is present. */ /** Read(=0) / Write(=1) flag. */ /** User(=1) / Supervisor (=0) flag. */ /** Write Thru flag. If PAT enabled, bit 0 of the index. */ /** Cache disabled flag. If PAT enabled, bit 1 of the index. */ * Indicates that the page have been read or written to. */ * Indicates that the page has been written to. */ /** Reserved / If PAT enabled, bit 2 of the index. */ /** Global flag. (Ignored in all but final level.) */ /** Available for use to system software. */ /** Physical Page number of the next level. */ /** Pointer to a page table entry. */ /** Pointer to a const page table entry. */ /** Unsigned integer view */ /** Pointer to a page table entry. */ /** Pointer to a const page table entry. */ /** Flags whether(=1) or not the page is present. */ /** Read(=0) / Write(=1) flag. */ /** User(=1) / Supervisor(=0) flag. */ /** Write Thru flag. If PAT enabled, bit 0 of the index. */ /** Cache disabled flag. If PAT enabled, bit 1 of the index. */ * Indicates that the page have been read or written to. */ * Indicates that the page has been written to. */ /** Reserved / If PAT enabled, bit 2 of the index. */ /** Global flag. (Ignored in all but final level.) */ /** Available for use to system software. */ /** Physical Page number of the next level - Low Part. Don't use this. */ /** Physical Page number of the next level - High Part. Don't use this. */ /** Pointer to a page table entry. */ /** Pointer to a page table entry. */ /** Unsigned integer view */ /** Pointer to a PAE page table entry. */ /** Pointer to a const PAE page table entry. */ /** Pointer to a page table. */ /** Pointer to a const page table. */ /** The page shift to get the PT index. */ /** The PT index mask (apply to a shifted page address). */ /** Pointer to a page table. */ /** Pointer to a const page table. */ /** The page shift to get the PA PTE index. */ /** The PAE PT index mask (apply to a shifted page address). */ /** @name 4KB Page Directory Entry /** Bit 0 - P - Present bit. */ /** Bit 1 - R/W - Read (clear) / Write (set) bit. */ /** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */ /** Bit 3 - PWT - Page level write thru bit. */ /** Bit 4 - PCD - Page level cache disable bit. */ /** Bit 5 - A - Access bit. */ /** Bit 7 - PS - Page size attribute. * Clear mean 4KB pages, set means large pages (2/4MB). */ /** Bits 9-11 - - Available for use to system software. */ /** Bits 12-31 - - Physical Page number of the next level. */ /** Bits 12-51 - - PAE - Physical Page number of the next level. */ /** Bits 63 - NX - PAE/LM - No execution flag. */ /** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */ /** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */ /** Bit 7 - - LM - MBZ bits when NX is active. */ /** Bits 63, 7 - - LM - MBZ bits when no NX. */ /** Flags whether(=1) or not the page is present. */ /** Read(=0) / Write(=1) flag. */ /** User(=1) / Supervisor (=0) flag. */ /** Write Thru flag. If PAT enabled, bit 0 of the index. */ /** Cache disabled flag. If PAT enabled, bit 1 of the index. */ * Indicates that the page has been read or written to. */ /** Reserved / Ignored (dirty bit). */ /** Size bit if PSE is enabled - in any event it's 0. */ /** Reserved / Ignored (global bit). */ /** Available for use to system software. */ /** Physical Page number of the next level. */ /** Pointer to a page directory entry. */ /** Pointer to a const page directory entry. */ * PAE page directory entry. /** Flags whether(=1) or not the page is present. */ /** Read(=0) / Write(=1) flag. */ /** User(=1) / Supervisor (=0) flag. */ /** Write Thru flag. If PAT enabled, bit 0 of the index. */ /** Cache disabled flag. If PAT enabled, bit 1 of the index. */ * Indicates that the page has been read or written to. */ /** Reserved / Ignored (dirty bit). */ /** Size bit if PSE is enabled - in any event it's 0. */ /** Reserved / Ignored (global bit). / */ /** Available for use to system software. */ /** Physical Page number of the next level - Low Part. Don't use! */ /** Physical Page number of the next level - High Part. Don't use! */ /** Pointer to a page directory entry. */ /** Pointer to a const page directory entry. */ /** @name 2/4MB Page Directory Entry /** Bit 0 - P - Present bit. */ /** Bit 1 - R/W - Read (clear) / Write (set) bit. */ /** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */ /** Bit 3 - PWT - Page level write thru bit. */ /** Bit 4 - PCD - Page level cache disable bit. */ /** Bit 5 - A - Access bit. */ /** Bit 6 - D - Dirty bit. */ /** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */ /** Bit 8 - G - Global flag. */ /** Bits 9-11 - AVL - Available for use to system software. */ /** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */ /** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */ /** Bits 22-31 - - Physical Page number. */ /** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */ /** The number of bits to the high part of the page number. */ /** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */ /** Bits 21-51 - - PAE/LM - Physical Page number. * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */ /** Bits 63 - NX - PAE/LM - No execution flag. */ /** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */ /** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */ /** Bits 20-13 - - LM - MBZ bits when NX is active. */ /** Bits 63, 20-13 - - LM - MBZ bits when no NX. */ * 4MB page directory entry. /** Flags whether(=1) or not the page is present. */ /** Read(=0) / Write(=1) flag. */ /** User(=1) / Supervisor (=0) flag. */ /** Write Thru flag. If PAT enabled, bit 0 of the index. */ /** Cache disabled flag. If PAT enabled, bit 1 of the index. */ * Indicates that the page have been read or written to. */ * Indicates that the page has been written to. */ /** Page size flag - always 1 for 4MB entries. */ /** Available for use to system software. */ /** Reserved / If PAT enabled, bit 2 of the index. */ /** Bits 32-39 of the page number on AMD64. * This AMD64 hack allows accessing 40bits of physical memory without PAE. */ /** Physical Page number of the page. */ /** Pointer to a page table entry. */ /** Pointer to a const page table entry. */ * 2MB PAE page directory entry. /** Flags whether(=1) or not the page is present. */ /** Read(=0) / Write(=1) flag. */ /** User(=1) / Supervisor(=0) flag. */ /** Write Thru flag. If PAT enabled, bit 0 of the index. */ /** Cache disabled flag. If PAT enabled, bit 1 of the index. */ * Indicates that the page have been read or written to. */ * Indicates that the page has been written to. */ /** Page size flag - always 1 for 2MB entries. */ /** Available for use to system software. */ /** Reserved / If PAT enabled, bit 2 of the index. */ /** Physical Page number of the next level - Low part. Don't use! */ /** Physical Page number of the next level - High part. Don't use! */ /** Pointer to a 2MB PAE page table entry. */ /** Pointer to a 2MB PAE page table entry. */ /** Unsigned integer view. */ /** 8 bit unsigned integer view. */ /** 16 bit unsigned integer view. */ /** 32 bit unsigned integer view. */ /** Pointer to a page directory entry. */ /** Pointer to a const page directory entry. */ * PAE page directory entry. /** Unsigned integer view. */ /** 2MB page view (big). */ /** 8 bit unsigned integer view. */ /** 16 bit unsigned integer view. */ /** 32 bit unsigned integer view. */ /** Pointer to a page directory entry. */ /** Pointer to a const page directory entry. */ /** Pointer to a page directory. */ /** Pointer to a const page directory. */ /** The page shift to get the PD index. */ /** The PD index mask (apply to a shifted page address). */ /** Pointer to a PAE page directory. */ /** Pointer to a const PAE page directory. */ /** The page shift to get the PAE PD index. */ /** The PAE PD index mask (apply to a shifted page address). */ /** @name Page Directory Pointer Table Entry (PAE) /** Bit 0 - P - Present bit. */ /** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */ /** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */ /** Bit 3 - PWT - Page level write thru bit. */ /** Bit 4 - PCD - Page level cache disable bit. */ /** Bit 5 - A - Access bit. Long Mode only. */ /** Bit 7 - PS - Page size (1GB). Long Mode only. */ /** Bits 9-11 - - Available for use to system software. */ /** Bits 12-51 - - PAE - Physical Page number of the next level. */ /** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */ /** Bits 63 - NX - LM - No execution flag. Long Mode only. */ /** Bits 8, 7 - - LM - MBZ bits when NX is active. */ /** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */ /** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */ /** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */ * Page directory pointer table entry. /** Flags whether(=1) or not the page is present. */ /** Chunk of reserved bits. */ /** Write Thru flag. If PAT enabled, bit 0 of the index. */ /** Cache disabled flag. If PAT enabled, bit 1 of the index. */ /** Chunk of reserved bits. */ /** Available for use to system software. */ /** Physical Page number of the next level - Low Part. Don't use! */ /** Physical Page number of the next level - High Part. Don't use! */ /** Pointer to a page directory pointer table entry. */ /** Pointer to a const page directory pointer table entry. */ * Page directory pointer table entry. AMD64 version /** Flags whether(=1) or not the page is present. */ /** Read(=0) / Write(=1) flag. */ /** User(=1) / Supervisor (=0) flag. */ /** Write Thru flag. If PAT enabled, bit 0 of the index. */ /** Cache disabled flag. If PAT enabled, bit 1 of the index. */ * Indicates that the page have been read or written to. */ /** Chunk of reserved bits. */ /** Available for use to system software. */ /** Physical Page number of the next level - Low Part. Don't use! */ /** Physical Page number of the next level - High Part. Don't use! */ /** Pointer to a page directory pointer table entry. */ /** Pointer to a const page directory pointer table entry. */ * Page directory pointer table entry. /** Unsigned integer view. */ /** 8 bit unsigned integer view. */ /** 16 bit unsigned integer view. */ /** 32 bit unsigned integer view. */ /** Pointer to a page directory pointer table entry. */ /** Pointer to a const page directory pointer table entry. */ * Page directory pointer table. /** Pointer to a page directory pointer table. */ /** Pointer to a const page directory pointer table. */ /** The page shift to get the PDPT index. */ /** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */ /** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/ /** @name Page Map Level-4 Entry (Long Mode PAE) /** Bit 0 - P - Present bit. */ /** Bit 1 - R/W - Read (clear) / Write (set) bit. */ /** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */ /** Bit 3 - PWT - Page level write thru bit. */ /** Bit 4 - PCD - Page level cache disable bit. */ /** Bit 5 - A - Access bit. */ /** Bits 9-11 - - Available for use to system software. */ /** Bits 12-51 - - PAE - Physical Page number of the next level. */ /** Bits 8, 7 - - MBZ bits when NX is active. */ /** Bits 63, 7 - - MBZ bits when no NX. */ /** Bits 63 - NX - PAE - No execution flag. */ /** Flags whether(=1) or not the page is present. */ /** Read(=0) / Write(=1) flag. */ /** User(=1) / Supervisor (=0) flag. */ /** Write Thru flag. If PAT enabled, bit 0 of the index. */ /** Cache disabled flag. If PAT enabled, bit 1 of the index. */ * Indicates that the page have been read or written to. */ /** Chunk of reserved bits. */ /** Available for use to system software. */ /** Physical Page number of the next level - Low Part. Don't use! */ /** Physical Page number of the next level - High Part. Don't use! */ /** Pointer to a page map level-4 entry. */ /** Pointer to a const page map level-4 entry. */ * Page Map Level-4 Entry. /** Unsigned integer view. */ /** 8 bit unsigned integer view. */ /** 16 bit unsigned integer view. */ /** 32 bit unsigned integer view. */ /** Pointer to a page map level-4 entry. */ /** Pointer to a const page map level-4 entry. */ /** Pointer to a page map level-4. */ /** Pointer to a const page map level-4. */ /** The page shift to get the PML4 index. */ /** The PML4 index mask (apply to a shifted page address). */ * 32-bit protected mode FSTENV image. /** Pointer to a 32-bit protected mode FSTENV image. */ /** Pointer to a const 32-bit protected mode FSTENV image. */ * 80-bit MMX/FPU register type. /** Pointer to a 80-bit MMX/FPU register type. */ /** Pointer to a const 80-bit MMX/FPU register type. */ /** 0x00 - Control word. */ /** 0x02 - Alignment word */ /** 0x04 - Status word. */ /** 0x06 - Alignment word */ /** 0x0a - Alignment word */ /** 0x0c - Instruction pointer. */ /** 0x10 - Code selector. */ /** Extended precision floating point view. */ /** Extended precision floating point view v2. */ /** 128-bit view. (yeah, very helpful) */ /** Pointer to a FPU state. */ /** Pointer to a const FPU state. */ /** 0x00 - Control word. */ /** 0x02 - Status word. */ /** 0x04 - Tag word. (The upper byte is always zero.) */ /** 0x08 - Instruction pointer. */ /** 0x0c - Code selector. */ /** 0x10 - Data pointer. */ /** 0x14 - Data segment */ /** Extended precision floating point view. */ /** Extended precision floating point view v2 */ /** 128-bit view. (yeah, very helpful) */ /** XMM Register view *. */ /** 128-bit view. (yeah, very helpful) */ }
aXMM[
16];
/* 8 registers in 32 bits mode; 16 in long mode *//** Pointer to a FPU Extended state. */ /** Pointer to a const FPU Extended state. */ /** @name FPU status word flags. /** Exception Flag: Invalid operation. */ /** Exception Flag: Denormalized operand. */ /** Exception Flag: Zero divide. */ /** Exception Flag: Overflow. */ /** Exception Flag: Underflow. */ /** Exception Flag: Precision. */ /** Error summary status. */ /** Mask of exceptions flags, excluding the summary bit. */ /** Mask of exceptions flags, including the summary bit. */ /** Top of the stack mask. */ /** Mask for getting TOP value after shifting it right. */ /** Get the TOP value. */ /** Mask of exceptions flags, including the summary bit. */ /** @name FPU control word flags. /** Exception Mask: Invalid operation. */ /** Exception Mask: Denormalized operand. */ /** Exception Mask: Zero divide. */ /** Exception Mask: Overflow. */ /** Exception Mask: Underflow. */ /** Exception Mask: Precision. */ /** Mask all exceptions, the value typically loaded (by for instance fninit). * @remarks This includes reserved bit 6. */ /** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */ /** Precision control mask. */ /** Precision control: 24-bit. */ /** Precision control: Reserved. */ /** Precision control: 53-bit. */ /** Precision control: 64-bit. */ /** Rounding control mask. */ /** Rounding control: To nearest. */ /** Rounding control: Down. */ /** Rounding control: Up. */ /** Rounding control: Towards zero. */ /** Bits which should be zero, apparently. */ /** Exception Flag: Invalid operation. */ /** Exception Flag: Denormalized operand. */ /** Exception Flag: Zero divide. */ /** Exception Flag: Overflow. */ /** Exception Flag: Underflow. */ /** Exception Flag: Precision. */ /** Denormals are zero. */ /** Exception Mask: Invalid operation. */ /** Exception Mask: Denormalized operand. */ /** Exception Mask: Zero divide. */ /** Exception Mask: Overflow. */ /** Exception Mask: Underflow. */ /** Exception Mask: Precision. */ /** Rounding control mask. */ /** Rounding control: To nearest. */ /** Rounding control: Down. */ /** Rounding control: Up. */ /** Rounding control: Towards zero. */ /** Flush-to-zero for masked underflow. */ /** Misaligned Exception Mask. */ /** @name Selector Descriptor * Descriptor attributes (as seen by VT-x). /** 00 - Segment Type. */ /** 04 - Descriptor Type. System(=0) or code/data selector */ /** 05 - Descriptor Privelege level. */ /** 07 - Flags selector present(=1) or not. */ /** 08 - Segment limit 16-19. */ /** 0c - Available for system software. */ /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */ /** 0e - This flags meaning depends on the segment type. Try make sense out * of the intel manual yourself. */ /** 0f - Granularity of the limit. If set 4KB granularity is used, if /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */ #
endif /* !VBOX_FOR_DTRACE_LIB *//** @name X86DESCATTR masks /** Unsigned integer view. */ /** Pointer to descriptor attributes. */ /** Pointer to const descriptor attributes. */ * Generic descriptor table entry /** 00 - Limit - Low word. */ /** 10 - Base address - lowe word. * Don't try set this to 24 because MSC is doing stupid things then. */ /** 20 - Base address - first 8 bits of high word. */ /** 28 - Segment Type. */ /** 2c - Descriptor Type. System(=0) or code/data selector */ /** 2d - Descriptor Privelege level. */ /** 2f - Flags selector present(=1) or not. */ /** 30 - Segment limit 16-19. */ /** 34 - Available for system software. */ /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */ /** 36 - This flags meaning depends on the segment type. Try make sense out * of the intel manual yourself. */ /** 37 - Granularity of the limit. If set 4KB granularity is used, if /** 38 - Base address - highest 8 bits. */ /** Pointer to a generic descriptor entry. */ /** Pointer to a const generic descriptor entry. */ /** @name Bit offsets of X86DESCGENERIC members. * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy). /** 00 - Target code segment offset - Low word. * Ignored if task-gate. */ /** 10 - Target code segment selector for call-, interrupt- and trap-gates, * TSS selector if task-gate. */ /** 20 - Number of parameters for a call-gate. * Ignored if interrupt-, trap- or task-gate. */ /** 24 - Reserved / ignored. */ /** 28 - Segment Type. */ /** 2c - Descriptor Type (0 = system). */ /** 2d - Descriptor Privelege level. */ /** 2f - Flags selector present(=1) or not. */ /** 30 - Target code segment offset - High word. * Ignored if task-gate. */ /** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */ /** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */ #
endif /* VBOX_FOR_DTRACE_LIB */ * Descriptor table entry. /** Generic descriptor view. */ /** Gate descriptor view. */ /** 8 bit unsigned integer view. */ /** 16 bit unsigned integer view. */ /** 32 bit unsigned integer view. */ /** 64 bit unsigned integer view. */ /** Unsigned integer view. */ /** Pointer to descriptor table entry. */ /** Pointer to const descriptor table entry. */ * Return the base address of a descriptor. * Return the limit of a descriptor. * Return the limit of a descriptor with the granularity bit taken into account. * @returns Selector limit (uint32_t). * @param a_pDesc Pointer to the descriptor. /** @def X86DESC_GET_HID_ATTR * Get the descriptor attributes for the hidden register. ( ((
a_pDesc)->u >> (
16+
16+
8)) &
UINT32_C(
0xf0ff) )
/** @todo do we have a define for 0xf0ff? */ * 64 bits generic descriptor table entry * Note: most of these bits have no meaning in long mode. /** Limit - Low word - *IGNORED*. */ /** Base address - low word. - *IGNORED* * Don't try set this to 24 because MSC is doing stupid things then. */ /** Base address - first 8 bits of high word. - *IGNORED* */ /** Descriptor Type. System(=0) or code/data selector */ /** Descriptor Privelege level. */ /** Flags selector present(=1) or not. */ /** Segment limit 16-19. - *IGNORED* */ /** Available for system software. - *IGNORED* */ /** This flags meaning depends on the segment type. Try make sense out * of the intel manual yourself. */ /** Granularity of the limit. If set 4KB granularity is used, if * clear byte. - *IGNORED* */ /** Base address - highest 8 bits. - *IGNORED* */ /** Base address - bits 63-32. */ /** Pointer to a generic descriptor entry. */ /** Pointer to a const generic descriptor entry. */ * System descriptor table entry (64 bits) * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC... /** Base address - lowe word. * Don't try set this to 24 because MSC is doing stupid things then. */ /** Base address - first 8 bits of high word. */ /** Descriptor Type. System(=0) or code/data selector */ /** Descriptor Privelege level. */ /** Flags selector present(=1) or not. */ /** Segment limit 16-19. */ /** Available for system software. */ /** This flags meaning depends on the segment type. Try make sense out * of the intel manual yourself. */ /** Granularity of the limit. If set 4KB granularity is used, if /** Base address - bits 31-24. */ /** Base address - bits 63-32. */ /** Pointer to a system descriptor entry. */ /** Pointer to a const system descriptor entry. */ * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit). /** Target code segment offset - Low word. */ /** Target code segment selector. */ /** Interrupt stack table for interrupt- and trap-gates. * Ignored by call-gates. */ /** Reserved / ignored. */ /** Descriptor Type (0 = system). */ /** Descriptor Privelege level. */ /** Flags selector present(=1) or not. */ /** Target code segment offset - High word. * Ignored if task-gate. */ /** Target code segment offset - Top dword. * Ignored if task-gate. */ /** Reserved / ignored / must be zero. * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */ /** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */ /** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */ #
endif /* VBOX_FOR_DTRACE_LIB */ * Descriptor table entry. /** Generic descriptor view. */ /** System descriptor view. */ /** Gate descriptor view. */ /** 8 bit unsigned integer view. */ /** 16 bit unsigned integer view. */ /** 32 bit unsigned integer view. */ /** 64 bit unsigned integer view. */ /** Pointer to descriptor table entry. */ /** Pointer to const descriptor table entry. */ * Return the base of a 64-bit descriptor. /** @name Host system descriptor table entry - Use with care! /** Host system descriptor table entry. */ /** Pointer to a host system descriptor table entry. */ /** Pointer to a const host system descriptor table entry. */ /** @name Selector Descriptor Types. /** @name Non-System Selector Types. /** Code(=set)/Data(=clear) bit. */ /** Memory(=set)/System(=clear) bit. */ /** Expand down bit (for data selectors only). */ /** Conforming bit (for code selectors only). */ /** Write bit (for data selectors only). */ /** Read bit (for code selectors only). */ /** The bit number of the code segment read bit (relative to u4Type). */ /** Read only selector type. */ /** Accessed read only selector type. */ /** Read write selector type. */ /** Accessed read write selector type. */ /** Expand down read only selector type. */ /** Accessed expand down read only selector type. */ /** Expand down read write selector type. */ /** Accessed expand down read write selector type. */ /** Execute only selector type. */ /** Accessed execute only selector type. */ /** Execute and read selector type. */ /** Accessed execute and read selector type. */ /** Conforming execute only selector type. */ /** Accessed Conforming execute only selector type. */ /** Conforming execute and write selector type. */ /** Accessed Conforming execute and write selector type. */ /** @name System Selector Types. /** The TSS busy bit mask. */ /** Undefined system selector type. */ /** 286 TSS selector - Busy. */ /** 286 Callgate selector. */ /** Taskgate selector. */ /** 286 Interrupt gate selector. */ /** 286 Trapgate selector. */ /** Undefined system selector. */ /** Undefined system selector. */ /** 386 TSS selector - Busy. */ /** 386 Callgate selector. */ /** Undefined system selector. */ /** 386 Interruptgate selector. */ /** 386 Trapgate selector. */ /** @name AMD64 System Selector Types. /** TSS selector - Busy. */ /** TSS selector - Busy. */ /** Callgate selector. */ /** Interruptgate selector. */ /** Trapgate selector. */ /** @name Descriptor Table Entry Flag Masks. * These are for the 2nd 32-bit word of a descriptor. /** Bits 8-11 - TYPE - Descriptor type mask. */ /** Bit 12 - S - System (=0) or Code/Data (=1). */ /** Bits 13-14 - DPL - Descriptor Privilege Level. */ /** Bit 15 - P - Present. */ /** Bit 20 - AVL - Available for system software. */ /** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */ /** Bit 23 - G - Granularity of the limit. If set 4KB granularity is * used, if clear byte. */ * 16-bit Task Segment (TSS). /** Back link to previous task. (static) */ /** Ring-0 stack pointer. (static) */ /** Ring-0 stack segment. (static) */ /** Ring-1 stack pointer. (static) */ /** Ring-1 stack segment. (static) */ /** Ring-2 stack pointer. (static) */ /** Ring-2 stack segment. (static) */ /** IP before task switch. */ /** FLAGS before task switch. */ /** AX before task switch. */ /** CX before task switch. */ /** DX before task switch. */ /** BX before task switch. */ /** SP before task switch. */ /** BP before task switch. */ /** SI before task switch. */ /** DI before task switch. */ /** ES before task switch. */ /** CS before task switch. */ /** SS before task switch. */ /** DS before task switch. */ /** LDTR before task switch. */ /** Pointer to a 16-bit task segment. */ /** Pointer to a const 16-bit task segment. */ * 32-bit Task Segment (TSS). /** Back link to previous task. (static) */ /** Ring-0 stack pointer. (static) */ /** Ring-0 stack segment. (static) */ /** Ring-1 stack pointer. (static) */ /** Ring-1 stack segment. (static) */ /** Ring-2 stack pointer. (static) */ /** Ring-2 stack segment. (static) */ /** Page directory for the task. (static) */ /** EIP before task switch. */ /** EFLAGS before task switch. */ /** EAX before task switch. */ /** ECX before task switch. */ /** EDX before task switch. */ /** EBX before task switch. */ /** ESP before task switch. */ /** EBP before task switch. */ /** ESI before task switch. */ /** EDI before task switch. */ /** ES before task switch. */ /** CS before task switch. */ /** SS before task switch. */ /** DS before task switch. */ /** FS before task switch. */ /** GS before task switch. */ /** LDTR before task switch. */ /** Offset relative to the TSS of the start of the I/O Bitmap * and the end of the interrupt redirection bitmap. */ /** 32 bytes for the virtual interrupt redirection bitmap. (VME) */ /** Pointer to task segment. */ /** Pointer to const task segment. */ /** Ring-0 stack pointer. (static) */ /** Ring-1 stack pointer. (static) */ /** Ring-2 stack pointer. (static) */ /** Offset relative to the TSS of the start of the I/O Bitmap * and the end of the interrupt redirection bitmap. */ /** 32 bytes for the virtual interrupt redirection bitmap. (VME) */ /** Pointer to a 64-bit task segment. */ /** Pointer to a const 64-bit task segment. */ * The shift used to convert a selector from and to index an index (C). * The mask used to mask off the table indicator and RPL of an selector. * The mask used to mask off the RPL of an selector. * This is suitable for checking for NULL selectors. * The bit indicating that a selector is in the LDT and not in the GDT. * The bit mask for getting the RPL of a selector. * The mask covering both RPL and LDT. * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit /** \#DE - Divide error. */ /** \#DB - Debug event (single step, DRx, ..) */ /** NMI - Non-Maskable Interrupt */ /** \#BP - Breakpoint (INT3). */ /** \#OF - Overflow (INTO). */ /** \#BR - Bound range exceeded (BOUND). */ /** \#UD - Undefined opcode. */ /** \#NM - Device not available (math coprocessor device). */ /** \#DF - Double fault. */ /** ??? - Coprocessor segment overrun (obsolete). */ /** \#TS - Taskswitch (TSS). */ /** \#NP - Segment no present. */ /** \#SS - Stack segment fault. */ /** \#GP - General protection fault. */ /** \#PF - Page fault. */ /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */ /** \#MF - Math fault (FPU). */ /** \#AC - Alignment check. */ /** \#MC - Machine check. */ /** \#XF - SIMD Floating-Pointer Exception. */ /** \#VE - Virtualzation Exception. */ /** \#SX - Security Exception. */ /** Pointer to a x86 exception code. */ /** Pointer to a const x86 exception code. */ /** The maximum exception value. */ /** @name Trap Error Codes /** External indicator. */ /** Descriptor table indicator - If set LDT, if clear GDT. */ /** Mask for getting the selector. */ /** Shift for getting the selector table index (C type index). */ /** @name \#PF Trap Error Codes /** Bit 0 - P - Not present (clear) or page level protection (set) fault. */ /** Bit 1 - R/W - Read (clear) or write (set) access. */ /** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */ /** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */ /** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */ /** Size of the descriptor table. */ /** Address of the descriptor table. */ /** Size of the descriptor table. */ /** Address of the descriptor table. */ /** @name General register indexes /** @name X86_SREG_XXX - Segment register indexes. /** Segment register count. */ /** @name X86_OP_XXX - Prefixes