x86.h revision 1f291c5acd315376ba984563c3165bc0edb53f49
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync * IPRT - X86 and AMD64 Structures and Definitions.
af062818b47340eef15700d2f0211576ba3506eevboxsync * @note x86.mac is generated from this file by running 'kmk incs' in the root.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Copyright (C) 2006-2012 Oracle Corporation
af062818b47340eef15700d2f0211576ba3506eevboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
af062818b47340eef15700d2f0211576ba3506eevboxsync * available from http://www.virtualbox.org. This file is free software;
af062818b47340eef15700d2f0211576ba3506eevboxsync * you can redistribute it and/or modify it under the terms of the GNU
af062818b47340eef15700d2f0211576ba3506eevboxsync * General Public License (GPL) as published by the Free Software
af062818b47340eef15700d2f0211576ba3506eevboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
af062818b47340eef15700d2f0211576ba3506eevboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
af062818b47340eef15700d2f0211576ba3506eevboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
af062818b47340eef15700d2f0211576ba3506eevboxsync * The contents of this file may alternatively be used under the terms
af062818b47340eef15700d2f0211576ba3506eevboxsync * of the Common Development and Distribution License Version 1.0
af062818b47340eef15700d2f0211576ba3506eevboxsync * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
af062818b47340eef15700d2f0211576ba3506eevboxsync * VirtualBox OSE distribution, in which case the provisions of the
af062818b47340eef15700d2f0211576ba3506eevboxsync * CDDL are applicable instead of those of the GPL.
af062818b47340eef15700d2f0211576ba3506eevboxsync * You may elect to license modified versions of this file under the
af062818b47340eef15700d2f0211576ba3506eevboxsync * terms and conditions of either the GPL or the CDDL or both.
af062818b47340eef15700d2f0211576ba3506eevboxsync/* Workaround for Solaris sys/regset.h defining CS, DS */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @defgroup grp_rt_x86 x86 Types and Definitions
af062818b47340eef15700d2f0211576ba3506eevboxsync * @ingroup grp_rt
af062818b47340eef15700d2f0211576ba3506eevboxsync * EFLAGS Bits.
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 0 - CF - Carry flag - Status flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 1 - 1 - Reserved flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 2 - PF - Parity flag - Status flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 3 - 0 - Reserved flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 5 - 0 - Reserved flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 6 - ZF - Zero flag - Status flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 7 - SF - Signed flag - Status flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 8 - TF - Trap flag - System flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 9 - IF - Interrupt flag - System flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 10 - DF - Direction flag - Control flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 11 - OF - Overflow flag - Status flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 14 - NT - Nested task flag - System flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 15 - 0 - Reserved flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 16 - RF - Resume flag - System flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 17 - VM - Virtual 8086 mode - System flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 22-31 - 0 - Reserved flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to EFLAGS bits. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to const EFLAGS bits. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#endif /* !VBOX_FOR_DTRACE_LIB */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** The plain unsigned view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** The bitfield view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** The 8-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** The 16-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** The 32-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** The 32-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to EFLAGS. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to const EFLAGS. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * RFLAGS (32 upper bits are reserved).
af062818b47340eef15700d2f0211576ba3506eevboxsync /** The plain unsigned view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** The bitfield view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** The 8-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** The 16-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** The 32-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** The 64-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** The 64-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to RFLAGS. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to const RFLAGS. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name EFLAGS
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 0 - CF - Carry flag - Status flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 1 - Reserved, reads as 1. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 2 - PF - Parity flag - Status flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 6 - ZF - Zero flag - Status flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 7 - SF - Signed flag - Status flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 8 - TF - Trap flag - System flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 9 - IF - Interrupt flag - System flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 10 - DF - Direction flag - Control flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 11 - OF - Overflow flag - Status flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 14 - NT - Nested task flag - System flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 16 - RF - Resume flag - System flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 17 - VM - Virtual 8086 mode - System flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** IOPL shift. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The the IOPL level from the flags. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits restored by popf */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_EFL_POPF_BITS (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** CPUID Feature information - ECX.
af062818b47340eef15700d2f0211576ba3506eevboxsync * CPUID query with EAX=1.
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 0 - SSE3 - Supports SSE3 or not. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 1 - PCLMULQDQ. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 2 - DS Area 64-bit layout. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 5 - VMX - Virtual Machine Technology. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 6 - SMX: Safer Mode Extensions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 7 - EST - Enh. SpeedStep Tech. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 8 - TM2 - Terminal Monitor 2. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 10 - CNTX-ID - L1 Context ID. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 11 - Reserved. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 12 - FMA. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 13 - CX16 - CMPXCHG16B. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 16 - Reserved. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 17 - PCID - Process-context identifiers. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 18 - Direct Cache Access. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 21 - x2APIC. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 22 - MOVBE - Supports MOVBE. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 23 - POPCNT - Supports POPCNT. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 24 - TSC-Deadline. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 25 - AES. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 26 - XSAVE - Supports XSAVE. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 28 - AVX - Supports AVX instruction extensions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 29 - 30 - Reserved */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 31 - Hypervisor present (we're a guest). */
af062818b47340eef15700d2f0211576ba3506eevboxsync#else /* VBOX_FOR_DTRACE_LIB */
af062818b47340eef15700d2f0211576ba3506eevboxsync#endif /* VBOX_FOR_DTRACE_LIB */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to CPUID Feature Information - ECX. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to const CPUID Feature Information - ECX. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** CPUID Feature Information - EDX.
af062818b47340eef15700d2f0211576ba3506eevboxsync * CPUID query with EAX=1.
af062818b47340eef15700d2f0211576ba3506eevboxsync#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 0 - FPU - x87 FPU on Chip. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 2 - DE - Debugging extensions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 3 - PSE - Page Size Extension. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 4 - TSC - Time Stamp Counter. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 6 - PAE - Physical Address Extension. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 7 - MCE - Machine Check Exception. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 8 - CX8 - CMPXCHG8B instruction. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 9 - APIC - APIC On-Chip. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 10 - Reserved. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 12 - MTRR - Memory Type Range Registers. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 13 - PGE - PTE Global Bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 14 - MCA - Machine Check Architecture. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 15 - CMOV - Conditional Move Instructions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 16 - PAT - Page Attribute Table. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 18 - PSN - Processor Serial Number. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 19 - CLFSH - CLFLUSH Instruction. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 20 - Reserved. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 21 - DS - Debug Store. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 23 - MMX - Intel MMX 'Technology'. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 25 - SSE - SSE Support. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 26 - SSE2 - SSE2 Support. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 27 - SS - Self Snoop. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 28 - HTT - Hyper-Threading Technology. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 29 - TM - Thermal Monitor. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 30 - Reserved - . */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit 31 - PBE - Pending Break Enabled. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#else /* VBOX_FOR_DTRACE_LIB */
af062818b47340eef15700d2f0211576ba3506eevboxsync#endif /* VBOX_FOR_DTRACE_LIB */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to CPUID Feature Information - EDX. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to const CPUID Feature Information - EDX. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name CPUID Vendor information.
af062818b47340eef15700d2f0211576ba3506eevboxsync * CPUID query with EAX=0.
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name CPUID Feature information.
af062818b47340eef15700d2f0211576ba3506eevboxsync * CPUID query with EAX=1.
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 5 - VMX - Virtual Machine Technology. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 6 - SMX - Safer Mode Extensions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 12 - FMA. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 13 - CX16 - CMPXCHG16B. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 17 - PCID - Process-context identifiers. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 18 - DCA - Direct Cache Access. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 21 - x2APIC support. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 22 - MOVBE instruction. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 23 - POPCNT instruction. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bir 24 - TSC-Deadline. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 25 - AES instructions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 26 - XSAVE instruction. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 27 - OSXSAVE instruction. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 28 - AVX. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 31 - Hypervisor Present (software only). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 0 - FPU - x87 FPU on Chip. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 2 - DE - Debugging extensions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 3 - PSE - Page Size Extension. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 4 - TSC - Time Stamp Counter. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 6 - PAE - Physical Address Extension. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 7 - MCE - Machine Check Exception. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 8 - CX8 - CMPXCHG8B instruction. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 9 - APIC - APIC On-Chip. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 12 - MTRR - Memory Type Range Registers. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 13 - PGE - PTE Global Bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 14 - MCA - Machine Check Architecture. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 15 - CMOV - Conditional Move Instructions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 16 - PAT - Page Attribute Table. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 18 - PSN - Processor Serial Number. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 19 - CLFSH - CLFLUSH Instruction. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 21 - DS - Debug Store. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 23 - MMX - Intel MMX Technology. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 25 - SSE - SSE Support. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 26 - SSE2 - SSE2 Support. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 27 - SS - Self Snoop. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 28 - HTT - Hyper-Threading Technology. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 29 - TM - Therm. Monitor. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 31 - PBE - Pending Break Enabled. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name CPUID mwait/monitor information.
af062818b47340eef15700d2f0211576ba3506eevboxsync * CPUID query with EAX=5.
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name CPUID Extended Feature information.
af062818b47340eef15700d2f0211576ba3506eevboxsync * CPUID query with EAX=0x80000001.
af062818b47340eef15700d2f0211576ba3506eevboxsync/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** EDX Bit 11 - SYSCALL/SYSRET. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** EDX Bit 20 - No-Execute/Execute-Disable. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** EDX Bit 26 - 1 GB large page. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** EDX Bit 27 - RDTSCP. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name CPUID AMD Feature information.
af062818b47340eef15700d2f0211576ba3506eevboxsync * CPUID query with EAX=0x80000001.
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 0 - FPU - x87 FPU on Chip. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 2 - DE - Debugging extensions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 3 - PSE - Page Size Extension. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 4 - TSC - Time Stamp Counter. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 6 - PAE - Physical Address Extension. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 7 - MCE - Machine Check Exception. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 8 - CX8 - CMPXCHG8B instruction. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 9 - APIC - APIC On-Chip. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 12 - MTRR - Memory Type Range Registers. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 13 - PGE - PTE Global Bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 14 - MCA - Machine Check Architecture. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 15 - CMOV - Conditional Move Instructions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 16 - PAT - Page Attribute Table. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 23 - MMX - Intel MMX Technology. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 31 - 3DNOW - AMD 3DNow. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 1 - CMPL - Core multi-processing legacy mode. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 2 - SVM - AMD VM extensions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 9 - OSVW - AMD OS visible workaround. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 10 - IBS - Instruct based sampling. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 11 - SSE5 - SSE5 instruction support. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 13 - WDT - AMD Watchdog timer support. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name CPUID AMD Feature information.
af062818b47340eef15700d2f0211576ba3506eevboxsync * CPUID query with EAX=0x80000007.
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 0 - TS - Temperature Sensor. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 1 - FID - Frequency ID Control. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 2 - VID - Voltage ID Control. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 3 - TTP - THERMTRIP. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 4 - TM - Hardware Thermal Control. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 5 - STC - Software Thermal Control. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 6 - MC - 100 Mhz Multiplier Control. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 7 - HWPSTATE - Hardware P-State Control. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 8 - TSCINVAR - TSC Invariant. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name CR0
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 0 - PE - Protection Enabled */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 1 - MP - Monitor Coprocessor */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 2 - EM - Emulation. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 3 - TS - Task Switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 5 - NE - Numeric error. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 16 - WP - Write Protect. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 18 - AM - Alignment Mask. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 29 - NW - Not Write-though. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 30 - WP - Cache Disable. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 31 - PG - Paging. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name CR3
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 3 - PWT - Page-level Writes Transparent. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 4 - PCD - Page-level Cache Disable. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 12-31 - - Page directory page number. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 5-31 - - PAE Page directory page number. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 12-51 - - AMD64 Page directory page number. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name CR4
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 2 - TSD - Time Stamp Disable. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 3 - DE - Debugging Extensions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 4 - PSE - Page Size Extension. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 5 - PAE - Physical Address Extension. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 6 - MCE - Machine-Check Enable. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 7 - PGE - Page Global Enable. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 13 - VMXE - VMX mode is enabled. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
af062818b47340eef15700d2f0211576ba3506eevboxsync * extended states. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name DR6
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 0 - B0 - Breakpoint 0 condition detected. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 1 - B1 - Breakpoint 1 condition detected. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 2 - B2 - Breakpoint 2 condition detected. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 3 - B3 - Breakpoint 3 condition detected. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 14 - BS - Single step */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 15 - BT - Task switch. (TSS T bit.) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Value of DR6 after powerup/reset. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name DR7
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
af062818b47340eef15700d2f0211576ba3506eevboxsync * any DR register is accessed. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits which must be 1s. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Calcs the L bit of Nth breakpoint.
af062818b47340eef15700d2f0211576ba3506eevboxsync * @param iBp The breakpoint number [0..3].
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Calcs the G bit of Nth breakpoint.
af062818b47340eef15700d2f0211576ba3506eevboxsync * @param iBp The breakpoint number [0..3].
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name Read/Write values.
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Break on instruction fetch only. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Break on write only. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Break on I/O read/write. This is only defined if CR4.DE is set. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Break on read or write (but not instruction fetches). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Shifts a X86_DR7_RW_* value to its right place.
af062818b47340eef15700d2f0211576ba3506eevboxsync * @param iBp The breakpoint number [0..3].
af062818b47340eef15700d2f0211576ba3506eevboxsync * @param fRw One of the X86_DR7_RW_* value.
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name Length values.
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_DR7_LEN_QWORD 2U /**< AMD64 long mode only. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Shifts a X86_DR7_LEN_* value to its right place.
af062818b47340eef15700d2f0211576ba3506eevboxsync * @param iBp The breakpoint number [0..3].
af062818b47340eef15700d2f0211576ba3506eevboxsync * @param cb One of the X86_DR7_LEN_* values.
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Fetch the breakpoint length bits from the DR7 value.
af062818b47340eef15700d2f0211576ba3506eevboxsync * @param uDR7 DR7 value
af062818b47340eef15700d2f0211576ba3506eevboxsync * @param iBp The breakpoint number [0..3].
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Mask used to check if any breakpoints are enabled. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7))
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Mask used to check if any io breakpoints are set. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) | X86_DR7_RW(1, X86_DR7_RW_IO) | X86_DR7_RW(2, X86_DR7_RW_IO) | X86_DR7_RW(3, X86_DR7_RW_IO))
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Value of DR7 after powerup/reset. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name Machine Specific Registers
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Time Stamp Counter. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** CPU Feature control. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** BIOS update trigger (microcode update). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** BIOS update signature (microcode). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** General performance counter no. 0. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** General performance counter no. 1. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** General performance counter no. 2. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** General performance counter no. 3. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Nehalem power control. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Get FSB clock status (Intel-specific). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** MTRR Capabilities. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
af062818b47340eef15700d2f0211576ba3506eevboxsync * R0 SS == CS + 8
af062818b47340eef15700d2f0211576ba3506eevboxsync * R3 CS == CS + 16
af062818b47340eef15700d2f0211576ba3506eevboxsync * R3 SS == CS + 24
af062818b47340eef15700d2f0211576ba3506eevboxsync/** SYSENTER_ESP - the R0 ESP. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** SYSENTER_EIP - the R0 EIP. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Machine Check Global Capabilities Register. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Machine Check Global Status Register. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Machine Check Global Control Register. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Trace/Profile Resource Control (R/W) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Page Attribute Table. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Performance counter MSRs. (Intel only) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Enable misc. processor features (R/W). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Enable fast-strings feature (for REP MOVS and REP STORS). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Automatic Thermal Control Circuit Enable (R/W). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Performance Monitoring Available (R). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Branch Trace Storage Unavailable (R/O). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Enhanced Intel SpeedStep Technology Enable (R/W). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** If MONITOR/MWAIT is supported (R/W). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Limit CPUID Maxval to 3 leafs (R/W). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** When set to 1, xTPR messages are disabled (R/W). */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Fixed range MTRRs.
af062818b47340eef15700d2f0211576ba3506eevboxsync/** MTRR Default Range. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Basic VMX information. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Allowed settings for pin-based VM execution controls */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Allowed settings for proc-based VM execution controls */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Allowed settings for the VMX exit controls. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Allowed settings for the VMX entry controls. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Misc VMX info. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Fixed cleared bits in CR0. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Fixed set bits in CR0. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Fixed cleared bits in CR4. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Fixed set bits in CR4. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Information for enumerating fields in the VMCS. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Allowed settings for the VM-functions controls. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Allowed settings for secondary proc-based VM execution controls */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** EPT capabilities. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** DS Save Area (R/W). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** X2APIC MSR ranges. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** K6 EFER - Extended Feature Enable Register. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @todo document EFER */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 8 - LME - Long mode enabled. (R/W) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 10 - LMA - Long mode active. (R) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** K6 STAR - SYSCALL/RET targets. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Shift value for getting the SYSRET CS and SS value. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Shift value for getting the SYSCALL CS and SS value. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Selector mask for use after shifting. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The mask which give the SYSCALL EIP. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** K6 WHCR - Write Handling Control Register. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** K6 UWCCR - UC/WC Cacheability Control Register. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** K6 PSOR - Processor State Observability Register. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** K6 PFIR - Page Flush/Invalidate Register. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Performance counter MSRs. (AMD only) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** K8 LSTAR - Long mode SYSCALL target (RIP). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** K8 FS.base - The 64-bit base FS register. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** K8 GS.base - The 64-bit base GS register. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** K8 KernelGSbase - Used with SWAPGS. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** K8 TSC_AUX - Used with RDTSCP. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
af062818b47340eef15700d2f0211576ba3506eevboxsync * host state during world switch.
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name Page Table / Directory / Directory Pointers / L4.
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Page table/directory entry as an unsigned integer. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page table/directory table entry as an unsigned integer. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to an const page table/directory table entry as an unsigned integer. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Number of entries in a 32-bit PT/PD. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Number of entries in a PAE PT/PD. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Number of entries in a PAE PDPT. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Number of entries in an AMD64 PDPT.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The size of a 4KB page. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The page shift of a 4KB page. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The 4KB page offset mask. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The 4KB page base mask for virtual addresses. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The 4KB page base mask for virtual addresses - 32bit version. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The size of a 2MB page. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The page shift of a 2MB page. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The 2MB page offset mask. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The 2MB page base mask for virtual addresses. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The 2MB page base mask for virtual addresses - 32bit version. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The size of a 4MB page. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The page shift of a 4MB page. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The 4MB page offset mask. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The 4MB page base mask for virtual addresses. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The 4MB page base mask for virtual addresses - 32bit version. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name Page Table Entry
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 0 - P - Present bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 3 - PWT - Page level write thru bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 4 - PCD - Page level cache disable bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 5 - A - Access bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 6 - D - Dirty bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 8 - G - Global flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 0 - P - Present bit mask. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 3 - PWT - Page level write thru bit mask. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 4 - PCD - Page level cache disable bit mask. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 5 - A - Access bit mask. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 6 - D - Dirty bit mask. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 8 - G - Global bit mask. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 9-11 - - Available for use to system software. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 12-31 - - Physical Page number of the next level. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 12-51 - - PAE - Physical Page number of the next level. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 63 - NX - PAE/LM - No execution flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 63-52 - - PAE - MBZ bits when no NX. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** No bits - - LM - MBZ bits when NX is active. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 63 - - LM - MBZ bits when no NX. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
af062818b47340eef15700d2f0211576ba3506eevboxsync * Page table entry.
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86PTEBITS
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Flags whether(=1) or not the page is present. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Read(=0) / Write(=1) flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** User(=1) / Supervisor (=0) flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Write Thru flag. If PAT enabled, bit 0 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Accessed flag.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Indicates that the page have been read or written to. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Dirty flag.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Indicates that the page has been written to. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Reserved / If PAT enabled, bit 2 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Global flag. (Ignored in all but final level.) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Available for use to system software. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Physical Page number of the next level. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const page table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * Page table entry.
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef union X86PTE
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Unsigned integer view */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit field view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 32-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 16-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 8-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const page table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * PAE page table entry.
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Flags whether(=1) or not the page is present. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Read(=0) / Write(=1) flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** User(=1) / Supervisor(=0) flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Write Thru flag. If PAT enabled, bit 0 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Accessed flag.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Indicates that the page have been read or written to. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Dirty flag.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Indicates that the page has been written to. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Reserved / If PAT enabled, bit 2 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Global flag. (Ignored in all but final level.) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Available for use to system software. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Physical Page number of the next level - Low Part. Don't use this. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Physical Page number of the next level - High Part. Don't use this. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** MBZ bits */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** No Execute flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * PAE Page table entry.
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Unsigned integer view */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bit field view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 32-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 16-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 8-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a PAE page table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const PAE page table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * Page table.
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86PT
af062818b47340eef15700d2f0211576ba3506eevboxsync /** PTE Array. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page table. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const page table. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The page shift to get the PT index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The PT index mask (apply to a shifted page address). */
af062818b47340eef15700d2f0211576ba3506eevboxsync * Page directory.
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86PTPAE
af062818b47340eef15700d2f0211576ba3506eevboxsync /** PTE Array. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page table. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const page table. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The page shift to get the PA PTE index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The PAE PT index mask (apply to a shifted page address). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name 4KB Page Directory Entry
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 0 - P - Present bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 3 - PWT - Page level write thru bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 4 - PCD - Page level cache disable bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 5 - A - Access bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 7 - PS - Page size attribute.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Clear mean 4KB pages, set means large pages (2/4MB). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 9-11 - - Available for use to system software. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 12-31 - - Physical Page number of the next level. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 12-51 - - PAE - Physical Page number of the next level. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 63 - NX - PAE/LM - No execution flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 7 - - LM - MBZ bits when NX is active. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 63, 7 - - LM - MBZ bits when no NX. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
af062818b47340eef15700d2f0211576ba3506eevboxsync * Page directory entry.
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86PDEBITS
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Flags whether(=1) or not the page is present. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Read(=0) / Write(=1) flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** User(=1) / Supervisor (=0) flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Write Thru flag. If PAT enabled, bit 0 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Accessed flag.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Indicates that the page has been read or written to. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Reserved / Ignored (dirty bit). */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Size bit if PSE is enabled - in any event it's 0. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Reserved / Ignored (global bit). */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Available for use to system software. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Physical Page number of the next level. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page directory entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const page directory entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * PAE page directory entry.
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Flags whether(=1) or not the page is present. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Read(=0) / Write(=1) flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** User(=1) / Supervisor (=0) flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Write Thru flag. If PAT enabled, bit 0 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Accessed flag.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Indicates that the page has been read or written to. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Reserved / Ignored (dirty bit). */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Size bit if PSE is enabled - in any event it's 0. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Reserved / Ignored (global bit). / */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Available for use to system software. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Physical Page number of the next level - Low Part. Don't use! */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Physical Page number of the next level - High Part. Don't use! */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** MBZ bits */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** No Execute flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page directory entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const page directory entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name 2/4MB Page Directory Entry
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 0 - P - Present bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 3 - PWT - Page level write thru bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 4 - PCD - Page level cache disable bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 5 - A - Access bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 6 - D - Dirty bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 8 - G - Global flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 9-11 - AVL - Available for use to system software. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 22-31 - - Physical Page number. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The number of bits to the high part of the page number. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 21-51 - - PAE/LM - Physical Page number.
af062818b47340eef15700d2f0211576ba3506eevboxsync * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 63 - NX - PAE/LM - No execution flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 20-13 - - LM - MBZ bits when NX is active. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
af062818b47340eef15700d2f0211576ba3506eevboxsync * 4MB page directory entry.
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86PDE4MBITS
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Flags whether(=1) or not the page is present. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Read(=0) / Write(=1) flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** User(=1) / Supervisor (=0) flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Write Thru flag. If PAT enabled, bit 0 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Accessed flag.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Indicates that the page have been read or written to. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Dirty flag.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Indicates that the page has been written to. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Page size flag - always 1 for 4MB entries. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Global flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Available for use to system software. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Reserved / If PAT enabled, bit 2 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Bits 32-39 of the page number on AMD64.
af062818b47340eef15700d2f0211576ba3506eevboxsync * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Reserved. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Physical Page number of the page. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const page table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * 2MB PAE page directory entry.
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Flags whether(=1) or not the page is present. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Read(=0) / Write(=1) flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** User(=1) / Supervisor(=0) flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Write Thru flag. If PAT enabled, bit 0 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Accessed flag.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Indicates that the page have been read or written to. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Dirty flag.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Indicates that the page has been written to. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Page size flag - always 1 for 2MB entries. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Global flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Available for use to system software. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Reserved / If PAT enabled, bit 2 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Reserved. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Physical Page number of the next level - Low part. Don't use! */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Physical Page number of the next level - High part. Don't use! */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** MBZ bits */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** No Execute flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a 2MB PAE page table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a 2MB PAE page table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * Page directory entry.
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef union X86PDE
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Normal view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 4MB view (big). */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 8 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 16 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 32 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page directory entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const page directory entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * PAE page directory entry.
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Normal view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 2MB page view (big). */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 8 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 16 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 32 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page directory entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const page directory entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * Page directory.
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86PD
af062818b47340eef15700d2f0211576ba3506eevboxsync /** PDE Array. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page directory. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const page directory. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The page shift to get the PD index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The PD index mask (apply to a shifted page address). */
af062818b47340eef15700d2f0211576ba3506eevboxsync * PAE page directory.
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86PDPAE
af062818b47340eef15700d2f0211576ba3506eevboxsync /** PDE Array. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a PAE page directory. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const PAE page directory. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The page shift to get the PAE PD index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The PAE PD index mask (apply to a shifted page address). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name Page Directory Pointer Table Entry (PAE)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 0 - P - Present bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 3 - PWT - Page level write thru bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 4 - PCD - Page level cache disable bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 5 - A - Access bit. Long Mode only. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 7 - PS - Page size (1GB). Long Mode only. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 9-11 - - Available for use to system software. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 12-51 - - PAE - Physical Page number of the next level. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
af062818b47340eef15700d2f0211576ba3506eevboxsync * Page directory pointer table entry.
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86PDPEBITS
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Flags whether(=1) or not the page is present. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Chunk of reserved bits. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Write Thru flag. If PAT enabled, bit 0 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Chunk of reserved bits. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Available for use to system software. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Physical Page number of the next level - Low Part. Don't use! */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Physical Page number of the next level - High Part. Don't use! */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** MBZ bits */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page directory pointer table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const page directory pointer table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * Page directory pointer table entry. AMD64 version
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Flags whether(=1) or not the page is present. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Read(=0) / Write(=1) flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** User(=1) / Supervisor (=0) flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Write Thru flag. If PAT enabled, bit 0 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Accessed flag.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Indicates that the page have been read or written to. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Chunk of reserved bits. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Available for use to system software. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Physical Page number of the next level - Low Part. Don't use! */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Physical Page number of the next level - High Part. Don't use! */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** MBZ bits */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** No Execute flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page directory pointer table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const page directory pointer table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * Page directory pointer table entry.
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef union X86PDPE
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Normal view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** AMD64 view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 8 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 16 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 32 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page directory pointer table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const page directory pointer table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * Page directory pointer table.
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86PDPT
af062818b47340eef15700d2f0211576ba3506eevboxsync /** PDE Array. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page directory pointer table. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const page directory pointer table. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The page shift to get the PDPT index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name Page Map Level-4 Entry (Long Mode PAE)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 0 - P - Present bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 3 - PWT - Page level write thru bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 4 - PCD - Page level cache disable bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 5 - A - Access bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 9-11 - - Available for use to system software. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 12-51 - - PAE - Physical Page number of the next level. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 8, 7 - - MBZ bits when NX is active. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 63, 7 - - MBZ bits when no NX. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 63 - NX - PAE - No execution flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * Page Map Level-4 Entry
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86PML4EBITS
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Flags whether(=1) or not the page is present. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Read(=0) / Write(=1) flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** User(=1) / Supervisor (=0) flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Write Thru flag. If PAT enabled, bit 0 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Accessed flag.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Indicates that the page have been read or written to. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Chunk of reserved bits. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Available for use to system software. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Physical Page number of the next level - Low Part. Don't use! */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Physical Page number of the next level - High Part. Don't use! */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** MBZ bits */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** No Execute flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page map level-4 entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const page map level-4 entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * Page Map Level-4 Entry.
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef union X86PML4E
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Normal view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 8 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 16 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 32 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page map level-4 entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const page map level-4 entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * Page Map Level-4.
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86PML4
af062818b47340eef15700d2f0211576ba3506eevboxsync /** PDE Array. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a page map level-4. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const page map level-4. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The page shift to get the PML4 index. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The PML4 index mask (apply to a shifted page address). */
af062818b47340eef15700d2f0211576ba3506eevboxsync * 80-bit MMX/FPU register type.
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86FPUMMX
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a 80-bit MMX/FPU register type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const 80-bit MMX/FPU register type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
af062818b47340eef15700d2f0211576ba3506eevboxsync * @todo verify this...
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86FPUSTATE
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x00 - Control word. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x02 - Alignment word */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x04 - Status word. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x06 - Alignment word */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x08 - Tag word */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x0a - Alignment word */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x0c - Instruction pointer. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x10 - Code selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x12 - Opcode. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x14 - FOO. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x18 - FOS. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x1c */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** MMX view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** FPU view - todo. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Extended precision floating point view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Extended precision floating point view v2. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 8-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 16-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 32-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 64-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 128-bit view. (yeah, very helpful) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a FPU state. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const FPU state. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86FXSTATE
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x00 - Control word. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x02 - Status word. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x04 - Tag word. (The upper byte is always zero.) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x06 - Opcode. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x08 - Instruction pointer. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x0c - Code selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x10 - Data pointer. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x14 - Data segment */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x16 */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x18 */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x1c */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0x20 */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** MMX view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** FPU view - todo. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Extended precision floating point view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Extended precision floating point view v2 */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 8-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 16-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 32-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 64-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 128-bit view. (yeah, very helpful) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* - offset 160 - */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** XMM Register view *. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 8-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 16-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 32-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 64-bit view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 128-bit view. (yeah, very helpful) */
af062818b47340eef15700d2f0211576ba3506eevboxsync } aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* - offset 416 - */
af062818b47340eef15700d2f0211576ba3506eevboxsync uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a FPU Extended state. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const FPU Extended state. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name FPU status word flags.
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Exception Flag: Invalid operation. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Exception Flag: Denormalized operand. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Exception Flag: Zero divide. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Exception Flag: Overflow. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Exception Flag: Underflow. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Exception Flag: Precision. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Stack fault. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Error summary status. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Mask of exceptions flags, excluding the summary bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Mask of exceptions flags, including the summary bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Condition code 0. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Condition code 1. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Condition code 2. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Top of the stack mask. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** TOP shift value. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Mask for getting TOP value after shifting it right. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Get the TOP value. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Condition code 3. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Mask of exceptions flags, including the summary bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** FPU busy. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name FPU control word flags.
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Exception Mask: Invalid operation. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Exception Mask: Denormalized operand. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Exception Mask: Zero divide. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Exception Mask: Overflow. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Exception Mask: Underflow. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Exception Mask: Precision. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Mask all exceptions, the value typically loaded (by for instance fninit).
af062818b47340eef15700d2f0211576ba3506eevboxsync * @remarks This includes reserved bit 6. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Precision control mask. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Precision control: 24-bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Precision control: Reserved. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Precision control: 53-bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Precision control: 64-bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Rounding control mask. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Rounding control: To nearest. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Rounding control: Down. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Rounding control: Up. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Rounding control: Towards zero. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits which should be zero, apparently. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name Selector Descriptor
af062818b47340eef15700d2f0211576ba3506eevboxsync * Descriptor attributes (as seen by VT-x).
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 00 - Segment Type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 04 - Descriptor Type. System(=0) or code/data selector */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 05 - Descriptor Privelege level. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 07 - Flags selector present(=1) or not. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 08 - Segment limit 16-19. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0c - Available for system software. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0e - This flags meaning depends on the segment type. Try make sense out
af062818b47340eef15700d2f0211576ba3506eevboxsync * of the intel manual yourself. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 0f - Granularity of the limit. If set 4KB granularity is used, if
af062818b47340eef15700d2f0211576ba3506eevboxsync * clear byte. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#endif /* !VBOX_FOR_DTRACE_LIB */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name X86DESCATTR masks
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Normal view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to descriptor attributes. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to const descriptor attributes. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * Generic descriptor table entry
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 00 - Limit - Low word. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 10 - Base address - lowe word.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Don't try set this to 24 because MSC is doing stupid things then. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 20 - Base address - first 8 bits of high word. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 28 - Segment Type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 2c - Descriptor Type. System(=0) or code/data selector */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 2d - Descriptor Privelege level. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 2f - Flags selector present(=1) or not. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 30 - Segment limit 16-19. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 34 - Available for system software. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 36 - This flags meaning depends on the segment type. Try make sense out
af062818b47340eef15700d2f0211576ba3506eevboxsync * of the intel manual yourself. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 37 - Granularity of the limit. If set 4KB granularity is used, if
af062818b47340eef15700d2f0211576ba3506eevboxsync * clear byte. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 38 - Base address - highest 8 bits. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a generic descriptor entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const generic descriptor entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name Bit offsets of X86DESCGENERIC members.
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86DESCGATE
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 00 - Target code segment offset - Low word.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Ignored if task-gate. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
af062818b47340eef15700d2f0211576ba3506eevboxsync * TSS selector if task-gate. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 20 - Number of parameters for a call-gate.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Ignored if interrupt-, trap- or task-gate. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 24 - Reserved / ignored. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 28 - Segment Type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 2c - Descriptor Type (0 = system). */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 2d - Descriptor Privelege level. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 2f - Flags selector present(=1) or not. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 30 - Target code segment offset - High word.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Ignored if task-gate. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#endif /* VBOX_FOR_DTRACE_LIB */
af062818b47340eef15700d2f0211576ba3506eevboxsync * Descriptor table entry.
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef union X86DESC
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Generic descriptor view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Gate descriptor view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 8 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 16 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 32 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 64 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to descriptor table entry. */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync/** Pointer to const descriptor table entry. */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync/** @def X86DESC_BASE
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync * Return the base address of a descriptor.
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync/** @def X86DESC_LIMIT
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync * Return the limit of a descriptor.
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync/** @def X86DESC_LIMIT_G
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync * Return the limit of a descriptor with the granularity bit taken into account.
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync * @returns Selector limit (uint32_t).
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync * @param a_pDesc Pointer to the descriptor.
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync/** @def X86DESC_GET_HID_ATTR
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync * Get the descriptor attributes for the hidden register.
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
af062818b47340eef15700d2f0211576ba3506eevboxsync ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
af062818b47340eef15700d2f0211576ba3506eevboxsync * 64 bits generic descriptor table entry
af062818b47340eef15700d2f0211576ba3506eevboxsync * Note: most of these bits have no meaning in long mode.
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Limit - Low word - *IGNORED*. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Base address - low word. - *IGNORED*
af062818b47340eef15700d2f0211576ba3506eevboxsync * Don't try set this to 24 because MSC is doing stupid things then. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Base address - first 8 bits of high word. - *IGNORED* */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Segment Type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Descriptor Type. System(=0) or code/data selector */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Descriptor Privelege level. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Flags selector present(=1) or not. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Segment limit 16-19. - *IGNORED* */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Available for system software. - *IGNORED* */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Long mode flag. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** This flags meaning depends on the segment type. Try make sense out
af062818b47340eef15700d2f0211576ba3506eevboxsync * of the intel manual yourself. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Granularity of the limit. If set 4KB granularity is used, if
af062818b47340eef15700d2f0211576ba3506eevboxsync * clear byte. - *IGNORED* */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Base address - highest 8 bits. - *IGNORED* */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Base address - bits 63-32. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a generic descriptor entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const generic descriptor entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * System descriptor table entry (64 bits)
af062818b47340eef15700d2f0211576ba3506eevboxsync * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Limit - Low word. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Base address - lowe word.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Don't try set this to 24 because MSC is doing stupid things then. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Base address - first 8 bits of high word. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Segment Type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Descriptor Type. System(=0) or code/data selector */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Descriptor Privelege level. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Flags selector present(=1) or not. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Segment limit 16-19. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Available for system software. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Reserved - 0. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** This flags meaning depends on the segment type. Try make sense out
af062818b47340eef15700d2f0211576ba3506eevboxsync * of the intel manual yourself. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Granularity of the limit. If set 4KB granularity is used, if
af062818b47340eef15700d2f0211576ba3506eevboxsync * clear byte. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Base address - bits 31-24. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Base address - bits 63-32. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a system descriptor entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const system descriptor entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Target code segment offset - Low word. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Target code segment selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Interrupt stack table for interrupt- and trap-gates.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Ignored by call-gates. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Reserved / ignored. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Segment Type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Descriptor Type (0 = system). */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Descriptor Privelege level. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Flags selector present(=1) or not. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Target code segment offset - High word.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Ignored if task-gate. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Target code segment offset - Top dword.
af062818b47340eef15700d2f0211576ba3506eevboxsync * Ignored if task-gate. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Reserved / ignored / must be zero.
af062818b47340eef15700d2f0211576ba3506eevboxsync * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#endif /* VBOX_FOR_DTRACE_LIB */
af062818b47340eef15700d2f0211576ba3506eevboxsync * Descriptor table entry.
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Generic descriptor view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** System descriptor view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Gate descriptor view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 8 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 16 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 32 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 64 bit unsigned integer view. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to descriptor table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to const descriptor table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @def X86DESC64_BASE
af062818b47340eef15700d2f0211576ba3506eevboxsync * Return the base of a 64-bit descriptor.
af062818b47340eef15700d2f0211576ba3506eevboxsync ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name Host system descriptor table entry - Use with care!
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Host system descriptor table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a host system descriptor table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const host system descriptor table entry. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name Selector Descriptor Types.
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name Non-System Selector Types.
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Code(=set)/Data(=clear) bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Memory(=set)/System(=clear) bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Accessed bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Expand down bit (for data selectors only). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Conforming bit (for code selectors only). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Write bit (for data selectors only). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Read bit (for code selectors only). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The bit number of the code segment read bit (relative to u4Type). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Read only selector type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Accessed read only selector type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Read write selector type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Accessed read write selector type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Expand down read only selector type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Accessed expand down read only selector type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Expand down read write selector type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Accessed expand down read write selector type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Execute only selector type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Accessed execute only selector type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Execute and read selector type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Accessed execute and read selector type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Conforming execute only selector type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Accessed Conforming execute only selector type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Conforming execute and write selector type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Accessed Conforming execute and write selector type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name System Selector Types.
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The TSS busy bit mask. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Undefined system selector type. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** 286 TSS selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** LDT selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** 286 TSS selector - Busy. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** 286 Callgate selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Taskgate selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** 286 Interrupt gate selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** 286 Trapgate selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Undefined system selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** 386 TSS selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Undefined system selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** 386 TSS selector - Busy. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** 386 Callgate selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Undefined system selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** 386 Interruptgate selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** 386 Trapgate selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name AMD64 System Selector Types.
af062818b47340eef15700d2f0211576ba3506eevboxsync/** LDT selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** TSS selector - Busy. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** TSS selector - Busy. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Callgate selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Interruptgate selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Trapgate selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name Descriptor Table Entry Flag Masks.
af062818b47340eef15700d2f0211576ba3506eevboxsync * These are for the 2nd 32-bit word of a descriptor.
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 8-11 - TYPE - Descriptor type mask. */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 12 - S - System (=0) or Code/Data (=1). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bits 13-14 - DPL - Descriptor Privilege Level. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 15 - P - Present. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 20 - AVL - Available for system software. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
af062818b47340eef15700d2f0211576ba3506eevboxsync * used, if clear byte. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name Task Segments.
af062818b47340eef15700d2f0211576ba3506eevboxsync * 16-bit Task Segment (TSS).
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86TSS16
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Back link to previous task. (static) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Ring-0 stack pointer. (static) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Ring-0 stack segment. (static) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Ring-1 stack pointer. (static) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Ring-1 stack segment. (static) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Ring-2 stack pointer. (static) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Ring-2 stack segment. (static) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** IP before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** FLAGS before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** AX before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** CX before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** DX before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** BX before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** SP before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** BP before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** SI before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** DI before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** ES before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** CS before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** SS before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** DS before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** LDTR before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a 16-bit task segment. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const 16-bit task segment. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * 32-bit Task Segment (TSS).
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86TSS32
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Back link to previous task. (static) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Ring-0 stack pointer. (static) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Ring-0 stack segment. (static) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Ring-1 stack pointer. (static) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Ring-1 stack segment. (static) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Ring-2 stack pointer. (static) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Ring-2 stack segment. (static) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Page directory for the task. (static) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** EIP before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** EFLAGS before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** EAX before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** ECX before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** EDX before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** EBX before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** ESP before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** EBP before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** ESI before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** EDI before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** ES before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** CS before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** SS before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** DS before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** FS before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** GS before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** LDTR before task switch. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Debug trap flag */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Offset relative to the TSS of the start of the I/O Bitmap
af062818b47340eef15700d2f0211576ba3506eevboxsync * and the end of the interrupt redirection bitmap. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to task segment. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to const task segment. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * 64-bit Task segment.
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86TSS64
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Reserved. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Ring-0 stack pointer. (static) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Ring-1 stack pointer. (static) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Ring-2 stack pointer. (static) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Reserved. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* Reserved. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Offset relative to the TSS of the start of the I/O Bitmap
af062818b47340eef15700d2f0211576ba3506eevboxsync * and the end of the interrupt redirection bitmap. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a 64-bit task segment. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const 64-bit task segment. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name Selectors.
af062818b47340eef15700d2f0211576ba3506eevboxsync * The shift used to convert a selector from and to index an index (C).
af062818b47340eef15700d2f0211576ba3506eevboxsync * The mask used to mask off the table indicator and RPL of an selector.
af062818b47340eef15700d2f0211576ba3506eevboxsync * The mask used to mask off the RPL of an selector.
af062818b47340eef15700d2f0211576ba3506eevboxsync * This is suitable for checking for NULL selectors.
af062818b47340eef15700d2f0211576ba3506eevboxsync * The bit indicating that a selector is in the LDT and not in the GDT.
af062818b47340eef15700d2f0211576ba3506eevboxsync * The bit mask for getting the RPL of a selector.
af062818b47340eef15700d2f0211576ba3506eevboxsync * The mask covering both RPL and LDT.
af062818b47340eef15700d2f0211576ba3506eevboxsync * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#DE - Divide error. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#DB - Debug event (single step, DRx, ..) */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** NMI - Non-Maskable Interrupt */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#BP - Breakpoint (INT3). */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#OF - Overflow (INTO). */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#BR - Bound range exceeded (BOUND). */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#UD - Undefined opcode. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#NM - Device not available (math coprocessor device). */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#DF - Double fault. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** ??? - Coprocessor segment overrun (obsolete). */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#TS - Taskswitch (TSS). */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#NP - Segment no present. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#SS - Stack segment fault. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#GP - General protection fault. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#PF - Page fault. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#MF - Math fault (FPU). */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#AC - Alignment check. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#MC - Machine check. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#XF - SIMD Floating-Pointer Exception. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#VE - Virtualzation Exception. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** \#SX - Security Exception. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a x86 exception code. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a const x86 exception code. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** The maximum exception value. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name Trap Error Codes
af062818b47340eef15700d2f0211576ba3506eevboxsync/** External indicator. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** IDT indicator. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Descriptor table indicator - If set LDT, if clear GDT. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Mask for getting the selector. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Shift for getting the selector table index (C type index). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name \#PF Trap Error Codes
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 1 - R/W - Read (clear) or write (set) access. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86XDTR32
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Size of the descriptor table. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Address of the descriptor table. */
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef struct X86XDTR64
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Size of the descriptor table. */
af062818b47340eef15700d2f0211576ba3506eevboxsync /** Address of the descriptor table. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name ModR/M
af062818b47340eef15700d2f0211576ba3506eevboxsyncAssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
af062818b47340eef15700d2f0211576ba3506eevboxsyncAssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
af062818b47340eef15700d2f0211576ba3506eevboxsyncAssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name SIB
af062818b47340eef15700d2f0211576ba3506eevboxsyncAssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
af062818b47340eef15700d2f0211576ba3506eevboxsyncAssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
af062818b47340eef15700d2f0211576ba3506eevboxsyncAssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name General register indexes
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @name X86_SREG_XXX - Segment register indexes.
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Segment register count. */