asm-amd64-x86.h revision d16f75bad381547b34a1f315da059b782f4c21d3
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun * IPRT - AMD64 and x86 Specific Assembly Functions.
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun * Copyright (C) 2006-2013 Oracle Corporation
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun * This file is part of VirtualBox Open Source Edition (OSE), as
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun * available from http://www.virtualbox.org. This file is free software;
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun * you can redistribute it and/or modify it under the terms of the GNU
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun * General Public License (GPL) as published by the Free Software
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun * Foundation, in version 2 as it comes in the "COPYING" file of the
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun * The contents of this file may alternatively be used under the terms
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun * of the Common Development and Distribution License Version 1.0
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun * VirtualBox OSE distribution, in which case the provisions of the
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun * CDDL are applicable instead of those of the GPL.
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun * You may elect to license modified versions of this file under the
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun * terms and conditions of either the GPL or the CDDL or both.
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun /* Emit the intrinsics at all optimization levels. */
71c10d94d9dcec087859cdb44231ccc02ecaef9dnilgun/** @defgroup grp_rt_asm_amd64_x86 AMD64 and x86 Specific ASM Routines
71c10d94d9dcec087859cdb44231ccc02ecaef9dnilgun * @ingroup grp_rt_asm
71c10d94d9dcec087859cdb44231ccc02ecaef9dnilgun/** @todo find a more proper place for these structures? */
e09595826656839c22c18b47ba1d6b6bae9dba5anilguntypedef struct RTIDTR
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun /** Size of the IDT. */
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun /** Address of the IDT. */
71c10d94d9dcec087859cdb44231ccc02ecaef9dnilgun/** @internal */
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun /** Alignment padding. */
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun /** The IDTR structure. */
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun/** Wrapped RTIDTR for preventing misalignment exceptions. */
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun /** Try make sure this structure has optimal alignment. */
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun /** Aligned structure. */
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun/** Pointer to a an RTIDTR alignment wrapper. */
e09595826656839c22c18b47ba1d6b6bae9dba5anilguntypedef struct RTGDTR
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun /** Size of the GDT. */
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun /** Address of the GDT. */
71c10d94d9dcec087859cdb44231ccc02ecaef9dnilgun/** @internal */
71c10d94d9dcec087859cdb44231ccc02ecaef9dnilgun /** Alignment padding. */
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun /** The GDTR structure. */
71c10d94d9dcec087859cdb44231ccc02ecaef9dnilgun/** Wrapped RTGDTR for preventing misalignment exceptions. */
71c10d94d9dcec087859cdb44231ccc02ecaef9dnilgun /** Try make sure this structure has optimal alignment. */
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun /** Aligned structure. */
71c10d94d9dcec087859cdb44231ccc02ecaef9dnilgun/** Pointer to a an RTGDTR alignment wrapper. */
71c10d94d9dcec087859cdb44231ccc02ecaef9dnilgun * Gets the content of the IDTR CPU register.
71c10d94d9dcec087859cdb44231ccc02ecaef9dnilgun * @param pIdtr Where to store the IDTR contents.
71c10d94d9dcec087859cdb44231ccc02ecaef9dnilgun * Gets the content of the IDTR.LIMIT CPU register.
71c10d94d9dcec087859cdb44231ccc02ecaef9dnilgun * @returns IDTR limit.
71c10d94d9dcec087859cdb44231ccc02ecaef9dnilgun __asm__ __volatile__("sidt %0" : "=m" (TmpIdtr.s.Idtr));
71c10d94d9dcec087859cdb44231ccc02ecaef9dnilgun * Sets the content of the IDTR CPU register.
e09595826656839c22c18b47ba1d6b6bae9dba5anilgun * @param pIdtr Where to load the IDTR contents from
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
return SelCS;
return SelDS;
return SelES;
return SelFS;
return SelGS;
return SelSS;
return SelTR;
return SelLDTR;
done:
return uAttr;
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
return uFlags;
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
RTUINT64U u;
u.u = __rdtsc();
RTUINT64U u;
# ifdef RT_ARCH_AMD64
DECLASM(void) ASMCpuId_Idx_ECX(uint32_t uOperator, uint32_t uIdxECX, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX);
DECLINLINE(void) ASMCpuId_Idx_ECX(uint32_t uOperator, uint32_t uIdxECX, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX)
# ifdef RT_ARCH_AMD64
DECLASM(uint32_t) ASMCpuIdExSlow(uint32_t uOperator, uint32_t uInitEBX, uint32_t uInitECX, uint32_t uInitEDX,
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
#ifdef RT_ARCH_AMD64
bool fRet = false;
return fRet;
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
return uCR0;
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
return uCR2;
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
return uCR3;
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
RTCCUINTREG u;
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
return uCR4;
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
return uCR8;
_enable();
_disable();
# ifdef RT_ARCH_AMD64
_disable();
__asm {
return xFlags;
__asm {
RTUINT64U u;
RTUINT64U u;
u.u = u64Val;
RTUINT64U u;
RTUINT64U u;
u.u = u64Val;
return u32;
return u32;
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
return uDR0;
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
return uDR1;
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
return uDR2;
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
return uDR3;
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
return uDR6;
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
return uDR6;
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
return uDR7;
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
# ifdef RT_ARCH_AMD64
return u8;
return u16;
return u32;
# ifdef RT_ARCH_AMD64
__wbinvd();
_mm_mfence();
_mm_sfence();
_mm_lfence();