asm-amd64-x86.h revision d16f75bad381547b34a1f315da059b782f4c21d3
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * IPRT - AMD64 and x86 Specific Assembly Functions.
c58f1213e628a545081c70e26c6b67a841cff880vboxsync * Copyright (C) 2006-2013 Oracle Corporation
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * available from http://www.virtualbox.org. This file is free software;
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * you can redistribute it and/or modify it under the terms of the GNU
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * General Public License (GPL) as published by the Free Software
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * The contents of this file may alternatively be used under the terms
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * of the Common Development and Distribution License Version 1.0
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * VirtualBox OSE distribution, in which case the provisions of the
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * CDDL are applicable instead of those of the GPL.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * You may elect to license modified versions of this file under the
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * terms and conditions of either the GPL or the CDDL or both.
141a285580775ead77d73bb52a63701a5591dc6dvboxsync#if !defined(RT_ARCH_AMD64) && !defined(RT_ARCH_X86)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync /* Emit the intrinsics at all optimization levels. */
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync/** @defgroup grp_rt_asm_amd64_x86 AMD64 and x86 Specific ASM Routines
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @ingroup grp_rt_asm
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsync/** @todo find a more proper place for these structures? */
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsynctypedef struct RTIDTR
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync /** Size of the IDT. */
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync /** Address of the IDT. */
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsync/** @internal */
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsync /** Alignment padding. */
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsync /** The IDTR structure. */
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsync/** Wrapped RTIDTR for preventing misalignment exceptions. */
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsync /** Try make sure this structure has optimal alignment. */
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsync /** Aligned structure. */
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsyncAssertCompileSize(RTIDTRALIGNED, ARCH_BITS * 2 / 8);
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsync/** Pointer to a an RTIDTR alignment wrapper. */
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsynctypedef struct RTGDTR
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync /** Size of the GDT. */
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync /** Address of the GDT. */
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsync/** @internal */
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsync /** Alignment padding. */
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsync /** The GDTR structure. */
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsync/** Wrapped RTGDTR for preventing misalignment exceptions. */
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsync /** Try make sure this structure has optimal alignment. */
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsync /** Aligned structure. */
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsyncAssertCompileSize(RTGDTRALIGNED, ARCH_BITS * 2 / 8);
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsync/** Pointer to a an RTGDTR alignment wrapper. */
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Gets the content of the IDTR CPU register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pIdtr Where to store the IDTR contents.
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsync * Gets the content of the IDTR.LIMIT CPU register.
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsync * @returns IDTR limit.
52df77333eaa775dd09e7b0c525e726ad75b5effvboxsync __asm__ __volatile__("sidt %0" : "=m" (TmpIdtr.s.Idtr));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Sets the content of the IDTR CPU register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pIdtr Where to load the IDTR contents from
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Gets the content of the GDTR CPU register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pGdtr Where to store the GDTR contents.
615c2f5544718590f05af51eff75bd1bbac4be54vboxsync * Sets the content of the GDTR CPU register.
615c2f5544718590f05af51eff75bd1bbac4be54vboxsync * @param pIdtr Where to load the GDTR contents from
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Get the cs register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns cs.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movw %%cs, %0\n\t" : "=r" (SelCS));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Get the DS register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns DS.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movw %%ds, %0\n\t" : "=r" (SelDS));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Get the ES register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns ES.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movw %%es, %0\n\t" : "=r" (SelES));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Get the FS register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns FS.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movw %%fs, %0\n\t" : "=r" (SelFS));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Get the GS register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns GS.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movw %%gs, %0\n\t" : "=r" (SelGS));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Get the SS register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns SS.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movw %%ss, %0\n\t" : "=r" (SelSS));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Get the TR register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns TR.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("str %w0\n\t" : "=r" (SelTR));
76d3e53889c5a02a3881bd3cfa31509d61cea9d0vboxsync * Get the LDTR register.
76d3e53889c5a02a3881bd3cfa31509d61cea9d0vboxsync * @returns LDTR.
76d3e53889c5a02a3881bd3cfa31509d61cea9d0vboxsync __asm__ __volatile__("sldt %w0\n\t" : "=r" (SelLDTR));
109c0d54dc2438e7887f198daefb7e164c8a9dffvboxsync * Get the access rights for the segment selector.
91b5f2a7d9797385e53af76c22883fa15fd25adfvboxsync * @returns The access rights on success or UINT32_MAX on failure.
109c0d54dc2438e7887f198daefb7e164c8a9dffvboxsync * @param uSel The selector value.
91b5f2a7d9797385e53af76c22883fa15fd25adfvboxsync * @remarks Using UINT32_MAX for failure is chosen because valid access rights
91b5f2a7d9797385e53af76c22883fa15fd25adfvboxsync * always have bits 0:7 as 0 (on both Intel & AMD).
109c0d54dc2438e7887f198daefb7e164c8a9dffvboxsync /* LAR only accesses 16-bit of the source operand, but eax for the
109c0d54dc2438e7887f198daefb7e164c8a9dffvboxsync destination operand is required for getting the full 32-bit access rights. */
109c0d54dc2438e7887f198daefb7e164c8a9dffvboxsync "jz done%=\n\t"
d8818699735c83c36fc9555f85e6d86b610cdc67vboxsync "movl $0xffffffff, %%eax\n\t"
109c0d54dc2438e7887f198daefb7e164c8a9dffvboxsync "done%=:\n\t"
d8818699735c83c36fc9555f85e6d86b610cdc67vboxsync "movl %%eax, %0\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Get the [RE]FLAGS register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns [RE]FLAGS.
9ad3427071ba81a2bbf60f5d9a04eb69c147ea6evboxsync#if RT_INLINE_ASM_EXTERNAL && RT_INLINE_ASM_USES_INTRIN < 15
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "popq %0\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "popl %0\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Set the [RE]FLAGS register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uFlags The new [RE]FLAGS value.
9ad3427071ba81a2bbf60f5d9a04eb69c147ea6evboxsync#if RT_INLINE_ASM_EXTERNAL && RT_INLINE_ASM_USES_INTRIN < 15
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "popfq\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "popfl\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Gets the content of the CPU timestamp counter register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns TSC.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("rdtsc\n\t" : "=a" (u.s.Lo), "=d" (u.s.Hi));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync return u.u;
26c76e19c6ae635af16484e15fa73fe74de5acaavboxsync * Gets the content of the CPU timestamp counter register and the
26c76e19c6ae635af16484e15fa73fe74de5acaavboxsync * assoicated AUX value.
26c76e19c6ae635af16484e15fa73fe74de5acaavboxsync * @returns TSC.
26c76e19c6ae635af16484e15fa73fe74de5acaavboxsync * @param puAux Where to store the AUX value.
26c76e19c6ae635af16484e15fa73fe74de5acaavboxsync#if RT_INLINE_ASM_EXTERNAL && RT_INLINE_ASM_USES_INTRIN < 15
26c76e19c6ae635af16484e15fa73fe74de5acaavboxsyncDECLASM(uint64_t) ASMReadTscWithAux(uint32_t *puAux);
26c76e19c6ae635af16484e15fa73fe74de5acaavboxsyncDECLINLINE(uint64_t) ASMReadTscWithAux(uint32_t *puAux)
ffaee3d9d3a768954b2b039615d71f25a6b53956vboxsync /* rdtscp is not supported by ancient linux build VM of course :-( */
ffaee3d9d3a768954b2b039615d71f25a6b53956vboxsync /*__asm__ __volatile__("rdtscp\n\t" : "=a" (u.s.Lo), "=d" (u.s.Hi), "=c" (*puAux)); */
ffaee3d9d3a768954b2b039615d71f25a6b53956vboxsync __asm__ __volatile__(".byte 0x0f,0x01,0xf9\n\t" : "=a" (u.s.Lo), "=d" (u.s.Hi), "=c" (*puAux));
26c76e19c6ae635af16484e15fa73fe74de5acaavboxsync return u.u;
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Performs the cpuid instruction returning all registers.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uOperator CPUID operation (eax).
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pvEAX Where to store eax.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pvEBX Where to store ebx.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pvECX Where to store ecx.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pvEDX Where to store edx.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @remark We're using void pointers to ease the use of special bitfield structures and such.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLASM(void) ASMCpuId(uint32_t uOperator, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(void) ASMCpuId(uint32_t uOperator, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX)
4d93fcdfb645b86163cfea77f687172295988d16vboxsync "cpuid\n\t"
4d93fcdfb645b86163cfea77f687172295988d16vboxsync "xchgl %%ebx, %1\n\t"
3e7e8dae1bd305767a63ff29f1ae8bd8dccb8000vboxsync * Performs the CPUID instruction with EAX and ECX input returning ALL output
3e7e8dae1bd305767a63ff29f1ae8bd8dccb8000vboxsync * registers.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uOperator CPUID operation (eax).
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uIdxECX ecx index
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pvEAX Where to store eax.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pvEBX Where to store ebx.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pvECX Where to store ecx.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pvEDX Where to store edx.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @remark We're using void pointers to ease the use of special bitfield structures and such.
3e7e8dae1bd305767a63ff29f1ae8bd8dccb8000vboxsync#if RT_INLINE_ASM_EXTERNAL || RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLASM(void) ASMCpuId_Idx_ECX(uint32_t uOperator, uint32_t uIdxECX, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(void) ASMCpuId_Idx_ECX(uint32_t uOperator, uint32_t uIdxECX, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "cpuid\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "xchgl %%ebx, %1\n\t"
1d9b8ac46277d5cbab832794c5cfcce1e0521873vboxsync * CPUID variant that initializes all 4 registers before the CPUID instruction.
1d9b8ac46277d5cbab832794c5cfcce1e0521873vboxsync * @returns The EAX result value.
1d9b8ac46277d5cbab832794c5cfcce1e0521873vboxsync * @param uOperator CPUID operation (eax).
1d9b8ac46277d5cbab832794c5cfcce1e0521873vboxsync * @param uInitEBX The value to assign EBX prior to the CPUID instruction.
1d9b8ac46277d5cbab832794c5cfcce1e0521873vboxsync * @param uInitECX The value to assign ECX prior to the CPUID instruction.
1d9b8ac46277d5cbab832794c5cfcce1e0521873vboxsync * @param uInitEDX The value to assign EDX prior to the CPUID instruction.
1d9b8ac46277d5cbab832794c5cfcce1e0521873vboxsync * @param pvEAX Where to store eax. Optional.
1d9b8ac46277d5cbab832794c5cfcce1e0521873vboxsync * @param pvEBX Where to store ebx. Optional.
1d9b8ac46277d5cbab832794c5cfcce1e0521873vboxsync * @param pvECX Where to store ecx. Optional.
1d9b8ac46277d5cbab832794c5cfcce1e0521873vboxsync * @param pvEDX Where to store edx. Optional.
1d9b8ac46277d5cbab832794c5cfcce1e0521873vboxsyncDECLASM(uint32_t) ASMCpuIdExSlow(uint32_t uOperator, uint32_t uInitEBX, uint32_t uInitECX, uint32_t uInitEDX,
1d9b8ac46277d5cbab832794c5cfcce1e0521873vboxsync void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Performs the cpuid instruction returning ecx and edx.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uOperator CPUID operation (eax).
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pvECX Where to store ecx.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pvEDX Where to store edx.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @remark We're using void pointers to ease the use of special bitfield structures and such.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLASM(void) ASMCpuId_ECX_EDX(uint32_t uOperator, void *pvECX, void *pvEDX);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(void) ASMCpuId_ECX_EDX(uint32_t uOperator, void *pvECX, void *pvEDX)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync ASMCpuId(uOperator, &uOperator, &uEBX, pvECX, pvEDX);
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsync * Performs the cpuid instruction returning eax.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uOperator CPUID operation (eax).
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsync * @returns EAX after cpuid operation.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsyncDECLINLINE(uint32_t) ASMCpuId_EAX(uint32_t uOperator)
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsync# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsync "cpuid\n\t"
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsync "pop %%ebx\n\t"
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsync * Performs the cpuid instruction returning ebx.
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsync * @param uOperator CPUID operation (eax).
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsync * @returns EBX after cpuid operation.
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsyncDECLINLINE(uint32_t) ASMCpuId_EBX(uint32_t uOperator)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "cpuid\n\t"
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsync "mov %%ebx, %%edx\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "pop %%ebx\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Performs the cpuid instruction returning ecx.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uOperator CPUID operation (eax).
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns ECX after cpuid operation.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(uint32_t) ASMCpuId_ECX(uint32_t uOperator)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "cpuid\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "pop %%ebx\n\t"
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsync * Performs the cpuid instruction returning edx.
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsync * @param uOperator CPUID operation (eax).
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsync * @returns EDX after cpuid operation.
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsyncDECLINLINE(uint32_t) ASMCpuId_EDX(uint32_t uOperator)
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsync# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsync "cpuid\n\t"
6a89b975ab84f4a47fb86fc27ba6c33c701720cfvboxsync "pop %%ebx\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Checks if the current CPU supports CPUID.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns true if CPUID is supported.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync return true; /* ASSUME that all amd64 compatible CPUs have cpuid. */
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#else /* !RT_ARCH_AMD64 */
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync bool fRet = false;
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "pop %1\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "mov %1, %2\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "xorl $0x200000, %1\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "push %1\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "pushf\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "pop %1\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "cmpl %1, %2\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "setne %0\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "push %2\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#endif /* !RT_ARCH_AMD64 */
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Gets the APIC ID of the current CPU.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns the APIC ID.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
4d93fcdfb645b86163cfea77f687172295988d16vboxsync "cpuid\n\t"
4d93fcdfb645b86163cfea77f687172295988d16vboxsync "xchgl %%ebx,%1\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Tests if it a genuine Intel CPU based on the ASMCpuId(0) output.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uEBX EBX return from ASMCpuId(0)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uECX ECX return from ASMCpuId(0)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uEDX EDX return from ASMCpuId(0)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(bool) ASMIsIntelCpuEx(uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Tests if this is a genuine Intel CPU.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @remarks ASSUMES that cpuid is supported by the CPU.
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync * Tests if it an authentic AMD CPU based on the ASMCpuId(0) output.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uEBX EBX return from ASMCpuId(0)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uECX ECX return from ASMCpuId(0)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uEDX EDX return from ASMCpuId(0)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(bool) ASMIsAmdCpuEx(uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Tests if this is an authentic AMD CPU.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @remarks ASSUMES that cpuid is supported by the CPU.
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync * Tests if it a centaur hauling VIA CPU based on the ASMCpuId(0) output.
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync * @param uEBX EBX return from ASMCpuId(0).
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync * @param uECX ECX return from ASMCpuId(0).
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync * @param uEDX EDX return from ASMCpuId(0).
a0a962c856e508933f3137cb0d583af5c206dc55vboxsyncDECLINLINE(bool) ASMIsViaCentaurCpuEx(uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync * Tests if this is a centaur hauling VIA CPU.
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync * @remarks ASSUMES that cpuid is supported by the CPU.
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync * Checks whether ASMCpuId_EAX(0x00000000) indicates a valid range.
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync * @param uEAX The EAX value of CPUID leaf 0x00000000.
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync * @note This only succeeds if there are at least two leaves in the range.
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync * @remarks The upper range limit is just some half reasonable value we've
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync * picked out of thin air.
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync return uEAX >= UINT32_C(0x00000001) && uEAX <= UINT32_C(0x000fffff);
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync * Checks whether ASMCpuId_EAX(0x80000000) indicates a valid range.
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync * This only succeeds if there are at least two leaves in the range.
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync * @param uEAX The EAX value of CPUID leaf 0x80000000.
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync * @note This only succeeds if there are at least two leaves in the range.
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync * @remarks The upper range limit is just some half reasonable value we've
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync * picked out of thin air.
a0a962c856e508933f3137cb0d583af5c206dc55vboxsync return uEAX >= UINT32_C(0x80000001) && uEAX <= UINT32_C(0x800fffff);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Extracts the CPU family from ASMCpuId(1) or ASMCpuId(0x80000001)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns Family.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uEAX EAX return from ASMCpuId(1) or ASMCpuId(0x80000001).
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Extracts the CPU model from ASMCpuId(1) or ASMCpuId(0x80000001), Intel variant.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns Model.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(uint32_t) ASMGetCpuModelIntel(uint32_t uEAX)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync return ((uEAX >> 8) & 0xf) == 0xf || (((uEAX >> 8) & 0xf) == 0x6) /* family! */
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Extracts the CPU model from ASMCpuId(1) or ASMCpuId(0x80000001), AMD variant.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns Model.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(uint32_t) ASMGetCpuModelAMD(uint32_t uEAX)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Extracts the CPU model from ASMCpuId(1) or ASMCpuId(0x80000001)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns Model.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param fIntel Whether it's an intel CPU. Use ASMIsIntelCpuEx() or ASMIsIntelCpu().
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(uint32_t) ASMGetCpuModel(uint32_t uEAX, bool fIntel)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync return ((uEAX >> 8) & 0xf) == 0xf || (((uEAX >> 8) & 0xf) == 0x6 && fIntel) /* family! */
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Extracts the CPU stepping from ASMCpuId(1) or ASMCpuId(0x80000001)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns Model.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(uint32_t) ASMGetCpuStepping(uint32_t uEAX)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns cr0.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %%cr0, %0\t\n" : "=r" (uCR0));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %%cr0, %0\t\n" : "=r" (uCR0));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Sets the CR0 register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uCR0 The new CR0 value.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %0, %%cr0\n\t" :: "r" (uCR0));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %0, %%cr0\n\t" :: "r" (uCR0));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns cr2.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %%cr2, %0\t\n" : "=r" (uCR2));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %%cr2, %0\t\n" : "=r" (uCR2));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Sets the CR2 register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uCR2 The new CR0 value.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %0, %%cr2\n\t" :: "r" (uCR2));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %0, %%cr2\n\t" :: "r" (uCR2));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns cr3.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %%cr3, %0\t\n" : "=r" (uCR3));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %%cr3, %0\t\n" : "=r" (uCR3));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Sets the CR3 register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uCR3 New CR3 value.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %0, %%cr3\n\t" : : "r" (uCR3));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %0, %%cr3\n\t" : : "r" (uCR3));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Reloads the CR3 register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "movq %0, %%cr3\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync : "=r" (u));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "movl %0, %%cr3\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync : "=r" (u));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns cr4.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %%cr4, %0\t\n" : "=r" (uCR4));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %%cr4, %0\t\n" : "=r" (uCR4));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync /*mov eax, cr4*/
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Sets the CR4 register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uCR4 New CR4 value.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %0, %%cr4\n\t" : : "r" (uCR4));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %0, %%cr4\n\t" : : "r" (uCR4));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns cr8.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @remark The lock prefix hack for access from non-64-bit modes is NOT used and 0 is returned.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %%cr8, %0\t\n" : "=r" (uCR8));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync# else /* !RT_ARCH_AMD64 */
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync# endif /* !RT_ARCH_AMD64 */
7a33455519f76382026197f01d5cac3f6a98ed51vboxsync * Get XCR0 (eXtended feature Control Register 0).
7a33455519f76382026197f01d5cac3f6a98ed51vboxsync * @returns xcr0.
7a33455519f76382026197f01d5cac3f6a98ed51vboxsync * Sets the XCR0 register.
7a33455519f76382026197f01d5cac3f6a98ed51vboxsync * @param uXcr0 The new XCR0 value.
d16f75bad381547b34a1f315da059b782f4c21d3vboxsync * Save extended CPU state.
d16f75bad381547b34a1f315da059b782f4c21d3vboxsync * @param pXStateArea Where to save the state.
d16f75bad381547b34a1f315da059b782f4c21d3vboxsync * @param fComponents Which state components to save.
d16f75bad381547b34a1f315da059b782f4c21d3vboxsyncDECLASM(void) ASMXSave(PX86XSAVEAREA pXStateArea, uint64_t fComponents);
d16f75bad381547b34a1f315da059b782f4c21d3vboxsync * Loads extended CPU state.
d16f75bad381547b34a1f315da059b782f4c21d3vboxsync * @param pXStateArea Where to load the state from.
d16f75bad381547b34a1f315da059b782f4c21d3vboxsync * @param fComponents Which state components to load.
d16f75bad381547b34a1f315da059b782f4c21d3vboxsyncDECLASM(void) ASMXLoad(PCX86XSAVEAREA pXStateArea, uint64_t fComponents);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Enables interrupts (EFLAGS.IF).
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Disables interrupts (!EFLAGS.IF).
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Disables interrupts and returns previous xFLAGS.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "popq %0\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "popl %0\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync# elif RT_INLINE_ASM_USES_INTRIN && !defined(RT_ARCH_X86)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Are interrupts enabled?
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns true / false.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync return uFlags & 0x200 /* X86_EFL_IF */ ? true : false;
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Halts the CPU until interrupted.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Reads a machine specific register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns Register content.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uRegister Register to read.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync return u.u;
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Writes a machine specific register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns Register content.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uRegister Register to write to.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param u64Val Value to write.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLASM(void) ASMWrMsr(uint32_t uRegister, uint64_t u64Val);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(void) ASMWrMsr(uint32_t uRegister, uint64_t u64Val)
9c5875d62215e6a088a86658e5553af6b8401f1cvboxsync * Reads a machine specific register, extended version (for AMD).
9c5875d62215e6a088a86658e5553af6b8401f1cvboxsync * @returns Register content.
9c5875d62215e6a088a86658e5553af6b8401f1cvboxsync * @param uRegister Register to read.
9c5875d62215e6a088a86658e5553af6b8401f1cvboxsync * @param uXDI RDI/EDI value.
9c5875d62215e6a088a86658e5553af6b8401f1cvboxsyncDECLASM(uint64_t) ASMRdMsrEx(uint32_t uRegister, RTCCUINTREG uXDI);
9c5875d62215e6a088a86658e5553af6b8401f1cvboxsyncDECLINLINE(uint64_t) ASMRdMsrEx(uint32_t uRegister, RTCCUINTREG uXDI)
9c5875d62215e6a088a86658e5553af6b8401f1cvboxsync return u.u;
9c5875d62215e6a088a86658e5553af6b8401f1cvboxsync * Writes a machine specific register, extended version (for AMD).
9c5875d62215e6a088a86658e5553af6b8401f1cvboxsync * @returns Register content.
9c5875d62215e6a088a86658e5553af6b8401f1cvboxsync * @param uRegister Register to write to.
9c5875d62215e6a088a86658e5553af6b8401f1cvboxsync * @param uXDI RDI/EDI value.
9c5875d62215e6a088a86658e5553af6b8401f1cvboxsync * @param u64Val Value to write.
9c5875d62215e6a088a86658e5553af6b8401f1cvboxsyncDECLASM(void) ASMWrMsrEx(uint32_t uRegister, RTCCUINTREG uXDI, uint64_t u64Val);
9c5875d62215e6a088a86658e5553af6b8401f1cvboxsyncDECLINLINE(void) ASMWrMsrEx(uint32_t uRegister, RTCCUINTREG uXDI, uint64_t u64Val)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Reads low part of a machine specific register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns Register content.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uRegister Register to read.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(uint32_t) ASMRdMsr_Low(uint32_t uRegister)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Reads high part of a machine specific register.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns Register content.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uRegister Register to read.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLASM(uint32_t) ASMRdMsr_High(uint32_t uRegister);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(uint32_t) ASMRdMsr_High(uint32_t uRegister)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Gets dr0.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns dr0.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %%dr0, %0\n\t" : "=r" (uDR0));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %%dr0, %0\n\t" : "=r" (uDR0));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Gets dr1.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns dr1.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %%dr1, %0\n\t" : "=r" (uDR1));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %%dr1, %0\n\t" : "=r" (uDR1));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Gets dr2.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns dr2.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %%dr2, %0\n\t" : "=r" (uDR2));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %%dr2, %0\n\t" : "=r" (uDR2));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Gets dr3.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns dr3.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %%dr3, %0\n\t" : "=r" (uDR3));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %%dr3, %0\n\t" : "=r" (uDR3));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Gets dr6.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns dr6.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %%dr6, %0\n\t" : "=r" (uDR6));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %%dr6, %0\n\t" : "=r" (uDR6));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Reads and clears DR6.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns DR6.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __writedr(6, 0xffff0ff0U); /* 31-16 and 4-11 are 1's, 12 and 63-31 are zero. */
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync RTCCUINTREG uNewValue = 0xffff0ff0U;/* 31-16 and 4-11 are 1's, 12 and 63-31 are zero. */
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "movq %1, %%dr6\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync "movl %1, %%dr6\n\t"
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync mov ecx, 0ffff0ff0h; /* 31-16 and 4-11 are 1's, 12 and 63-31 are zero. */
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync mov ecx, 0ffff0ff0h; /* 31-16 and 4-11 are 1's, 12 is zero. */
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Gets dr7.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns dr7.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %%dr7, %0\n\t" : "=r" (uDR7));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %%dr7, %0\n\t" : "=r" (uDR7));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Sets dr0.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uDRVal Debug register value to write
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %0, %%dr0\n\t" : : "r" (uDRVal));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %0, %%dr0\n\t" : : "r" (uDRVal));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Sets dr1.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uDRVal Debug register value to write
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %0, %%dr1\n\t" : : "r" (uDRVal));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %0, %%dr1\n\t" : : "r" (uDRVal));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Sets dr2.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uDRVal Debug register value to write
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %0, %%dr2\n\t" : : "r" (uDRVal));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %0, %%dr2\n\t" : : "r" (uDRVal));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Sets dr3.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uDRVal Debug register value to write
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %0, %%dr3\n\t" : : "r" (uDRVal));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %0, %%dr3\n\t" : : "r" (uDRVal));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Sets dr6.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uDRVal Debug register value to write
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %0, %%dr6\n\t" : : "r" (uDRVal));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %0, %%dr6\n\t" : : "r" (uDRVal));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Sets dr7.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param uDRVal Debug register value to write
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movq %0, %%dr7\n\t" : : "r" (uDRVal));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __asm__ __volatile__("movl %0, %%dr7\n\t" : : "r" (uDRVal));
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Writes a 8-bit unsigned integer to an I/O port, ordered.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param Port I/O port to write to.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param u8 8-bit integer to write.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(void) ASMOutU8(RTIOPORT Port, uint8_t u8)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Reads a 8-bit unsigned integer from an I/O port, ordered.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns 8-bit integer.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param Port I/O port to read from.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Writes a 16-bit unsigned integer to an I/O port, ordered.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param Port I/O port to write to.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param u16 16-bit integer to write.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLASM(void) ASMOutU16(RTIOPORT Port, uint16_t u16);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(void) ASMOutU16(RTIOPORT Port, uint16_t u16)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Reads a 16-bit unsigned integer from an I/O port, ordered.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns 16-bit integer.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param Port I/O port to read from.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Writes a 32-bit unsigned integer to an I/O port, ordered.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param Port I/O port to write to.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param u32 32-bit integer to write.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLASM(void) ASMOutU32(RTIOPORT Port, uint32_t u32);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(void) ASMOutU32(RTIOPORT Port, uint32_t u32)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Reads a 32-bit unsigned integer from an I/O port, ordered.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @returns 32-bit integer.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param Port I/O port to read from.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Writes a string of 8-bit unsigned integer items to an I/O port, ordered.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param Port I/O port to write to.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pau8 Pointer to the string buffer.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param c The number of items to write.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLASM(void) ASMOutStrU8(RTIOPORT Port, uint8_t const *pau8, size_t c);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(void) ASMOutStrU8(RTIOPORT Port, uint8_t const *pau8, size_t c)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __outbytestring(Port, (unsigned char *)pau8, (unsigned long)c);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Reads a string of 8-bit unsigned integer items from an I/O port, ordered.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param Port I/O port to read from.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pau8 Pointer to the string buffer (output).
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param c The number of items to read.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLASM(void) ASMInStrU8(RTIOPORT Port, uint8_t *pau8, size_t c);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(void) ASMInStrU8(RTIOPORT Port, uint8_t *pau8, size_t c)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Writes a string of 16-bit unsigned integer items to an I/O port, ordered.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param Port I/O port to write to.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pau16 Pointer to the string buffer.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param c The number of items to write.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLASM(void) ASMOutStrU16(RTIOPORT Port, uint16_t const *pau16, size_t c);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(void) ASMOutStrU16(RTIOPORT Port, uint16_t const *pau16, size_t c)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __outwordstring(Port, (unsigned short *)pau16, (unsigned long)c);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Reads a string of 16-bit unsigned integer items from an I/O port, ordered.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param Port I/O port to read from.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pau16 Pointer to the string buffer (output).
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param c The number of items to read.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLASM(void) ASMInStrU16(RTIOPORT Port, uint16_t *pau16, size_t c);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(void) ASMInStrU16(RTIOPORT Port, uint16_t *pau16, size_t c)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Writes a string of 32-bit unsigned integer items to an I/O port, ordered.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param Port I/O port to write to.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pau32 Pointer to the string buffer.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param c The number of items to write.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLASM(void) ASMOutStrU32(RTIOPORT Port, uint32_t const *pau32, size_t c);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(void) ASMOutStrU32(RTIOPORT Port, uint32_t const *pau32, size_t c)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __outdwordstring(Port, (unsigned long *)pau32, (unsigned long)c);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Reads a string of 32-bit unsigned integer items from an I/O port, ordered.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param Port I/O port to read from.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pau32 Pointer to the string buffer (output).
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param c The number of items to read.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLASM(void) ASMInStrU32(RTIOPORT Port, uint32_t *pau32, size_t c);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(void) ASMInStrU32(RTIOPORT Port, uint32_t *pau32, size_t c)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync __indwordstring(Port, (unsigned long *)pau32, (unsigned long)c);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Invalidate page.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * @param pv Address of the page to invalidate.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Write back the internal caches and invalidate them.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLASM(void) ASMWriteBackAndInvalidateCaches(void);
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsyncDECLINLINE(void) ASMWriteBackAndInvalidateCaches(void)
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Invalidate internal and (perhaps) external caches without first
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * flushing dirty cache lines. Use with extreme care.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Memory load/store fence, waits for any pending writes and reads to complete.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Requires the X86_CPUID_FEATURE_EDX_SSE2 CPUID bit set.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Memory store fence, waits for any writes to complete.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Requires the X86_CPUID_FEATURE_EDX_SSE CPUID bit set.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Memory load fence, waits for any pending reads to complete.
831acea16fc15fff2cf90a217d02eea69bf27a40vboxsync * Requires the X86_CPUID_FEATURE_EDX_SSE2 CPUID bit set.