x86.h revision 9f9a20823b87e89c1b5cb45eb9b5699b29bfefeb
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync * X86 (and AMD64) Structures and Definitions (VMM,++).
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync * x86.mac is generated from this file by running 'kmk incs' in the root.
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync * Copyright (C) 2006-2009 Oracle Corporation
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync * available from http://www.virtualbox.org. This file is free software;
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * you can redistribute it and/or modify it under the terms of the GNU
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * General Public License (GPL) as published by the Free Software
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * The contents of this file may alternatively be used under the terms
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * of the Common Development and Distribution License Version 1.0
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * VirtualBox OSE distribution, in which case the provisions of the
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * CDDL are applicable instead of those of the GPL.
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * You may elect to license modified versions of this file under the
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync * terms and conditions of either the GPL or the CDDL or both.
aa4bcf0a4b2db3ac352b56a291d49cb8d4b66d32vboxsync/* Workaround for Solaris sys/regset.h defining CS, DS */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** @defgroup grp_x86 x86 Types and Definitions
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync * EFLAGS Bits.
192a1d418422c3b5905dd2577527c07a8ed8b61evboxsync /** Bit 0 - CF - Carry flag - Status flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 1 - 1 - Reserved flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 2 - PF - Parity flag - Status flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 3 - 0 - Reserved flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 5 - 0 - Reserved flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 6 - ZF - Zero flag - Status flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 7 - SF - Signed flag - Status flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 8 - TF - Trap flag - System flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 9 - IF - Interrupt flag - System flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 10 - DF - Direction flag - Control flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 11 - OF - Overflow flag - Status flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 14 - NT - Nested task flag - System flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 15 - 0 - Reserved flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 16 - RF - Resume flag - System flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 17 - VM - Virtual 8086 mode - System flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 19 - VIF - Virtual interupt flag - System flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 22-31 - 0 - Reserved flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Pointer to EFLAGS bits. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Pointer to const EFLAGS bits. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** The plain unsigned view. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** The bitfield view. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** The 8-bit view. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** The 16-bit view. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** The 32-bit view. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** The 32-bit view. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Pointer to EFLAGS. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Pointer to const EFLAGS. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync * RFLAGS (32 upper bits are reserved).
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** The plain unsigned view. */
192a1d418422c3b5905dd2577527c07a8ed8b61evboxsync /** The bitfield view. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** The 8-bit view. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** The 16-bit view. */
3ae788d4138a852743619b65c7404deb5cbae3e7vboxsync /** The 32-bit view. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** The 64-bit view. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** The 64-bit view. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Pointer to RFLAGS. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Pointer to const RFLAGS. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** @name EFLAGS
2a2b173b54c259e34320ce0acf26f18e9382ce2avboxsync/** Bit 0 - CF - Carry flag - Status flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 2 - PF - Parity flag - Status flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 6 - ZF - Zero flag - Status flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 7 - SF - Signed flag - Status flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 8 - TF - Trap flag - System flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 9 - IF - Interrupt flag - System flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 10 - DF - Direction flag - Control flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 11 - OF - Overflow flag - Status flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 14 - NT - Nested task flag - System flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 16 - RF - Resume flag - System flag. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 17 - VM - Virtual 8086 mode - System flag. */
3ae788d4138a852743619b65c7404deb5cbae3e7vboxsync/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
3ae788d4138a852743619b65c7404deb5cbae3e7vboxsync/** Bit 19 - VIF - Virtual interupt flag - System flag. */
3ae788d4138a852743619b65c7404deb5cbae3e7vboxsync/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
3ae788d4138a852743619b65c7404deb5cbae3e7vboxsync/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
3ae788d4138a852743619b65c7404deb5cbae3e7vboxsync/** IOPL shift. */
3ae788d4138a852743619b65c7404deb5cbae3e7vboxsync/** The the IOPL level from the flags. */
3ae788d4138a852743619b65c7404deb5cbae3e7vboxsync#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
3ae788d4138a852743619b65c7404deb5cbae3e7vboxsync/** Bits restored by popf */
3ae788d4138a852743619b65c7404deb5cbae3e7vboxsync#define X86_EFL_POPF_BITS (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID)
3ae788d4138a852743619b65c7404deb5cbae3e7vboxsync/** CPUID Feature information - ECX.
3ae788d4138a852743619b65c7404deb5cbae3e7vboxsync * CPUID query with EAX=1.
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 0 - SSE3 - Supports SSE3 or not. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Reserved. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 2 - DS Area 64-bit layout. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 5 - VMX - Virtual Machine Technology. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 6 - SMX: Safer Mode Extensions. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 7 - EST - Enh. SpeedStep Tech. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 8 - TM2 - Terminal Monitor 2. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 10 - CNTX-ID - L1 Context ID. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 11 - FMA. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 12 - Reserved. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 13 - CX16 - CMPXCHG16B. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Reserved. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 18 - Direct Cache Access. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 21 - x2APIC. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /** Bit 22 - MOVBE - Supports MOVBE. */
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync /** Bit 23 - POPCNT - Supports POPCNT. */
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync /** Bit 24 - Reserved. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 25 - AES. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 26 - XSAVE - Supports XSAVE. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Reserved. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Pointer to CPUID Feature Information - ECX. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Pointer to const CPUID Feature Information - ECX. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** CPUID Feature Information - EDX.
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync * CPUID query with EAX=1.
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 0 - FPU - x87 FPU on Chip. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 2 - DE - Debugging extensions. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 3 - PSE - Page Size Extension. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 4 - TSC - Time Stamp Counter. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 6 - PAE - Physical Address Extension. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 7 - MCE - Machine Check Exception. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 8 - CX8 - CMPXCHG8B instruction. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 9 - APIC - APIC On-Chip. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 10 - Reserved. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 12 - MTRR - Memory Type Range Registers. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 13 - PGE - PTE Global Bit. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 14 - MCA - Machine Check Architecture. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 15 - CMOV - Conditional Move Instructions. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 16 - PAT - Page Attribute Table. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 18 - PSN - Processor Serial Number. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 19 - CLFSH - CLFLUSH Instruction. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 20 - Reserved. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 21 - DS - Debug Store. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
4e47bb772df0d04d1ded3e06354de547d52e2d06vboxsync /** Bit 23 - MMX - Intel MMX 'Technology'. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 25 - SSE - SSE Support. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /** Bit 26 - SSE2 - SSE2 Support. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 27 - SS - Self Snoop. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 28 - HTT - Hyper-Threading Technology. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 29 - TM - Thermal Monitor. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** Bit 30 - Reserved - . */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /** Bit 31 - PBE - Pending Break Enabled. */
4e47bb772df0d04d1ded3e06354de547d52e2d06vboxsync/** Pointer to CPUID Feature Information - EDX. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Pointer to const CPUID Feature Information - EDX. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** @name CPUID Vendor information.
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync * CPUID query with EAX=0.
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
4e47bb772df0d04d1ded3e06354de547d52e2d06vboxsync#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** @name CPUID Feature information.
4e47bb772df0d04d1ded3e06354de547d52e2d06vboxsync * CPUID query with EAX=1.
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** ECX Bit 5 - VMX - Virtual Machine Technology. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** ECX Bit 6 - SMX - Safer Mode Extensions. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** ECX Bit 12 - FMA. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** ECX Bit 13 - CX16 - CMPXCHG16B. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** ECX Bit 18 - DCA - Direct Cache Access. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** ECX Bit 21 - x2APIC support. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** ECX Bit 22 - MOVBE instruction. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** ECX Bit 23 - POPCNT instruction. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** ECX Bit 25 - AES instructions. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** ECX Bit 26 - XSAVE instruction. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** ECX Bit 27 - OSXSAVE instruction. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** ECX Bit 28 - AVX. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 0 - FPU - x87 FPU on Chip. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 2 - DE - Debugging extensions. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 3 - PSE - Page Size Extension. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 4 - TSC - Time Stamp Counter. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 6 - PAE - Physical Address Extension. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 7 - MCE - Machine Check Exception. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 8 - CX8 - CMPXCHG8B instruction. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 9 - APIC - APIC On-Chip. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 12 - MTRR - Memory Type Range Registers. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 13 - PGE - PTE Global Bit. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 14 - MCA - Machine Check Architecture. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 15 - CMOV - Conditional Move Instructions. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 16 - PAT - Page Attribute Table. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 18 - PSN - Processor Serial Number. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 19 - CLFSH - CLFLUSH Instruction. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 21 - DS - Debug Store. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 23 - MMX - Intel MMX Technology. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 25 - SSE - SSE Support. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 26 - SSE2 - SSE2 Support. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 27 - SS - Self Snoop. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 28 - HTT - Hyper-Threading Technology. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 29 - TM - Therm. Monitor. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 31 - PBE - Pending Break Enabled. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** @name CPUID mwait/monitor information.
5b0a093ca572a855886faa6747ad46df859dd041vboxsync * CPUID query with EAX=5.
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** @name CPUID AMD Feature information.
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync * CPUID query with EAX=0x80000001.
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 0 - FPU - x87 FPU on Chip. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
993a55bd118e0b54549b3f0b380a8fbd6246a040vboxsync/** Bit 2 - DE - Debugging extensions. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 3 - PSE - Page Size Extension. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 4 - TSC - Time Stamp Counter. */
192a1d418422c3b5905dd2577527c07a8ed8b61evboxsync/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 6 - PAE - Physical Address Extension. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 7 - MCE - Machine Check Exception. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 8 - CX8 - CMPXCHG8B instruction. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 9 - APIC - APIC On-Chip. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 12 - MTRR - Memory Type Range Registers. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 13 - PGE - PTE Global Bit. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 14 - MCA - Machine Check Architecture. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 15 - CMOV - Conditional Move Instructions. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 16 - PAT - Page Attribute Table. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 20 - NX - AMD No-Execute Page Protection. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 23 - MMX - Intel MMX Technology. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 29 - LM - AMD Long Mode. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 31 - 3DNOW - AMD 3DNow. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 1 - CMPL - Core multi-processing legacy mode. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 2 - SVM - AMD VM extensions. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 9 - OSVW - AMD OS visible workaround. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 10 - IBS - Instruct based sampling. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 11 - SSE5 - SSE5 instruction support. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
0c8e85263a357c44964520942cb5816ab1c2e69dvboxsync/** Bit 13 - WDT - AMD Watchdog timer support. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** @name CPUID AMD Feature information.
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync * CPUID query with EAX=0x80000007.
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 0 - TS - Temperature Sensor. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 1 - FID - Frequency ID Control. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 2 - VID - Voltage ID Control. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 3 - TTP - THERMTRIP. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 4 - TM - Hardware Thermal Control. */
0c8e85263a357c44964520942cb5816ab1c2e69dvboxsync/** Bit 5 - STC - Software Thermal Control. */
0c8e85263a357c44964520942cb5816ab1c2e69dvboxsync/** Bit 6 - MC - 100 Mhz Multiplier Control. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 7 - HWPSTATE - Hardware P-State Control. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 8 - TSCINVAR - TSC Invariant. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** @name CR0
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 0 - PE - Protection Enabled */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 1 - MP - Monitor Coprocessor */
4e47bb772df0d04d1ded3e06354de547d52e2d06vboxsync/** Bit 2 - EM - Emulation. */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync/** Bit 3 - TS - Task Switch. */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync/** Bit 5 - NE - Numeric error. */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync/** Bit 16 - WP - Write Protect. */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync/** Bit 18 - AM - Alignment Mask. */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync/** Bit 29 - NW - Not Write-though. */
d1e9999d55e7ac80a28692c161710be98071fc00vboxsync/** Bit 30 - WP - Cache Disable. */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync/** Bit 31 - PG - Paging. */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync/** @name CR3
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync/** Bit 3 - PWT - Page-level Writes Transparent. */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync/** Bit 4 - PCD - Page-level Cache Disable. */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync/** Bits 12-31 - - Page directory page number. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bits 5-31 - - PAE Page directory page number. */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync/** Bits 12-51 - - AMD64 Page directory page number. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** @name CR4
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync/** Bit 2 - TSD - Time Stamp Disable. */
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync/** Bit 3 - DE - Debugging Extensions. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 4 - PSE - Page Size Extension. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 5 - PAE - Physical Address Extension. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 6 - MCE - Machine-Check Enable. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 7 - PGE - Page Global Enable. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 13 - VMXE - VMX mode is enabled. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** @name DR6
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 0 - B0 - Breakpoint 0 condition detected. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 1 - B1 - Breakpoint 1 condition detected. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 2 - B2 - Breakpoint 2 condition detected. */
e8859cfff41731e3688972d64cf6d5575addcd8fvboxsync/** Bit 3 - B3 - Breakpoint 3 condition detected. */
e8859cfff41731e3688972d64cf6d5575addcd8fvboxsync/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
e8859cfff41731e3688972d64cf6d5575addcd8fvboxsync/** Bit 14 - BS - Single step */
e8859cfff41731e3688972d64cf6d5575addcd8fvboxsync/** Bit 15 - BT - Task switch. (TSS T bit.) */
e8859cfff41731e3688972d64cf6d5575addcd8fvboxsync/** Value of DR6 after powerup/reset. */
e8859cfff41731e3688972d64cf6d5575addcd8fvboxsync/** @name DR7
e8859cfff41731e3688972d64cf6d5575addcd8fvboxsync/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
d3dea25ec07f6546715fe3af943ea863294b392evboxsync * any DR register is accessed. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync/** Bits which must be 1s. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** Calcs the L bit of Nth breakpoint.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * @param iBp The breakpoint number [0..3].
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** Calcs the G bit of Nth breakpoint.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * @param iBp The breakpoint number [0..3].
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** @name Read/Write values.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** Break on instruction fetch only. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** Break on write only. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** Break on I/O read/write. This is only defined if CR4.DE is set. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** Break on read or write (but not instruction fetches). */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** Shifts a X86_DR7_RW_* value to its right place.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * @param iBp The breakpoint number [0..3].
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * @param fRw One of the X86_DR7_RW_* value.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** @name Length values.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync#define X86_DR7_LEN_QWORD 2U /**< AMD64 long mode only. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** Shifts a X86_DR7_LEN_* value to its right place.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * @param iBp The breakpoint number [0..3].
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * @param cb One of the X86_DR7_LEN_* values.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** Fetch the breakpoint length bits from the DR7 value.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * @param uDR7 DR7 value
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * @param iBp The breakpoint number [0..3].
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** Mask used to check if any breakpoints are enabled. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync#define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7))
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** Mask used to check if any io breakpoints are set. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) | X86_DR7_RW(1, X86_DR7_RW_IO) | X86_DR7_RW(2, X86_DR7_RW_IO) | X86_DR7_RW(3, X86_DR7_RW_IO))
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** Value of DR7 after powerup/reset. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** @name Machine Specific Registers
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** Time Stamp Counter. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** CPU Feature control. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** BIOS update trigger (microcode update). */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** BIOS update signature (microcode). */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** General performance counter no. 0. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** General performance counter no. 1. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** General performance counter no. 2. */
682342827b0e80c493c820603508e79e76c42658vboxsync/** General performance counter no. 3. */
682342827b0e80c493c820603508e79e76c42658vboxsync/** Nehalem power control. */
682342827b0e80c493c820603508e79e76c42658vboxsync/** Get FSB clock status (Intel-specific). */
2a2b173b54c259e34320ce0acf26f18e9382ce2avboxsync/** MTRR Capabilities. */
2a2b173b54c259e34320ce0acf26f18e9382ce2avboxsync#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
2a2b173b54c259e34320ce0acf26f18e9382ce2avboxsync/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
2a2b173b54c259e34320ce0acf26f18e9382ce2avboxsync * R0 SS == CS + 8
2a2b173b54c259e34320ce0acf26f18e9382ce2avboxsync * R3 CS == CS + 16
2a2b173b54c259e34320ce0acf26f18e9382ce2avboxsync * R3 SS == CS + 24
2a2b173b54c259e34320ce0acf26f18e9382ce2avboxsync/** SYSENTER_ESP - the R0 ESP. */
2a2b173b54c259e34320ce0acf26f18e9382ce2avboxsync/** SYSENTER_EIP - the R0 EIP. */
2a2b173b54c259e34320ce0acf26f18e9382ce2avboxsync/** Machine Check Global Capabilities Register. */
2a2b173b54c259e34320ce0acf26f18e9382ce2avboxsync/** Machine Check Global Status Register. */
2a2b173b54c259e34320ce0acf26f18e9382ce2avboxsync/** Machine Check Global Control Register. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Trace/Profile Resource Control (R/W) */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/* Page Attribute Table. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Performance counter MSRs. (Intel only) */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Enable misc. processor features (R/W). */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync/** MTRR Default Range. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync/** Basic VMX information. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Allowed settings for pin-based VM execution controls */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Allowed settings for proc-based VM execution controls */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Allowed settings for the VMX exit controls. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Allowed settings for the VMX entry controls. */
6c2750d8e30830bf114880ca33922b108ab3e942vboxsync/** Misc VMX info. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Fixed cleared bits in CR0. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Fixed set bits in CR0. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Fixed cleared bits in CR4. */
6c2750d8e30830bf114880ca33922b108ab3e942vboxsync/** Fixed set bits in CR4. */
6c2750d8e30830bf114880ca33922b108ab3e942vboxsync/** Information for enumerating fields in the VMCS. */
6c2750d8e30830bf114880ca33922b108ab3e942vboxsync/** Allowed settings for secondary proc-based VM execution controls */
6c2750d8e30830bf114880ca33922b108ab3e942vboxsync/** EPT capabilities. */
6c2750d8e30830bf114880ca33922b108ab3e942vboxsync/** DS Save Area (R/W). */
6c2750d8e30830bf114880ca33922b108ab3e942vboxsync/** X2APIC MSR ranges. */
6c2750d8e30830bf114880ca33922b108ab3e942vboxsync/** K6 EFER - Extended Feature Enable Register. */
f9f1d016018f6c0d3c4a81299816198e1a377c90vboxsync/** @todo document EFER */
f9f1d016018f6c0d3c4a81299816198e1a377c90vboxsync/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync/** Bit 8 - LME - Long mode enabled. (R/W) */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 10 - LMA - Long mode active. (R) */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
f9f1d016018f6c0d3c4a81299816198e1a377c90vboxsync/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** K6 STAR - SYSCALL/RET targets. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Shift value for getting the SYSRET CS and SS value. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Shift value for getting the SYSCALL CS and SS value. */
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync/** Selector mask for use after shifting. */
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync/** The mask which give the SYSCALL EIP. */
6ba706e9f431401d425d16817fdcd6316f83b584vboxsync/** K6 WHCR - Write Handling Control Register. */
6ba706e9f431401d425d16817fdcd6316f83b584vboxsync/** K6 UWCCR - UC/WC Cacheability Control Register. */
6ba706e9f431401d425d16817fdcd6316f83b584vboxsync/** K6 PSOR - Processor State Observability Register. */
6ba706e9f431401d425d16817fdcd6316f83b584vboxsync/** K6 PFIR - Page Flush/Invalidate Register. */
6ba706e9f431401d425d16817fdcd6316f83b584vboxsync/** Performance counter MSRs. (AMD only) */
6ba706e9f431401d425d16817fdcd6316f83b584vboxsync/** K8 LSTAR - Long mode SYSCALL target (RIP). */
6ba706e9f431401d425d16817fdcd6316f83b584vboxsync/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
6ba706e9f431401d425d16817fdcd6316f83b584vboxsync/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
6ba706e9f431401d425d16817fdcd6316f83b584vboxsync/** K8 FS.base - The 64-bit base FS register. */
6ba706e9f431401d425d16817fdcd6316f83b584vboxsync/** K8 GS.base - The 64-bit base GS register. */
6ba706e9f431401d425d16817fdcd6316f83b584vboxsync/** K8 KernelGSbase - Used with SWAPGS. */
d1e9999d55e7ac80a28692c161710be98071fc00vboxsync/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync * host state during world switch.
192a1d418422c3b5905dd2577527c07a8ed8b61evboxsync/** @name Page Table / Directory / Directory Pointers / L4.
192a1d418422c3b5905dd2577527c07a8ed8b61evboxsync/** Page table/directory entry as an unsigned integer. */
192a1d418422c3b5905dd2577527c07a8ed8b61evboxsync/** Pointer to a page table/directory table entry as an unsigned integer. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Pointer to an const page table/directory table entry as an unsigned integer. */
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync/** Number of entries in a 32-bit PT/PD. */
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
#define X86_PTE_BIT_P 0
#if 1 /* we're using this internally and have to mask of the top 16-bit. */ /** @todo this should be safe to ditch now */
typedef struct X86PTEBITS
} X86PTEBITS;
typedef union X86PTE
X86PGUINT u;
X86PTEBITS n;
} X86PTE;
typedef struct X86PTEPAEBITS
typedef union X86PTEPAE
X86PGPAEUINT u;
} X86PTEPAE;
typedef struct X86PT
} X86PT;
typedef struct X86PTPAE
} X86PTPAE;
typedef struct X86PDEBITS
} X86PDEBITS;
typedef struct X86PDEPAEBITS
* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
typedef struct X86PDE4MBITS
} X86PDE4MBITS;
typedef struct X86PDE2MPAEBITS
typedef union X86PDE
X86PGUINT u;
X86PDEBITS n;
X86PDE4MBITS b;
} X86PDE;
typedef union X86PDEPAE
X86PGPAEUINT u;
} X86PDEPAE;
typedef struct X86PD
} X86PD;
typedef struct X86PDPAE
} X86PDPAE;
typedef struct X86PDPEBITS
} X86PDPEBITS;
typedef struct X86PDPEAMD64BITS
typedef union X86PDPE
X86PGPAEUINT u;
X86PDPEBITS n;
} X86PDPE;
typedef struct X86PDPT
} X86PDPT;
typedef struct X86PML4EBITS
} X86PML4EBITS;
typedef union X86PML4E
X86PGPAEUINT u;
X86PML4EBITS n;
} X86PML4E;
typedef struct X86PML4
} X86PML4;
typedef struct X86FPUMMX
} X86FPUMMX;
typedef struct X86FPUSTATE
} X86FPUSTATE;
#pragma pack()
typedef struct X86FXSTATE
} X86FXSTATE;
#pragma pack()
typedef struct X86DESCATTRBITS
typedef union X86DESCATTR
uint32_t u;
} X86DESCATTR;
#pragma pack()
typedef struct X86DESCGENERIC
#pragma pack()
typedef struct X86DESCGATE
} X86DESCGATE;
typedef union X86DESC
} X86DESC;
#pragma pack()
typedef struct X86DESC64GENERIC
#pragma pack()
typedef struct X86DESC64SYSTEM
#pragma pack()
typedef struct X86DESC64GATE
typedef union X86DESC64
} X86DESC64;
#pragma pack()
#define X86_SEL_TYPE_RO 0
#define X86_SEL_TYPE_SYS_UNDEFINED 0
typedef struct X86TSS16
} X86TSS16;
#pragma pack()
typedef struct X86TSS32
} X86TSS32;
#pragma pack()
typedef struct X86TSS64
} X86TSS64;
#pragma pack()
* x86 Exceptions/Faults/Traps.
typedef enum X86XCPT
} X86XCPT;
typedef struct X86XDTR32
#pragma pack()
typedef struct X86XDTR64
#pragma pack()