hm_svm.h revision b7029d66bfed68ca24ca2dfb583df814391e9762
c97989161fbe75bc14cea477a5443bbf474dd3advboxsync * HM - SVM (AMD-V) Structures and Definitions. (VMM)
c97989161fbe75bc14cea477a5443bbf474dd3advboxsync * Copyright (C) 2006-2015 Oracle Corporation
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c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync/** @defgroup grp_svm SVM (AMD-V) Types and Definitions
739c77783387df1b22501b27bd870869a865d20cvboxsync * @ingroup grp_hm
739c77783387df1b22501b27bd870869a865d20cvboxsync/** @name SVM features for cpuid 0x8000000a
739c77783387df1b22501b27bd870869a865d20cvboxsync/** Bit 0 - NP - Nested Paging supported. */
739c77783387df1b22501b27bd870869a865d20cvboxsync#define AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
739c77783387df1b22501b27bd870869a865d20cvboxsync/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync#define AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync/** Bit 2 - SVML - SVM locking bit supported. */
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync#define AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync#define AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync#define AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync/** Bit 5 - VmcbClean - Support VMCB clean bits. */
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync#define AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync * VMCB.TLB_Control is supported. */
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync#define AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync/** Bit 7 - DecodeAssist - Indicate decode assist is supported. */
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync#define AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST RT_BIT(7)
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync#define AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync * intercept filter cycle count threshold. */
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync#define AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
c39e02bbf326184d8f70d4d6f4fbceb8ea5b6b97vboxsync/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
739c77783387df1b22501b27bd870869a865d20cvboxsync/** @name SVM Basic Exit Reasons.
739c77783387df1b22501b27bd870869a865d20cvboxsync/** Invalid guest state in VMCB. */
739c77783387df1b22501b27bd870869a865d20cvboxsync/** Read from CR0-CR15. */
/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault). */
/** The value of EFLAGS.RF that would be saved in the outgoing TSS if the task switch were not intercepted. */
/** @name SVMVMCB.ctrl.u32InterceptCtrl1
/** @name SVMVMCB.ctrl.u32InterceptCtrl2
/** @name SVMVMCB.ctrl.u64NestedPaging
/** @name SVMVMCB.ctrl.u64IntShadow
#define SVM_EVENT_EXTERNAL_IRQ 0
/** @name SVMVMCB.ctrl.TLBCtrl.n.u8TLBFlush
#define SVM_TLB_FLUSH_NOTHING 0
} SVMSEL;
} SVMGDTR;
uint64_t u;
} SVMEVENT;
uint64_t u;
} SVMINTCTRL;
uint64_t u;
} SVMTLBCTRL;
uint32_t u;
} SVMIOIOEXIT;
#define SVM_IOIO_WRITE 0
uint64_t u;
} SVMNPCTRL;
uint64_t u;
} SVMAVIC;
uint64_t u;
} SVMAVICPHYS;
typedef struct SVMVMCB
} ctrl;
} guest;
} SVMVMCB;
#ifdef IN_RING0