pci.h revision e1a2185b146905911611b6d7f84637dfab7d278d
af062818b47340eef15700d2f0211576ba3506eevboxsync * PCI - The PCI Controller And Devices. (DEV)
5112e32d7072e280613921c982a6672f2c859cf3vboxsync * Copyright (C) 2006-2007 Oracle Corporation
af062818b47340eef15700d2f0211576ba3506eevboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
af062818b47340eef15700d2f0211576ba3506eevboxsync * available from http://www.virtualbox.org. This file is free software;
af062818b47340eef15700d2f0211576ba3506eevboxsync * you can redistribute it and/or modify it under the terms of the GNU
af062818b47340eef15700d2f0211576ba3506eevboxsync * General Public License (GPL) as published by the Free Software
af062818b47340eef15700d2f0211576ba3506eevboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
af062818b47340eef15700d2f0211576ba3506eevboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
af062818b47340eef15700d2f0211576ba3506eevboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
af062818b47340eef15700d2f0211576ba3506eevboxsync * The contents of this file may alternatively be used under the terms
af062818b47340eef15700d2f0211576ba3506eevboxsync * of the Common Development and Distribution License Version 1.0
af062818b47340eef15700d2f0211576ba3506eevboxsync * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
af062818b47340eef15700d2f0211576ba3506eevboxsync * VirtualBox OSE distribution, in which case the provisions of the
af062818b47340eef15700d2f0211576ba3506eevboxsync * CDDL are applicable instead of those of the GPL.
af062818b47340eef15700d2f0211576ba3506eevboxsync * You may elect to license modified versions of this file under the
b955672b950093ff7416d1269dd4d3b69983bd8fvboxsync * terms and conditions of either the GPL or the CDDL or both.
af062818b47340eef15700d2f0211576ba3506eevboxsync/** @defgroup grp_pci PCI - The PCI Controller.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/** Pointer to a PCI device. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * PCI configuration word 4 (command) and word 6 (status).
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync /** Supports/uses memory accesses. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * PCI Address space specification.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * This is used when registering a I/O region.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/** Note: There are all sorts of dirty dependencies on the values in the
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * pci device. Be careful when changing this.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync /** Memory. */
fc50d11e45d83ecb4fbb2a6761d1adb5d6cc268fvboxsync /** I/O space. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync /** 32-bit BAR. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync /** 64-bit BAR. */
fc50d11e45d83ecb4fbb2a6761d1adb5d6cc268fvboxsync /** Prefetch memory. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * Callback function for mapping an PCI I/O region.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @return VBox status code.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @param iRegion The region number.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @param GCPhysAddress Physical address of the region. If enmType is PCI_ADDRESS_SPACE_IO, this
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * is an I/O port, otherwise it's a physical address.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * NIL_RTGCPHYS indicates that a MMIO2 mapping is about to be unmapped and
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * that the device deregister access handlers for it and update its internal
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * state to reflect this.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @param enmType One of the PCI_ADDRESS_SPACE_* values.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @remarks The address is *NOT* relative to pci_mem_base.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsynctypedef DECLCALLBACK(int) FNPCIIOREGIONMAP(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType);
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/** Pointer to a FNPCIIOREGIONMAP() function. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/** @name PCI Configuration Space Registers
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* Commented out values common for different header types */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* Common part of the header */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_COMMAND 0x04 /**< 16-bit RW, some bits RO */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_STATUS 0x06 /**< 16-bit RW, some bits RO */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_REVISION_ID 0x08 /**< 8-bit RO - - device revision */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CLASS_PROG 0x09 /**< 8-bit RO - - register-level programming class code (device specific). */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CLASS_SUB 0x0a /**< 8-bit RO - - sub-class code. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CLASS_BASE 0x0b /**< 8-bit RO - - base class code. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CACHE_LINE_SIZE 0x0c /**< 8-bit RW - - system cache line size */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_LATENCY_TIMER 0x0d /**< 8-bit RW - - master latency timer, hardwired to 0 for PCIe */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_HEADER_TYPE 0x0e /**< 8-bit RO - - header type (0 - device, 1 - bridge, 2 - CardBus bridge) */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_BIST 0x0f /**< 8-bit RW - - built-in self test control */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CAPABILITY_LIST 0x34 /**< 8-bit RO? - - linked list of new capabilities implemented by the device, 2 bottom bits reserved */
fc50d11e45d83ecb4fbb2a6761d1adb5d6cc268fvboxsync#define VBOX_PCI_INTERRUPT_LINE 0x3c /**< 8-bit RW - - interrupt line. */
fc50d11e45d83ecb4fbb2a6761d1adb5d6cc268fvboxsync#define VBOX_PCI_INTERRUPT_PIN 0x3d /**< 8-bit RO - - interrupt pin. */
fc50d11e45d83ecb4fbb2a6761d1adb5d6cc268fvboxsync/* Type 0 header, device */
fc50d11e45d83ecb4fbb2a6761d1adb5d6cc268fvboxsync#define VBOX_PCI_BASE_ADDRESS_0 0x10 /**< 32-bit RW */
fc50d11e45d83ecb4fbb2a6761d1adb5d6cc268fvboxsync#define VBOX_PCI_BASE_ADDRESS_1 0x14 /**< 32-bit RW */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_BASE_ADDRESS_2 0x18 /**< 32-bit RW */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_BASE_ADDRESS_3 0x1c /**< 32-bit RW */
fc50d11e45d83ecb4fbb2a6761d1adb5d6cc268fvboxsync#define VBOX_PCI_BASE_ADDRESS_4 0x20 /**< 32-bit RW */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_BASE_ADDRESS_5 0x24 /**< 32-bit RW */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_SUBSYSTEM_VENDOR_ID 0x2c /**< 16-bit RO */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_SUBSYSTEM_ID 0x2e /**< 16-bit RO */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_RESERVED_35 0x35 /**< 8-bit ?? - - reserved */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_RESERVED_36 0x36 /**< 8-bit ?? - - reserved */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_RESERVED_37 0x37 /**< 8-bit ?? - - reserved */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_RESERVED_38 0x38 /**< 32-bit ?? - - reserved */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_MIN_GNT 0x3e /**< 8-bit RO - - burst period length (in 1/4 microsecond units) */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_MAX_LAT 0x3f /**< 8-bit RO - - how often the device needs access to the PCI bus (in 1/4 microsecond units) */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* Type 1 header, PCI-to-PCI bridge */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* #define VBOX_PCI_BASE_ADDRESS_0 0x10 */ /**< 32-bit RW */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* #define VBOX_PCI_BASE_ADDRESS_1 0x14 */ /**< 32-bit RW */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_PRIMARY_BUS 0x18 /**< 8-bit ?? - - primary bus number. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_SECONDARY_BUS 0x19 /**< 8-bit ?? - - secondary bus number. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_SUBORDINATE_BUS 0x1a /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_SEC_LATENCY_TIMER 0x1b /**< 8-bit ?? - - secondary latency timer. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_IO_BASE 0x1c /**< 8-bit ?? - - I/O range base. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_IO_LIMIT 0x1d /**< 8-bit ?? - - I/O range limit. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_SEC_STATUS 0x1e /**< 16-bit ?? - - secondary status register. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_MEMORY_BASE 0x20 /**< 16-bit ?? - - memory range base. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_MEMORY_LIMIT 0x22 /**< 16-bit ?? - - memory range limit. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_PREF_MEMORY_BASE 0x24 /**< 16-bit ?? - - prefetchable memory range base. */
3c5c04d7b0973be0757addef8ba44b9352b38386vboxsync#define VBOX_PCI_PREF_MEMORY_LIMIT 0x26 /**< 16-bit ?? - - prefetchable memory range limit. */
3c5c04d7b0973be0757addef8ba44b9352b38386vboxsync#define VBOX_PCI_PREF_BASE_UPPER32 0x28 /**< 32-bit ?? - - prefetchable memory range high base.*/
3c5c04d7b0973be0757addef8ba44b9352b38386vboxsync#define VBOX_PCI_PREF_LIMIT_UPPER32 0x2c /**< 32-bit ?? - - prefetchable memory range high limit. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_IO_BASE_UPPER16 0x30 /**< 16-bit ?? - - memory range high base. */
3c5c04d7b0973be0757addef8ba44b9352b38386vboxsync#define VBOX_PCI_IO_LIMIT_UPPER16 0x32 /**< 16-bit ?? - - memory range high limit. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* #define VBOX_PCI_RESERVED_35 0x35 */ /**< 8-bit ?? - - reserved */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* #define VBOX_PCI_RESERVED_36 0x36 */ /**< 8-bit ?? - - reserved */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* #define VBOX_PCI_RESERVED_37 0x37 */ /**< 8-bit ?? - - reserved */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_ROM_ADDRESS_BR 0x38 /**< 32-bit ?? - - expansion ROM base address */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_BRIDGE_CONTROL 0x3e /**< 16-bit? ?? - - bridge control */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* Type 2 header, PCI-to-CardBus bridge */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CARDBUS_BASE_ADDRESS 0x10 /**< 32-bit RW - - CardBus Socket/ExCa base address */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CARDBUS_CAPLIST 0x14 /**< 8-bit RO? - - offset of capabilities list */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CARDBUS_RESERVED_15 0x15 /**< 8-bit ?? - - reserved */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CARDBUS_SEC_STATUS 0x16 /**< 16-bit ?? - - secondary status */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CARDBUS_PCIBUS_NUMBER 0x18 /**< 8-bit ?? - - PCI bus number */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CARDBUS_CARDBUS_NUMBER 0x19 /**< 8-bit ?? - - CardBus bus number */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* #define VBOX_PCI_SUBORDINATE_BUS 0x1a */ /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* #define VBOX_PCI_SEC_LATENCY_TIMER 0x1b */ /**< 8-bit ?? - - secondary latency timer. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CARDBUS_MEMORY_BASE0 0x1c /**< 32-bit RW - - memory base address 0 */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CARDBUS_MEMORY_LIMIT0 0x20 /**< 32-bit RW - - memory limit 0 */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CARDBUS_MEMORY_BASE1 0x24 /**< 32-bit RW - - memory base address 1 */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CARDBUS_MEMORY_LIMIT1 0x28 /**< 32-bit RW - - memory limit 1 */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CARDBUS_IO_BASE0 0x2c /**< 32-bit RW - - IO base address 0 */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CARDBUS_IO_LIMIT0 0x30 /**< 32-bit RW - - IO limit 0 */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CARDBUS_IO_BASE1 0x34 /**< 32-bit RW - - IO base address 1 */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CARDBUS_IO_LIMIT1 0x38 /**< 32-bit RW - - IO limit 1 */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* #define VBOX_PCI_BRIDGE_CONTROL 0x3e */ /**< 16-bit? ?? - - bridge control */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* Possible values in status bitmask */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_STATUS_PARITY 0x100 /* Detected parity error */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* Command bitmask */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
3c5c04d7b0973be0757addef8ba44b9352b38386vboxsync#define VBOX_PCI_COMMAND_SERR 0x100 /* Enable SERR */
3c5c04d7b0973be0757addef8ba44b9352b38386vboxsync#define VBOX_PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
3c5c04d7b0973be0757addef8ba44b9352b38386vboxsync#define VBOX_PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* Capability list values (capability offset 0) */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* Next value pointer in offset 1, or 0 if none */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CAP_ID_PM 0x01 /* Power Management */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CAP_ID_HT 0x08 /* HyperTransport */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CAP_ID_SATA 0x12 /* Serial-ATA HBA */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* Extended Capabilities (PCI-X 2.0 and Express), start at 0x100, next - bits [20..32] */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* MSI flags, aka Message Control (2 bytes, capability offset 2) */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking support */
af062818b47340eef15700d2f0211576ba3506eevboxsync/* Encoding for 3-bit patterns for message queue (per chapter 6.8.1 of PCI spec),
af062818b47340eef15700d2f0211576ba3506eevboxsync someone very similar to log_2().
af062818b47340eef15700d2f0211576ba3506eevboxsync 110 Reserved
af062818b47340eef15700d2f0211576ba3506eevboxsync 111 Reserved */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured (i.e. vectors per device allocated) */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available (i.e. vectors per device possible) */
af062818b47340eef15700d2f0211576ba3506eevboxsync/* MSI-X flags (2 bytes, capability offset 2) */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_MSIX_FLAGS_FUNCMASK 0x4000 /* Function mask */
af062818b47340eef15700d2f0211576ba3506eevboxsync/* Power management flags (2 bytes, capability offset 2) */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_PM_CAP_VER_MASK 0x0007 /* Version mask */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_PM_CAP_D1 0x0200 /* D1 power state support */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_PM_CAP_D2 0x0400 /* D2 power state support */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_PM_CAP_PME 0x0800 /* PME pin supported */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync/* Power management control flags (2 bytes, capability offset 4) */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
040b4a09341f574825386333398110f4db3e1e51vboxsync#define VBOX_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
040b4a09341f574825386333398110f4db3e1e51vboxsync#define VBOX_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync#define VBOX_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
040b4a09341f574825386333398110f4db3e1e51vboxsync/* PCI-X config flags (2 bytes, capability offset 2) */
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync#define VBOX_PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
040b4a09341f574825386333398110f4db3e1e51vboxsync#define VBOX_PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync#define VBOX_PCI_X_CMD_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
040b4a09341f574825386333398110f4db3e1e51vboxsync#define VBOX_PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync#define VBOX_PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
af062818b47340eef15700d2f0211576ba3506eevboxsync/* PCI-X config flags (4 bytes, capability offset 4) */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
5112e32d7072e280613921c982a6672f2c859cf3vboxsync#define VBOX_PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity, 0 = simple device, 1 = bridge device */
5112e32d7072e280613921c982a6672f2c859cf3vboxsync#define VBOX_PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count, 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
5112e32d7072e280613921c982a6672f2c859cf3vboxsync#define VBOX_PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
5112e32d7072e280613921c982a6672f2c859cf3vboxsync#define VBOX_PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
5112e32d7072e280613921c982a6672f2c859cf3vboxsync/* PCI Express config flags (2 bytes, capability offset 2) */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync#define VBOX_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
5112e32d7072e280613921c982a6672f2c859cf3vboxsync#define VBOX_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
5112e32d7072e280613921c982a6672f2c859cf3vboxsync#define VBOX_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
5112e32d7072e280613921c982a6672f2c859cf3vboxsync#define VBOX_PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_TYPE_ROOT_INT_EP 0x9 /* Root Complex Integrated Endpoint */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
af062818b47340eef15700d2f0211576ba3506eevboxsync/* PCI Express device capabilities (4 bytes, capability offset 4) */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync#define VBOX_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync#define VBOX_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */
af062818b47340eef15700d2f0211576ba3506eevboxsync/* PCI Express device control (2 bytes, capability offset 8) */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
5112e32d7072e280613921c982a6672f2c859cf3vboxsync#define VBOX_PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync#define VBOX_PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit shared with BCRE] */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync/* PCI Express device status (2 bytes, capability offset 10) */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
5112e32d7072e280613921c982a6672f2c859cf3vboxsync#define VBOX_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
040b4a09341f574825386333398110f4db3e1e51vboxsync#define VBOX_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync/* PCI Express link capabilities (4 bytes, capability offset 12) */
040b4a09341f574825386333398110f4db3e1e51vboxsync#define VBOX_PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync#define VBOX_PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */
040b4a09341f574825386333398110f4db3e1e51vboxsync#define VBOX_PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync/* PCI Express link control (2 bytes, capability offset 16) */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */
589fd26cedb2b4ebbed14f2964cad03cc8ebbca2vboxsync#define VBOX_PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */
5112e32d7072e280613921c982a6672f2c859cf3vboxsync#define VBOX_PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */
af062818b47340eef15700d2f0211576ba3506eevboxsync/* PCI Express link status (2 bytes, capability offset 18) */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync#define VBOX_PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */
5112e32d7072e280613921c982a6672f2c859cf3vboxsync#define VBOX_PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active State */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */
040b4a09341f574825386333398110f4db3e1e51vboxsync#define VBOX_PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status */
af062818b47340eef15700d2f0211576ba3506eevboxsync/* PCI Express slot capabilities (4 bytes, capability offset 20) */
040b4a09341f574825386333398110f4db3e1e51vboxsync#define VBOX_PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */
a3133ef29cdf3656735d569fd64e54c9286effc0vboxsync#define VBOX_PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */
a3133ef29cdf3656735d569fd64e54c9286effc0vboxsync#define VBOX_PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */
a3133ef29cdf3656735d569fd64e54c9286effc0vboxsync#define VBOX_PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */
a3133ef29cdf3656735d569fd64e54c9286effc0vboxsync#define VBOX_PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
a3133ef29cdf3656735d569fd64e54c9286effc0vboxsync#define VBOX_PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
040b4a09341f574825386333398110f4db3e1e51vboxsync#define VBOX_PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* PCI Express slot control (2 bytes, capability offset 24) */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */
040b4a09341f574825386333398110f4db3e1e51vboxsync#define VBOX_PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */
040b4a09341f574825386333398110f4db3e1e51vboxsync#define VBOX_PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
040b4a09341f574825386333398110f4db3e1e51vboxsync#define VBOX_PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Enable */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync/* PCI Express slot status (2 bytes, capability offset 26) */
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync#define VBOX_PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */
af062818b47340eef15700d2f0211576ba3506eevboxsync/* PCI Express root control (2 bytes, capability offset 28) */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
af062818b47340eef15700d2f0211576ba3506eevboxsync/* PCI Express root capabilities (2 bytes, capability offset 30) */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
af062818b47340eef15700d2f0211576ba3506eevboxsync/* PCI Express root status (4 bytes, capability offset 32) */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
af062818b47340eef15700d2f0211576ba3506eevboxsync#define VBOX_PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
040b4a09341f574825386333398110f4db3e1e51vboxsync * Callback function for reading from the PCI configuration space.
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync * @returns The register value.
040b4a09341f574825386333398110f4db3e1e51vboxsync * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @param Address The configuration space register address. [0..4096]
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @param cb The register size. [1,2,4]
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsynctypedef DECLCALLBACK(uint32_t) FNPCICONFIGREAD(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb);
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync/** Pointer to a FNPCICONFIGREAD() function. */
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync/** Pointer to a PFNPCICONFIGREAD. */
af062818b47340eef15700d2f0211576ba3506eevboxsync * Callback function for writing to the PCI configuration space.
af062818b47340eef15700d2f0211576ba3506eevboxsync * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
af062818b47340eef15700d2f0211576ba3506eevboxsync * @param Address The configuration space register address. [0..4096]
af062818b47340eef15700d2f0211576ba3506eevboxsync * @param u32Value The value that's being written. The number of bits actually used from
af062818b47340eef15700d2f0211576ba3506eevboxsync * this value is determined by the cb parameter.
af062818b47340eef15700d2f0211576ba3506eevboxsync * @param cb The register size. [1,2,4]
af062818b47340eef15700d2f0211576ba3506eevboxsynctypedef DECLCALLBACK(void) FNPCICONFIGWRITE(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb);
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a FNPCICONFIGWRITE() function. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Pointer to a PFNPCICONFIGWRITE. */
af062818b47340eef15700d2f0211576ba3506eevboxsync/** Fixed I/O region number for ROM. */
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync/** Max number of I/O regions. */
040b4a09341f574825386333398110f4db3e1e51vboxsync * Hack to include the PCIDEVICEINT structure at the right place
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync * to avoid duplications of FNPCIIOREGIONMAP and PCI_NUM_REGIONS.
5112e32d7072e280613921c982a6672f2c859cf3vboxsync * PCI Device structure.
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsynctypedef struct PCIDevice
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync /** PCI config space. */
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync /** Internal data. */
5112e32d7072e280613921c982a6672f2c859cf3vboxsync /** Read only data.
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync /** PCI device number on the pci bus. */
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync /** Device name. */
5112e32d7072e280613921c982a6672f2c859cf3vboxsync /** Pointer to the device instance which registered the device. */
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync/* @todo: handle extended space access */
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsyncDECLINLINE(void) PCIDevSetByte(PPCIDEVICE pPciDev, uint32_t uOffset, uint8_t u8Value)
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsyncDECLINLINE(uint8_t) PCIDevGetByte(PPCIDEVICE pPciDev, uint32_t uOffset)
5112e32d7072e280613921c982a6672f2c859cf3vboxsyncDECLINLINE(void) PCIDevSetWord(PPCIDEVICE pPciDev, uint32_t uOffset, uint16_t u16Value)
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsync *(uint16_t*)&pPciDev->config[uOffset] = RT_H2LE_U16(u16Value);
114410893548b9522c46fdcbd8f63385eb8bfb68vboxsyncDECLINLINE(uint16_t) PCIDevGetWord(PPCIDEVICE pPciDev, uint32_t uOffset)
5112e32d7072e280613921c982a6672f2c859cf3vboxsync uint16_t u16Value = *(uint16_t*)&pPciDev->config[uOffset];
af062818b47340eef15700d2f0211576ba3506eevboxsyncDECLINLINE(void) PCIDevSetDWord(PPCIDEVICE pPciDev, uint32_t uOffset, uint32_t u32Value)
af062818b47340eef15700d2f0211576ba3506eevboxsync *(uint32_t*)&pPciDev->config[uOffset] = RT_H2LE_U32(u32Value);
af062818b47340eef15700d2f0211576ba3506eevboxsyncDECLINLINE(uint32_t) PCIDevGetDWord(PPCIDEVICE pPciDev, uint32_t uOffset)
af062818b47340eef15700d2f0211576ba3506eevboxsync uint32_t u32Value = *(uint32_t*)&pPciDev->config[uOffset];
af062818b47340eef15700d2f0211576ba3506eevboxsyncDECLINLINE(void) PCIDevSetQWord(PPCIDEVICE pPciDev, uint32_t uOffset, uint64_t u64Value)
af062818b47340eef15700d2f0211576ba3506eevboxsync *(uint64_t*)&pPciDev->config[uOffset] = RT_H2LE_U64(u64Value);
af062818b47340eef15700d2f0211576ba3506eevboxsyncDECLINLINE(uint64_t) PCIDevGetQWord(PPCIDEVICE pPciDev, uint32_t uOffset)
af062818b47340eef15700d2f0211576ba3506eevboxsync uint64_t u64Value = *(uint64_t*)&pPciDev->config[uOffset];
af062818b47340eef15700d2f0211576ba3506eevboxsync * Sets the vendor id config register.
af062818b47340eef15700d2f0211576ba3506eevboxsync * @param pPciDev The PCI device.
af062818b47340eef15700d2f0211576ba3506eevboxsync * @param u16VendorId The vendor id.
af062818b47340eef15700d2f0211576ba3506eevboxsyncDECLINLINE(void) PCIDevSetVendorId(PPCIDEVICE pPciDev, uint16_t u16VendorId)
af062818b47340eef15700d2f0211576ba3506eevboxsync PCIDevSetWord(pPciDev, VBOX_PCI_VENDOR_ID, u16VendorId);
af062818b47340eef15700d2f0211576ba3506eevboxsync * Gets the vendor id config register.
af062818b47340eef15700d2f0211576ba3506eevboxsync * @returns the vendor id.
af062818b47340eef15700d2f0211576ba3506eevboxsync * @param pPciDev The PCI device.
af062818b47340eef15700d2f0211576ba3506eevboxsyncDECLINLINE(uint16_t) PCIDevGetVendorId(PPCIDEVICE pPciDev)
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * Sets the device id config register.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @param pPciDev The PCI device.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @param u16DeviceId The device id.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsyncDECLINLINE(void) PCIDevSetDeviceId(PPCIDEVICE pPciDev, uint16_t u16DeviceId)
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync PCIDevSetWord(pPciDev, VBOX_PCI_DEVICE_ID, u16DeviceId);
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * Gets the device id config register.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @returns the device id.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @param pPciDev The PCI device.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsyncDECLINLINE(uint16_t) PCIDevGetDeviceId(PPCIDEVICE pPciDev)
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * Sets the command config register.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @param pPciDev The PCI device.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @param u16Command The command register value.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsyncDECLINLINE(void) PCIDevSetCommand(PPCIDEVICE pPciDev, uint16_t u16Command)
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync PCIDevSetWord(pPciDev, VBOX_PCI_COMMAND, u16Command);
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * Gets the command config register.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @returns The command register value.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @param pPciDev The PCI device.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsyncDECLINLINE(uint16_t) PCIDevGetCommand(PPCIDEVICE pPciDev)
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * Checks if INTx interrupts disabled in the command config register.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @returns true if disabled.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @param pPciDev The PCI device.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsyncDECLINLINE(bool) PCIDevIsIntxDisabled(PPCIDEVICE pPciDev)
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync return (PCIDevGetCommand(pPciDev) & VBOX_PCI_COMMAND_INTX_DISABLE) != 0;
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * Gets the status config register.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @returns status config register.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * @param pPciDev The PCI device.
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsyncDECLINLINE(uint16_t) PCIDevGetStatus(PPCIDEVICE pPciDev)
ee6bcfc59fe3b0230aad85e2ef63d0402b7719b2vboxsync * Sets the status config register.
* @param f64Bit Whether the memory can be mapped anywhere in the 64-bit address space. Otherwise restrict to 32-bit.
DECLINLINE(void) PCIDevSetBaseAddress(PPCIDEVICE pPciDev, uint8_t iReg, bool fIOSpace, bool fPrefetchable, bool f64Bit, uint32_t u32Addr)
if (fIOSpace)
if (fPrefetchable)
if (f64Bit)
switch (iReg)
default: AssertFailedReturnVoid();
#ifdef PCIDEVICEINT_DECLARED