pci.h revision 56d3c9238bc5578f5f9ced79ae9432783e0b7a63
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * PCI - The PCI Controller And Devices. (DEV)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Copyright (C) 2006-2007 Oracle Corporation
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * available from http://www.virtualbox.org. This file is free software;
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * you can redistribute it and/or modify it under the terms of the GNU
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * General Public License (GPL) as published by the Free Software
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * The contents of this file may alternatively be used under the terms
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * of the Common Development and Distribution License Version 1.0
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * VirtualBox OSE distribution, in which case the provisions of the
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * CDDL are applicable instead of those of the GPL.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * You may elect to license modified versions of this file under the
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * terms and conditions of either the GPL or the CDDL or both.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/** @defgroup grp_pci PCI - The PCI Controller.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/** Pointer to a PCI device. */
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync * PCI configuration word 4 (command) and word 6 (status).
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync /** Supports/uses memory accesses. */
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync * PCI Address space specification.
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync * This is used when registering a I/O region.
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync/** Note: There are all sorts of dirty dependencies on the values in the
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync * pci device. Be careful when changing this.
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync /** Memory. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync /** I/O space. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync /** 32-bit BAR. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync /** 64-bit BAR. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync /** Prefetch memory. */
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync * Callback function for mapping an PCI I/O region.
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync * @return VBox status code.
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync * @param iRegion The region number.
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync * @param GCPhysAddress Physical address of the region. If enmType is PCI_ADDRESS_SPACE_IO, this
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync * is an I/O port, otherwise it's a physical address.
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync * NIL_RTGCPHYS indicates that a MMIO2 mapping is about to be unmapped and
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync * that the device deregister access handlers for it and update its internal
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync * state to reflect this.
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync * @param enmType One of the PCI_ADDRESS_SPACE_* values.
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync * @remarks The address is *NOT* relative to pci_mem_base.
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsynctypedef DECLCALLBACK(int) FNPCIIOREGIONMAP(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType);
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync/** Pointer to a FNPCIIOREGIONMAP() function. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/** @name PCI Configuration Space Registers
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* Commented out values common for different header types */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* Common part of the header */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_COMMAND 0x04 /**< 16-bit RW, some bits RO */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_STATUS 0x06 /**< 16-bit RW, some bits RO */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_REVISION_ID 0x08 /**< 8-bit RO - - device revision */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CLASS_PROG 0x09 /**< 8-bit RO - - register-level programming class code (device specific). */
ffb50166c9adb4ae583b914d405197035cf890advboxsync#define VBOX_PCI_CLASS_SUB 0x0a /**< 8-bit RO - - sub-class code. */
ffb50166c9adb4ae583b914d405197035cf890advboxsync#define VBOX_PCI_CLASS_BASE 0x0b /**< 8-bit RO - - base class code. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CACHE_LINE_SIZE 0x0c /**< 8-bit RW - - system cache line size */
ffb50166c9adb4ae583b914d405197035cf890advboxsync#define VBOX_PCI_LATENCY_TIMER 0x0d /**< 8-bit RW - - master latency timer, hardwired to 0 for PCIe */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_HEADER_TYPE 0x0e /**< 8-bit RO - - header type (0 - device, 1 - bridge, 2 - CardBus bridge) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_BIST 0x0f /**< 8-bit RW - - built-in self test control */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CAPABILITY_LIST 0x34 /**< 8-bit RO? - - linked list of new capabilities implemented by the device, 2 bottom bits reserved */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_INTERRUPT_LINE 0x3c /**< 8-bit RW - - interrupt line. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_INTERRUPT_PIN 0x3d /**< 8-bit RO - - interrupt pin. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* Type 0 header, device */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_BASE_ADDRESS_0 0x10 /**< 32-bit RW */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_BASE_ADDRESS_1 0x14 /**< 32-bit RW */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_BASE_ADDRESS_2 0x18 /**< 32-bit RW */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_BASE_ADDRESS_3 0x1c /**< 32-bit RW */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_BASE_ADDRESS_4 0x20 /**< 32-bit RW */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_BASE_ADDRESS_5 0x24 /**< 32-bit RW */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_SUBSYSTEM_VENDOR_ID 0x2c /**< 16-bit RO */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_SUBSYSTEM_ID 0x2e /**< 16-bit RO */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_RESERVED_35 0x35 /**< 8-bit ?? - - reserved */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_RESERVED_36 0x36 /**< 8-bit ?? - - reserved */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_RESERVED_37 0x37 /**< 8-bit ?? - - reserved */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_RESERVED_38 0x38 /**< 32-bit ?? - - reserved */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_MIN_GNT 0x3e /**< 8-bit RO - - burst period length (in 1/4 microsecond units) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_MAX_LAT 0x3f /**< 8-bit RO - - how often the device needs access to the PCI bus (in 1/4 microsecond units) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* Type 1 header, PCI-to-PCI bridge */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* #define VBOX_PCI_BASE_ADDRESS_0 0x10 */ /**< 32-bit RW */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* #define VBOX_PCI_BASE_ADDRESS_1 0x14 */ /**< 32-bit RW */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PRIMARY_BUS 0x18 /**< 8-bit ?? - - primary bus number. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_SECONDARY_BUS 0x19 /**< 8-bit ?? - - secondary bus number. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_SUBORDINATE_BUS 0x1a /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_SEC_LATENCY_TIMER 0x1b /**< 8-bit ?? - - secondary latency timer. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_IO_BASE 0x1c /**< 8-bit ?? - - I/O range base. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_IO_LIMIT 0x1d /**< 8-bit ?? - - I/O range limit. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_SEC_STATUS 0x1e /**< 16-bit ?? - - secondary status register. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_MEMORY_BASE 0x20 /**< 16-bit ?? - - memory range base. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_MEMORY_LIMIT 0x22 /**< 16-bit ?? - - memory range limit. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PREF_MEMORY_BASE 0x24 /**< 16-bit ?? - - prefetchable memory range base. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PREF_MEMORY_LIMIT 0x26 /**< 16-bit ?? - - prefetchable memory range limit. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PREF_BASE_UPPER32 0x28 /**< 32-bit ?? - - prefetchable memory range high base.*/
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PREF_LIMIT_UPPER32 0x2c /**< 32-bit ?? - - prefetchable memory range high limit. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_IO_BASE_UPPER16 0x30 /**< 16-bit ?? - - memory range high base. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_IO_LIMIT_UPPER16 0x32 /**< 16-bit ?? - - memory range high limit. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* #define VBOX_PCI_RESERVED_35 0x35 */ /**< 8-bit ?? - - reserved */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* #define VBOX_PCI_RESERVED_36 0x36 */ /**< 8-bit ?? - - reserved */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* #define VBOX_PCI_RESERVED_37 0x37 */ /**< 8-bit ?? - - reserved */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_ROM_ADDRESS_BR 0x38 /**< 32-bit ?? - - expansion ROM base address */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_BRIDGE_CONTROL 0x3e /**< 16-bit? ?? - - bridge control */
11b175175a0ed424b8e8354acda681ad0adde0f8vboxsync/* Type 2 header, PCI-to-CardBus bridge */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CARDBUS_BASE_ADDRESS 0x10 /**< 32-bit RW - - CardBus Socket/ExCa base address */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CARDBUS_CAPLIST 0x14 /**< 8-bit RO? - - offset of capabilities list */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CARDBUS_RESERVED_15 0x15 /**< 8-bit ?? - - reserved */
11b175175a0ed424b8e8354acda681ad0adde0f8vboxsync#define VBOX_PCI_CARDBUS_SEC_STATUS 0x16 /**< 16-bit ?? - - secondary status */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CARDBUS_PCIBUS_NUMBER 0x18 /**< 8-bit ?? - - PCI bus number */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CARDBUS_CARDBUS_NUMBER 0x19 /**< 8-bit ?? - - CardBus bus number */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* #define VBOX_PCI_SUBORDINATE_BUS 0x1a */ /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* #define VBOX_PCI_SEC_LATENCY_TIMER 0x1b */ /**< 8-bit ?? - - secondary latency timer. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CARDBUS_MEMORY_BASE0 0x1c /**< 32-bit RW - - memory base address 0 */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CARDBUS_MEMORY_LIMIT0 0x20 /**< 32-bit RW - - memory limit 0 */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CARDBUS_MEMORY_BASE1 0x24 /**< 32-bit RW - - memory base address 1 */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CARDBUS_MEMORY_LIMIT1 0x28 /**< 32-bit RW - - memory limit 1 */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CARDBUS_IO_BASE0 0x2c /**< 32-bit RW - - IO base address 0 */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CARDBUS_IO_LIMIT0 0x30 /**< 32-bit RW - - IO limit 0 */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CARDBUS_IO_BASE1 0x34 /**< 32-bit RW - - IO base address 1 */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CARDBUS_IO_LIMIT1 0x38 /**< 32-bit RW - - IO limit 1 */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* #define VBOX_PCI_BRIDGE_CONTROL 0x3e */ /**< 16-bit? ?? - - bridge control */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* Possible values in status bitmask */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_STATUS_PARITY 0x100 /* Detected parity error */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* Command bitmask */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_COMMAND_SERR 0x100 /* Enable SERR */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* Capability list values (capability offset 0) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* Next value pointer in offset 1, or 0 if none */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CAP_ID_PM 0x01 /* Power Management */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CAP_ID_HT 0x08 /* HyperTransport */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CAP_ID_SATA 0x12 /* Serial-ATA HBA */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* Extended Capabilities (PCI-X 2.0 and Express), start at 0x100, next - bits [20..32] */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* MSI flags, aka Message Control (2 bytes, capability offset 2) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking support */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* Encoding for 3-bit patterns for message queue (per chapter 6.8.1 of PCI spec),
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync someone very similar to log_2().
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync 110 Reserved
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync 111 Reserved */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured (i.e. vectors per device allocated) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available (i.e. vectors per device possible) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* MSI-X flags (2 bytes, capability offset 2) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_MSIX_FLAGS_FUNCMASK 0x4000 /* Function mask */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* Power management flags (2 bytes, capability offset 2) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CAP_VER_MASK 0x0007 /* Version mask */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CAP_D1 0x0200 /* D1 power state support */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CAP_D2 0x0400 /* D2 power state support */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CAP_PME 0x0800 /* PME pin supported */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* Power management control flags (2 bytes, capability offset 4) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* PCI-X config flags (2 bytes, capability offset 2) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_CMD_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* PCI-X config flags (4 bytes, capability offset 4) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity, 0 = simple device, 1 = bridge device */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count, 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* PCI Express config flags (2 bytes, capability offset 2) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_TYPE_ROOT_INT_EP 0x9 /* Root Complex Integrated Endpoint */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* PCI Express device capabilities (4 bytes, capability offset 4) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* PCI Express device control (2 bytes, capability offset 8) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit shared with BCRE] */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* PCI Express device status (2 bytes, capability offset 10) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* PCI Express link capabilities (4 bytes, capability offset 12) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* PCI Express link control (2 bytes, capability offset 16) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* PCI Express link status (2 bytes, capability offset 18) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active State */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* PCI Express slot capabilities (4 bytes, capability offset 20) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* PCI Express slot control (2 bytes, capability offset 24) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* PCI Express slot status (2 bytes, capability offset 26) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync#define VBOX_PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync#define VBOX_PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* PCI Express root control (2 bytes, capability offset 28) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* PCI Express root capabilities (2 bytes, capability offset 30) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* PCI Express root status (4 bytes, capability offset 32) */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync#define VBOX_PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Callback function for reading from the PCI configuration space.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @returns The register value.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param Address The configuration space register address. [0..4096]
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param cb The register size. [1,2,4]
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsynctypedef DECLCALLBACK(uint32_t) FNPCICONFIGREAD(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/** Pointer to a FNPCICONFIGREAD() function. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/** Pointer to a PFNPCICONFIGREAD. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Callback function for writing to the PCI configuration space.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param Address The configuration space register address. [0..4096]
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param u32Value The value that's being written. The number of bits actually used from
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * this value is determined by the cb parameter.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param cb The register size. [1,2,4]
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsynctypedef DECLCALLBACK(void) FNPCICONFIGWRITE(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/** Pointer to a FNPCICONFIGWRITE() function. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/** Pointer to a PFNPCICONFIGWRITE. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/** Fixed I/O region number for ROM. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/** Max number of I/O regions. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Hack to include the PCIDEVICEINT structure at the right place
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * to avoid duplications of FNPCIIOREGIONMAP and PCI_NUM_REGIONS.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * PCI Device structure.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsynctypedef struct PCIDevice
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync /** PCI config space. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync /** Internal data. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync /** Read only data.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync /** PCI device number on the pci bus. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync /** Device name. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync /** Pointer to the device instance which registered the device. */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync/* @todo: handle extended space access */
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetByte(PPCIDEVICE pPciDev, uint32_t uOffset, uint8_t u8Value)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(uint8_t) PCIDevGetByte(PPCIDEVICE pPciDev, uint32_t uOffset)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetWord(PPCIDEVICE pPciDev, uint32_t uOffset, uint16_t u16Value)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync *(uint16_t*)&pPciDev->config[uOffset] = RT_H2LE_U16(u16Value);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(uint16_t) PCIDevGetWord(PPCIDEVICE pPciDev, uint32_t uOffset)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uint16_t u16Value = *(uint16_t*)&pPciDev->config[uOffset];
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetDWord(PPCIDEVICE pPciDev, uint32_t uOffset, uint32_t u32Value)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync *(uint32_t*)&pPciDev->config[uOffset] = RT_H2LE_U32(u32Value);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(uint32_t) PCIDevGetDWord(PPCIDEVICE pPciDev, uint32_t uOffset)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uint32_t u32Value = *(uint32_t*)&pPciDev->config[uOffset];
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetQWord(PPCIDEVICE pPciDev, uint32_t uOffset, uint64_t u64Value)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync *(uint64_t*)&pPciDev->config[uOffset] = RT_H2LE_U64(u64Value);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(uint64_t) PCIDevGetQWord(PPCIDEVICE pPciDev, uint32_t uOffset)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uint64_t u64Value = *(uint64_t*)&pPciDev->config[uOffset];
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Sets the vendor id config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param u16VendorId The vendor id.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetVendorId(PPCIDEVICE pPciDev, uint16_t u16VendorId)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync PCIDevSetWord(pPciDev, VBOX_PCI_VENDOR_ID, u16VendorId);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Gets the vendor id config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @returns the vendor id.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(uint16_t) PCIDevGetVendorId(PPCIDEVICE pPciDev)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Sets the device id config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param u16DeviceId The device id.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetDeviceId(PPCIDEVICE pPciDev, uint16_t u16DeviceId)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync PCIDevSetWord(pPciDev, VBOX_PCI_DEVICE_ID, u16DeviceId);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Gets the device id config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @returns the device id.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(uint16_t) PCIDevGetDeviceId(PPCIDEVICE pPciDev)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Sets the command config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param u16Command The command register value.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetCommand(PPCIDEVICE pPciDev, uint16_t u16Command)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync PCIDevSetWord(pPciDev, VBOX_PCI_COMMAND, u16Command);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Gets the command config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @returns The command register value.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(uint16_t) PCIDevGetCommand(PPCIDEVICE pPciDev)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Checks if INTx interrupts disabled in the command config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @returns true if disabled.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(bool) PCIDevIsIntxDisabled(PPCIDEVICE pPciDev)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return (PCIDevGetCommand(pPciDev) & VBOX_PCI_COMMAND_INTX_DISABLE) != 0;
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Gets the status config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @returns status config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(uint16_t) PCIDevGetStatus(PPCIDEVICE pPciDev)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Sets the status config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param u16Status The status register value.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetStatus(PPCIDEVICE pPciDev, uint16_t u16Status)
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync PCIDevSetWord(pPciDev, VBOX_PCI_STATUS, u16Status);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Sets the revision id config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param u8RevisionId The revision id.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetRevisionId(PPCIDEVICE pPciDev, uint8_t u8RevisionId)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync PCIDevSetByte(pPciDev, VBOX_PCI_REVISION_ID, u8RevisionId);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Sets the register level programming class config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param u8ClassProg The new value.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetClassProg(PPCIDEVICE pPciDev, uint8_t u8ClassProg)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_PROG, u8ClassProg);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Sets the sub-class (aka device class) config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param u8SubClass The sub-class.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetClassSub(PPCIDEVICE pPciDev, uint8_t u8SubClass)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_SUB, u8SubClass);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Sets the base class config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param u8BaseClass The base class.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetClassBase(PPCIDEVICE pPciDev, uint8_t u8BaseClass)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_BASE, u8BaseClass);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Sets the header type config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param u8HdrType The header type.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetHeaderType(PPCIDEVICE pPciDev, uint8_t u8HdrType)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync PCIDevSetByte(pPciDev, VBOX_PCI_HEADER_TYPE, u8HdrType);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Gets the header type config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @returns u8HdrType The header type.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(uint8_t) PCIDevGetHeaderType(PPCIDEVICE pPciDev)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return PCIDevGetByte(pPciDev, VBOX_PCI_HEADER_TYPE);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Sets the BIST (built-in self-test) config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
ffb50166c9adb4ae583b914d405197035cf890advboxsync * @param u8Bist The BIST value.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetBIST(PPCIDEVICE pPciDev, uint8_t u8Bist)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Gets the BIST (built-in self-test) config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @returns u8Bist The BIST.
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncDECLINLINE(uint8_t) PCIDevGetBIST(PPCIDEVICE pPciDev)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Sets a base address config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param fIOSpace Whether it's I/O (true) or memory (false) space.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param fPrefetchable Whether the memory is prefetachable. Must be false if fIOSpace == true.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param f64Bit Whether the memory can be mapped anywhere in the 64-bit address space. Otherwise restrict to 32-bit.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param u32Addr The address value.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetBaseAddress(PPCIDEVICE pPciDev, uint8_t iReg, bool fIOSpace, bool fPrefetchable, bool f64Bit, uint32_t u32Addr)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync Assert(!(u32Addr & 0x3)); Assert(!fPrefetchable); Assert(!f64Bit);
ffb50166c9adb4ae583b914d405197035cf890advboxsync * Sets the sub-system vendor id config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param u16SubSysVendorId The sub-system vendor id.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetSubSystemVendorId(PPCIDEVICE pPciDev, uint16_t u16SubSysVendorId)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync PCIDevSetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, u16SubSysVendorId);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Gets the sub-system vendor id config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @returns the sub-system vendor id.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(uint16_t) PCIDevGetSubSystemVendorId(PPCIDEVICE pPciDev)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return PCIDevGetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Sets the sub-system id config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync * @param u16SubSystemId The sub-system id.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetSubSystemId(PPCIDEVICE pPciDev, uint16_t u16SubSystemId)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync PCIDevSetWord(pPciDev, VBOX_PCI_SUBSYSTEM_ID, u16SubSystemId);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Gets the sub-system id config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @returns the sub-system id.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(uint16_t) PCIDevGetSubSystemId(PPCIDEVICE pPciDev)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return PCIDevGetWord(pPciDev, VBOX_PCI_SUBSYSTEM_ID);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Sets offset to capability list.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param u8Offset The offset to capability list.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetCapabilityList(PPCIDEVICE pPciDev, uint8_t u8Offset)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync PCIDevSetByte(pPciDev, VBOX_PCI_CAPABILITY_LIST, u8Offset);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Returns offset to capability list.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @returns offset to capability list.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(uint8_t) PCIDevGetCapabilityList(PPCIDEVICE pPciDev)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return PCIDevGetByte(pPciDev, VBOX_PCI_CAPABILITY_LIST);
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync * Sets the interrupt line config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param u8Line The interrupt line.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIDevSetInterruptLine(PPCIDEVICE pPciDev, uint8_t u8Line)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync PCIDevSetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE, u8Line);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Gets the interrupt line config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @returns The interrupt line.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(uint8_t) PCIDevGetInterruptLine(PPCIDEVICE pPciDev)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE);
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * Sets the interrupt pin config register.
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync * @param pPciDev The PCI device.
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync * @param u8Pin The interrupt pin.
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsyncDECLINLINE(void) PCIDevSetInterruptPin(PPCIDEVICE pPciDev, uint8_t u8Pin)
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync PCIDevSetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN, u8Pin);
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync * Gets the interrupt pin config register.
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync * @returns The interrupt pin.
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync * @param pPciDev The PCI device.
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsyncDECLINLINE(uint8_t) PCIDevGetInterruptPin(PPCIDEVICE pPciDev)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN);
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsyncDECLINLINE(void) PCISetRequestedDevfunc(PPCIDEVICE pDev)
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync pDev->Int.s.uFlags |= PCIDEV_FLAG_REQUESTED_DEVFUNC;
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncDECLINLINE(void) PCIClearRequestedDevfunc(PPCIDEVICE pDev)
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync pDev->Int.s.uFlags &= ~PCIDEV_FLAG_REQUESTED_DEVFUNC;
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsyncDECLINLINE(bool) PCIIsRequestedDevfunc(PPCIDEVICE pDev)
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync return (pDev->Int.s.uFlags & PCIDEV_FLAG_REQUESTED_DEVFUNC) != 0;
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsyncDECLINLINE(void) PCISetPci2PciBridge(PPCIDEVICE pDev)
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync pDev->Int.s.uFlags |= PCIDEV_FLAG_PCI_TO_PCI_BRIDGE;
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsyncDECLINLINE(bool) PCIIsPci2PciBridge(PPCIDEVICE pDev)
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync return (pDev->Int.s.uFlags & PCIDEV_FLAG_PCI_TO_PCI_BRIDGE) != 0;
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync pDev->Int.s.uFlags |= PCIDEV_FLAG_PCI_EXPRESS_DEVICE;
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync return (pDev->Int.s.uFlags & PCIDEV_FLAG_PCI_EXPRESS_DEVICE) != 0;
750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncDECLINLINE(void) PCIClearMsiCapable(PPCIDEVICE pDev)
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync return (pDev->Int.s.uFlags & PCIDEV_FLAG_MSI_CAPABLE) != 0;
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncDECLINLINE(void) PCIClearMsixCapable(PPCIDEVICE pDev)
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return (pDev->Int.s.uFlags & PCIDEV_FLAG_MSIX_CAPABLE) != 0;
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync return true;
553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return false;
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync return true;
ffb50166c9adb4ae583b914d405197035cf890advboxsync return false;
ffb50166c9adb4ae583b914d405197035cf890advboxsync return true;
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync return false;
ffb50166c9adb4ae583b914d405197035cf890advboxsync return false;
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync bool valid() const
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync return (iBus != -1) && (iDevice != -1) && (iFn != -1);
c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync#endif /* __cplusplus */